diff --git a/doc/join_cn.md b/doc/join_cn.md index 37a35df..070448c 100644 --- a/doc/join_cn.md +++ b/doc/join_cn.md @@ -50,7 +50,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 ## 任务 -### uFTB +### 任务1. uFTB + +源代码地址: [FauFTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/uFTB) +功能描述文档：[uFTB分支预测器](https://open-verify.cc/xs-bpu/docs/modules/01_uftb/) +参考功能点文档：[uFTB功能列表](https://open-verify.cc/xs-bpu/docs/feature/01_uftbfeature/) 1. 完成对 uFTB 子预测器的代码及文档阅读，了解 uFTB 的工作原理及模块功能。明确 uFTB 使用的 FTB 项缓存的结构。 2. 根据给出的参考功能点，完善 uFTB 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 @@ -59,7 +63,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 5. 完成对 uFTB 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/uFTB-yourId.html` 查看本次测试报告内容。 6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。 -### TageSC +### 任务2. TageSC + +源代码地址: [TageSC.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/TageSC) +功能描述文档：[TAGE-SC 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/02_tage_sc/) +参考功能点文档：[TAGE-SC 功能列表](https://open-verify.cc/xs-bpu/docs/feature/03_tagescfeature/) 1. 完成对 TageSC 子预测器的代码及文档阅读，了解 Tage 及 SC 单个模块的工作原理及功能，再了解 TageSC 整体模块的功能。明确使用的 Tage 表项及 SC 表项的结构，以及分支折叠历史的工作原理。 2. 根据给出的参考功能点，完善 Tage、SC、TageSC 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 @@ -68,7 +76,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 5. 完成对 TageSC 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/TageSC-yourId.html` 查看本次测试报告内容。 6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。 -### FTB +### 任务3. FTB + +源代码地址: [FTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/FTB) +功能描述文档：[FTB 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/03_ftb/) +参考功能点文档：[FTB 功能列表](https://open-verify.cc/xs-bpu/docs/feature/02_ftbfeature/) 1. 完成对 FTB 子预测器的代码及文档阅读，了解 FTB 的工作原理及模块功能。明确 FTB 使用的 FTB 项缓存的结构，了解条件分支指令和间接跳转指令的不同。 2. 根据给出的参考功能点，完善 FTB 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 @@ -77,7 +89,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 5. 完成对 FTB 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/FTB-yourId.html` 查看本次测试报告内容。 6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。 -### ITTAGE +### 任务4. ITTAGE + +源代码地址: [ITTAGE.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/ITTAGE) +功能描述文档：[ITTAGE 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/04_ittage/) +参考功能点文档：[ITTAGE 功能列表](https://open-verify.cc/xs-bpu/docs/feature/04_ittagefeature/) 1. 完成对 ITTAGE 子预测器的代码及文档阅读，了解 ITTAGE 的工作原理及模块功能。明确 ITTAGE 使用的 Tage 表项的结构，了解 ITTAGE 的预测器结构。同时了解分支折叠历史的工作原理。 2. 根据给出的参考功能点，完善 ITTAGE 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 @@ -87,7 +103,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。 -### RAS +### 任务5. RAS + +源代码地址: [RAS.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/RAS) +功能描述文档：[RAS 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/05_ras/) +参考功能点文档：[RAS 功能列表](https://open-verify.cc/xs-bpu/docs/feature/05_rasfeature/) 1. 完成对 RAS 子预测器的代码及文档阅读，了解 RAS 的工作原理及模块功能。了解程序运行时栈帧的工作原理，再明确 RAS 的 RAS 栈的工作原理。最明确 RAS 的预测器如何为 call 和 ret 指令提供预测。 2. 根据给出的参考功能点，完善 RAS 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 @@ -96,7 +116,11 @@ Fork本仓库，然后在本地进行环境搭建，参与测试任务。 5. 完成对 RAS 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/RAS-yourId.html` 查看本次测试报告内容。 6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。 -### BPU Top +### 任务6. BPU Top + +源代码地址: [Predictor.sv & Composer.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/common) +功能描述文档：[BPU 顶层模块](https://open-verify.cc/xs-bpu/docs/modules/00_bpu_top/) +参考功能点文档：[BPU Top 功能列表](https://open-verify.cc/xs-bpu/docs/feature/00_bpufeature/) 1. 完成对 BPU Top 子预测器的代码及文档阅读，了解 BPU Top 的工作原理及模块功能。了解 BPU Top 的预测器结构，明确 BPU Top 的预测器如何为不同类型的分支提供预测。同时了解 BPU Top 如何与外界的 FTQ 模块进行交互。 2. 根据给出的参考功能点，完善 BPU Top 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。 diff --git a/rtl/FTB.txt b/rtl/FTB.txt index f60568f..5b267ac 100644 --- a/rtl/FTB.txt +++ b/rtl/FTB.txt @@ -1,9 +1,11 @@ ./rtl/FTB/FTBBank.sv ./rtl/FTB/FTBEntryGen.sv -./rtl/FTB/SRAMTemplate_9.sv +./rtl/FTB/SRAMTemplate_13.sv ./rtl/FTB/array_3.sv ./rtl/common/ext_sram.v ./rtl/common/DelayN_2.sv ./rtl/common/DelayN_4.sv ./rtl/common/DelayN_5.sv ./rtl/common/DelayN_6.sv +./rtl/common/DelayNWithValid.sv +./rtl/common/DelayNWithValid_1.sv diff --git a/rtl/FTB/FTB.sv b/rtl/FTB/FTB.sv index b984820..093778e 100644 --- a/rtl/FTB/FTB.sv +++ b/rtl/FTB/FTB.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,1123 +55,1135 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FTB( // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - input clock, - input reset, - input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [218:0] io_update_bits_meta // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module FTB( // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + input clock, // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + input reset, // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_btb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_s1_ready, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_old_entry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [5:0] io_perf_0_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_1_value // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] ); - wire _write_valid_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_valid; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [3:0] _delay2_entry_delay_io_out_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [11:0] _delay2_entry_delay_io_out_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [1:0] _delay2_entry_delay_io_out_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [3:0] _delay2_entry_delay_io_out_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [19:0] _delay2_entry_delay_io_out_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [1:0] _delay2_entry_delay_io_out_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [3:0] _delay2_entry_delay_io_out_pftAddr; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_carry; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_isCall; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_isRet; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_isJalr; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_always_taken_0; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _delay2_entry_delay_io_out_always_taken_1; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [38:0] _delay2_pc_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ftbBank_io_req_pc_ready; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [3:0] _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [19:0] _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [3:0] _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_read_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [1:0] _ftbBank_io_read_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire _ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [1:0] _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 - wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - reg s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg [3:0] s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 - reg s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg [3:0] s3_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - reg s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 - wire io_out_last_stage_meta_e_hit = - _ftbBank_io_read_hits_valid & io_ctrl_btb_enable; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43 - reg s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 - reg s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 - reg s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 - reg s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 - reg s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 - reg s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 - reg s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 - reg s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 - reg [25:0] higher_r; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 - wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 - wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 - reg [17:0] higher_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s2_full_pred_0_targets_1_output = + wire _write_valid_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _delay2_entry_pipMod_io_out_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [3:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [11:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [1:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [3:0] _delay2_entry_pipMod_io_out_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [19:0] _delay2_entry_pipMod_io_out_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [1:0] _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [3:0] _delay2_entry_pipMod_io_out_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _delay2_entry_pipMod_io_out_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire [40:0] _delay2_pc_pipMod_io_out_bits; // @[utility/src/main/scala/utility/Hold.scala:130:24] + wire _ftbBank_io_req_pc_ready; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [3:0] _ftbBank_io_read_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [19:0] _ftbBank_io_read_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [3:0] _ftbBank_io_read_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_read_hits_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [1:0] _ftbBank_io_read_hits_bits; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire _ftbBank_io_update_hits_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [1:0] _ftbBank_io_update_hits_bits; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] + wire [35:0] _reset_vector_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + reg [40:0] s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s2_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s3_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + reg REG_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + reg s2_ftb_entry_dup_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_0_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_1_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_1_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_2_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_2_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg [3:0] s2_ftb_entry_dup_3_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s2_ftb_entry_dup_3_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55] + reg s3_ftb_entry_dup_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_0_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_1_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_1_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_2_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_2_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg [3:0] s3_ftb_entry_dup_3_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + reg s3_ftb_entry_dup_3_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:429:88] + wire s1_hit = _ftbBank_io_read_hits_valid & io_ctrl_btb_enable; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43] + reg s2_hit_dup_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49] + reg s2_hit_dup_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49] + reg s2_hit_dup_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49] + reg s2_hit_dup_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49] + reg s3_hit_dup_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:433:76] + reg s3_hit_dup_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:433:76] + reg s3_hit_dup_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:433:76] + reg s3_hit_dup_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:433:76] + reg [27:0] higher_r; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55] + wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55] + wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55] + reg [19:0] higher_r_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s2_full_pred_0_targets_1_0 = {s2_ftb_entry_dup_0_tailSlot_sharing - ? {(_target_T_18 ? higher_plus_one_r_1 : 26'h0) - | (_target_T_19 ? higher_minus_one_r_1 : 26'h0) - | (_target_T_20 ? higher_r_1 : 26'h0), + ? {(_target_T_18 ? higher_plus_one_r_1 : 28'h0) + | (_target_T_19 ? higher_minus_one_r_1 : 28'h0) + | (_target_T_20 ? higher_r_1 : 28'h0), s2_ftb_entry_dup_0_tailSlot_lower[11:0]} - : {(_target_T_18 ? higher_plus_one_r_2 : 18'h0) - | (_target_T_19 ? higher_minus_one_r_2 : 18'h0) - | (_target_T_20 ? higher_r_2 : 18'h0), + : {(_target_T_18 ? higher_plus_one_r_2 : 20'h0) + | (_target_T_19 ? higher_minus_one_r_2 : 20'h0) + | (_target_T_20 ? higher_r_2 : 20'h0), s2_ftb_entry_dup_0_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 - reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 - reg [25:0] higher_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 - wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 - wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 - reg [17:0] higher_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s2_full_pred_1_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55] + reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36] + reg [27:0] higher_r_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_4; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_4; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_4; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55] + wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55] + wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55] + reg [19:0] higher_r_5; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_5; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_5; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s2_full_pred_1_targets_1_0 = {s2_ftb_entry_dup_1_tailSlot_sharing - ? {(_target_T_45 ? higher_plus_one_r_4 : 26'h0) - | (_target_T_46 ? higher_minus_one_r_4 : 26'h0) - | (_target_T_47 ? higher_r_4 : 26'h0), + ? {(_target_T_45 ? higher_plus_one_r_4 : 28'h0) + | (_target_T_46 ? higher_minus_one_r_4 : 28'h0) + | (_target_T_47 ? higher_r_4 : 28'h0), s2_ftb_entry_dup_1_tailSlot_lower[11:0]} - : {(_target_T_45 ? higher_plus_one_r_5 : 18'h0) - | (_target_T_46 ? higher_minus_one_r_5 : 18'h0) - | (_target_T_47 ? higher_r_5 : 18'h0), + : {(_target_T_45 ? higher_plus_one_r_5 : 20'h0) + | (_target_T_46 ? higher_minus_one_r_5 : 20'h0) + | (_target_T_47 ? higher_r_5 : 20'h0), s2_ftb_entry_dup_1_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 - reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 - reg [25:0] higher_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 - wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 - wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 - reg [17:0] higher_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s2_full_pred_2_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55] + reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36] + reg [27:0] higher_r_6; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_6; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_6; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_7; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_7; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_7; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55] + wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55] + wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55] + reg [19:0] higher_r_8; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_8; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_8; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s2_full_pred_2_targets_1_0 = {s2_ftb_entry_dup_2_tailSlot_sharing - ? {(_target_T_72 ? higher_plus_one_r_7 : 26'h0) - | (_target_T_73 ? higher_minus_one_r_7 : 26'h0) - | (_target_T_74 ? higher_r_7 : 26'h0), + ? {(_target_T_72 ? higher_plus_one_r_7 : 28'h0) + | (_target_T_73 ? higher_minus_one_r_7 : 28'h0) + | (_target_T_74 ? higher_r_7 : 28'h0), s2_ftb_entry_dup_2_tailSlot_lower[11:0]} - : {(_target_T_72 ? higher_plus_one_r_8 : 18'h0) - | (_target_T_73 ? higher_minus_one_r_8 : 18'h0) - | (_target_T_74 ? higher_r_8 : 18'h0), + : {(_target_T_72 ? higher_plus_one_r_8 : 20'h0) + | (_target_T_73 ? higher_minus_one_r_8 : 20'h0) + | (_target_T_74 ? higher_r_8 : 20'h0), s2_ftb_entry_dup_2_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 - reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 - reg [25:0] higher_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 - wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 - wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 - reg [17:0] higher_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s2_full_pred_3_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55] + reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36] + reg [27:0] higher_r_9; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_9; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_9; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_10; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_10; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_10; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55] + wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55] + wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55] + reg [19:0] higher_r_11; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_11; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_11; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s2_full_pred_3_targets_1_0 = {s2_ftb_entry_dup_3_tailSlot_sharing - ? {(_target_T_99 ? higher_plus_one_r_10 : 26'h0) - | (_target_T_100 ? higher_minus_one_r_10 : 26'h0) - | (_target_T_101 ? higher_r_10 : 26'h0), + ? {(_target_T_99 ? higher_plus_one_r_10 : 28'h0) + | (_target_T_100 ? higher_minus_one_r_10 : 28'h0) + | (_target_T_101 ? higher_r_10 : 28'h0), s2_ftb_entry_dup_3_tailSlot_lower[11:0]} - : {(_target_T_99 ? higher_plus_one_r_11 : 18'h0) - | (_target_T_100 ? higher_minus_one_r_11 : 18'h0) - | (_target_T_101 ? higher_r_11 : 18'h0), + : {(_target_T_99 ? higher_plus_one_r_11 : 20'h0) + | (_target_T_100 ? higher_minus_one_r_11 : 20'h0) + | (_target_T_101 ? higher_r_11 : 20'h0), s2_ftb_entry_dup_3_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 - wire _io_out_s2_full_pred_3_fallThroughErr_output = - {1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 - reg [25:0] higher_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 - wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 - wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 - reg [17:0] higher_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s3_full_pred_0_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55] + wire io_out_s2_full_pred_3_fallThroughErr_0 = + {1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36] + reg [27:0] higher_r_12; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_12; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_12; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_13; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_13; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_13; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88] + wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88] + wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88] + reg [19:0] higher_r_14; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_14; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_14; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s3_full_pred_0_targets_1_0 = {s3_ftb_entry_dup_0_tailSlot_sharing - ? {(_target_T_126 ? higher_plus_one_r_13 : 26'h0) - | (_target_T_127 ? higher_minus_one_r_13 : 26'h0) - | (_target_T_128 ? higher_r_13 : 26'h0), + ? {(_target_T_126 ? higher_plus_one_r_13 : 28'h0) + | (_target_T_127 ? higher_minus_one_r_13 : 28'h0) + | (_target_T_128 ? higher_r_13 : 28'h0), s3_ftb_entry_dup_0_tailSlot_lower[11:0]} - : {(_target_T_126 ? higher_plus_one_r_14 : 18'h0) - | (_target_T_127 ? higher_minus_one_r_14 : 18'h0) - | (_target_T_128 ? higher_r_14 : 18'h0), + : {(_target_T_126 ? higher_plus_one_r_14 : 20'h0) + | (_target_T_127 ? higher_minus_one_r_14 : 20'h0) + | (_target_T_128 ? higher_r_14 : 20'h0), s3_ftb_entry_dup_0_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 - wire _io_out_s3_full_pred_0_fallThroughErr_output = - {1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - reg [25:0] higher_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 - wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 - wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 - reg [17:0] higher_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s3_full_pred_1_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88] + wire io_out_s3_full_pred_0_fallThroughErr_0 = + {1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + reg [27:0] higher_r_15; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_15; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_15; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_16; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_16; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_16; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88] + wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88] + wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88] + reg [19:0] higher_r_17; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_17; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_17; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s3_full_pred_1_targets_1_0 = {s3_ftb_entry_dup_1_tailSlot_sharing - ? {(_target_T_153 ? higher_plus_one_r_16 : 26'h0) - | (_target_T_154 ? higher_minus_one_r_16 : 26'h0) - | (_target_T_155 ? higher_r_16 : 26'h0), + ? {(_target_T_153 ? higher_plus_one_r_16 : 28'h0) + | (_target_T_154 ? higher_minus_one_r_16 : 28'h0) + | (_target_T_155 ? higher_r_16 : 28'h0), s3_ftb_entry_dup_1_tailSlot_lower[11:0]} - : {(_target_T_153 ? higher_plus_one_r_17 : 18'h0) - | (_target_T_154 ? higher_minus_one_r_17 : 18'h0) - | (_target_T_155 ? higher_r_17 : 18'h0), + : {(_target_T_153 ? higher_plus_one_r_17 : 20'h0) + | (_target_T_154 ? higher_minus_one_r_17 : 20'h0) + | (_target_T_155 ? higher_r_17 : 20'h0), s3_ftb_entry_dup_1_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 - wire _io_out_s3_full_pred_1_fallThroughErr_output = - {1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - reg [25:0] higher_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 - wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 - wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 - reg [17:0] higher_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s3_full_pred_2_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88] + wire io_out_s3_full_pred_1_fallThroughErr_0 = + {1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + reg [27:0] higher_r_18; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_18; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_18; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_19; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_19; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_19; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88] + wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88] + wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88] + reg [19:0] higher_r_20; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_20; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_20; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s3_full_pred_2_targets_1_0 = {s3_ftb_entry_dup_2_tailSlot_sharing - ? {(_target_T_180 ? higher_plus_one_r_19 : 26'h0) - | (_target_T_181 ? higher_minus_one_r_19 : 26'h0) - | (_target_T_182 ? higher_r_19 : 26'h0), + ? {(_target_T_180 ? higher_plus_one_r_19 : 28'h0) + | (_target_T_181 ? higher_minus_one_r_19 : 28'h0) + | (_target_T_182 ? higher_r_19 : 28'h0), s3_ftb_entry_dup_2_tailSlot_lower[11:0]} - : {(_target_T_180 ? higher_plus_one_r_20 : 18'h0) - | (_target_T_181 ? higher_minus_one_r_20 : 18'h0) - | (_target_T_182 ? higher_r_20 : 18'h0), + : {(_target_T_180 ? higher_plus_one_r_20 : 20'h0) + | (_target_T_181 ? higher_minus_one_r_20 : 20'h0) + | (_target_T_182 ? higher_r_20 : 20'h0), s3_ftb_entry_dup_2_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 - wire _io_out_s3_full_pred_2_fallThroughErr_output = - {1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - reg [25:0] higher_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - reg [25:0] higher_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [25:0] higher_plus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [25:0] higher_minus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 - wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 - wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 - reg [17:0] higher_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 - reg [17:0] higher_plus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 - reg [17:0] higher_minus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 - wire [38:0] _io_out_s3_full_pred_3_targets_1_output = + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88] + wire io_out_s3_full_pred_2_fallThroughErr_0 = + {1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + reg [27:0] higher_r_21; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_21; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_21; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + reg [27:0] higher_r_22; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [27:0] higher_plus_one_r_22; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [27:0] higher_minus_one_r_22; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88] + wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88] + wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88] + reg [19:0] higher_r_23; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28] + reg [19:0] higher_plus_one_r_23; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37] + reg [19:0] higher_minus_one_r_23; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38] + wire [40:0] io_out_s3_full_pred_3_targets_1_0 = {s3_ftb_entry_dup_3_tailSlot_sharing - ? {(_target_T_207 ? higher_plus_one_r_22 : 26'h0) - | (_target_T_208 ? higher_minus_one_r_22 : 26'h0) - | (_target_T_209 ? higher_r_22 : 26'h0), + ? {(_target_T_207 ? higher_plus_one_r_22 : 28'h0) + | (_target_T_208 ? higher_minus_one_r_22 : 28'h0) + | (_target_T_209 ? higher_r_22 : 28'h0), s3_ftb_entry_dup_3_tailSlot_lower[11:0]} - : {(_target_T_207 ? higher_plus_one_r_23 : 18'h0) - | (_target_T_208 ? higher_minus_one_r_23 : 18'h0) - | (_target_T_209 ? higher_r_23 : 18'h0), + : {(_target_T_207 ? higher_plus_one_r_23 : 20'h0) + | (_target_T_208 ? higher_minus_one_r_23 : 20'h0) + | (_target_T_209 ? higher_r_23 : 20'h0), s3_ftb_entry_dup_3_tailSlot_lower}, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 - wire _io_out_s3_full_pred_3_fallThroughErr_output = - {1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - reg [2:0] io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:48 - reg [2:0] io_out_last_stage_meta_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:458:38 - wire u_valid = io_update_valid & ~io_update_bits_old_entry; // src/main/scala/xiangshan/frontend/FTB.scala:474:{33,36} - wire update_now = u_valid & io_update_bits_meta[0]; // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :480:28 - wire update_need_read = u_valid & ~(io_update_bits_meta[0]); // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:{34,37} - reg io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:483:76 - wire [38:0] _ftb_write_tag_WIRE_2 = - update_now ? io_update_bits_pc : _delay2_pc_delay_io_out; // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :492:40, utility/src/main/scala/utility/Hold.scala:97:23 - reg [1:0] ftbBank_io_update_write_way_REG; // src/main/scala/xiangshan/frontend/FTB.scala:499:76 - reg ftbBank_io_update_write_alloc_REG; // src/main/scala/xiangshan/frontend/FTB.scala:500:76 - wire [38:0] _GEN = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 - always @(posedge clock) begin - if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - s1_pc_dup_0 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_1 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_2 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_3 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88] + wire io_out_s3_full_pred_3_fallThroughErr_0 = + {1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + reg [2:0] io_out_last_stage_meta_r; // @[src/main/scala/xiangshan/frontend/FTB.scala:458:48] + reg [2:0] io_out_last_stage_meta_r_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:458:38] + wire u_valid = io_update_valid & ~io_update_bits_old_entry; // @[src/main/scala/xiangshan/frontend/FTB.scala:474:{33,36}] + wire update_now = u_valid & io_update_bits_meta[0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :480:28] + wire update_need_read = u_valid & ~(io_update_bits_meta[0]); // @[src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:{34,37}] + reg io_s1_ready_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:483:76] + wire [40:0] _ftbBank_io_update_pc_T = + update_now ? io_update_bits_pc : _delay2_pc_pipMod_io_out_bits; // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :492:40, utility/src/main/scala/utility/Hold.scala:130:24] + reg [1:0] ftbBank_io_update_write_way_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:499:76] + reg ftbBank_io_update_write_alloc_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:500:76] + reg io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + wire [40:0] _GEN = {5'h0, _reset_vector_delay_io_out}; // @[src/main/scala/xiangshan/frontend/BPU.scala:192:39, utility/src/main/scala/utility/Hold.scala:100:23] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + if (REG_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + s1_pc_dup_0 <= _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_1 <= _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_2 <= _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_3 <= _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] end - else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + else begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + if (io_s0_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] end - if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + if (io_s1_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_0 <= s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] s2_ftb_entry_dup_0_last_may_be_rvi_call <= - _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - higher_r <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_1 <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_1 <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_1 <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_2 <= s1_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_2 <= 18'(s1_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_2 <= 18'(s1_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 - io_out_last_stage_meta_r <= - {_ftbBank_io_read_hits_bits, io_out_last_stage_meta_e_hit}; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43, :458:{48,92} + _ftbBank_io_read_resp_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + higher_r <= s1_pc_dup_0[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r <= 28'(s1_pc_dup_0[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r <= 28'(s1_pc_dup_0[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_1 <= s1_pc_dup_0[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_1 <= 28'(s1_pc_dup_0[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_1 <= 28'(s1_pc_dup_0[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_2 <= s1_pc_dup_0[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_2 <= 20'(s1_pc_dup_0[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_2 <= 20'(s1_pc_dup_0[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23] + io_out_last_stage_meta_r <= {_ftbBank_io_read_hits_bits, s1_hit}; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43, :458:{48,92}] end - if (io_s1_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - higher_r_3 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_3 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_3 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_4 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_4 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_4 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_5 <= s1_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_5 <= 18'(s1_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_5 <= 18'(s1_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + if (io_s1_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_1 <= s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + higher_r_3 <= s1_pc_dup_1[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_3 <= 28'(s1_pc_dup_1[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_3 <= 28'(s1_pc_dup_1[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_4 <= s1_pc_dup_1[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_4 <= 28'(s1_pc_dup_1[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_4 <= 28'(s1_pc_dup_1[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_5 <= s1_pc_dup_1[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_5 <= 20'(s1_pc_dup_1[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_5 <= 20'(s1_pc_dup_1[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23] end - if (io_s1_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + if (io_s1_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_2 <= s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] s2_ftb_entry_dup_2_last_may_be_rvi_call <= - _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - higher_r_6 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_6 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_6 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_7 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_7 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_7 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_8 <= s1_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_8 <= 18'(s1_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_8 <= 18'(s1_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + _ftbBank_io_read_resp_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + higher_r_6 <= s1_pc_dup_2[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_6 <= 28'(s1_pc_dup_2[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_6 <= 28'(s1_pc_dup_2[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_7 <= s1_pc_dup_2[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_7 <= 28'(s1_pc_dup_2[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_7 <= 28'(s1_pc_dup_2[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_8 <= s1_pc_dup_2[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_8 <= 20'(s1_pc_dup_2[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_8 <= 20'(s1_pc_dup_2[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23] end - if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 - higher_r_9 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_9 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_9 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_10 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_10 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_10 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - higher_r_11 <= s1_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 - higher_plus_one_r_11 <= 18'(s1_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} - higher_minus_one_r_11 <= 18'(s1_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} - io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + if (io_s1_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_3 <= s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55] + higher_r_9 <= s1_pc_dup_3[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_9 <= 28'(s1_pc_dup_3[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_9 <= 28'(s1_pc_dup_3[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_10 <= s1_pc_dup_3[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_10 <= 28'(s1_pc_dup_3[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_10 <= 28'(s1_pc_dup_3[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + higher_r_11 <= s1_pc_dup_3[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28] + higher_plus_one_r_11 <= 20'(s1_pc_dup_3[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}] + higher_minus_one_r_11 <= 20'(s1_pc_dup_3[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}] + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23] end - if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - higher_r_12 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_12 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_12 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_13 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_13 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_13 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_14 <= s2_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_14 <= 18'(s2_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_14 <= 18'(s2_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:{38,48} + if (io_s2_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_0 <= s2_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + higher_r_12 <= s2_pc_dup_0[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_12 <= 28'(s2_pc_dup_0[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_12 <= 28'(s2_pc_dup_0[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_13 <= s2_pc_dup_0[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_13 <= 28'(s2_pc_dup_0[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_13 <= 28'(s2_pc_dup_0[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_14 <= s2_pc_dup_0[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_14 <= 20'(s2_pc_dup_0[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_14 <= 20'(s2_pc_dup_0[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r; // @[src/main/scala/xiangshan/frontend/FTB.scala:458:{38,48}] end - if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - higher_r_15 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_15 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_15 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_16 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_16 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_16 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_17 <= s2_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_17 <= 18'(s2_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_17 <= 18'(s2_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + if (io_s2_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_1 <= s2_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + higher_r_15 <= s2_pc_dup_1[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_15 <= 28'(s2_pc_dup_1[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_15 <= 28'(s2_pc_dup_1[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_16 <= s2_pc_dup_1[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_16 <= 28'(s2_pc_dup_1[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_16 <= 28'(s2_pc_dup_1[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_17 <= s2_pc_dup_1[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_17 <= 20'(s2_pc_dup_1[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_17 <= 20'(s2_pc_dup_1[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] end - if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - higher_r_18 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_18 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_18 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_19 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_19 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_19 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_20 <= s2_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_20 <= 18'(s2_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_20 <= 18'(s2_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + if (io_s2_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_2 <= s2_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + higher_r_18 <= s2_pc_dup_2[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_18 <= 28'(s2_pc_dup_2[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_18 <= 28'(s2_pc_dup_2[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_19 <= s2_pc_dup_2[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_19 <= 28'(s2_pc_dup_2[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_19 <= 28'(s2_pc_dup_2[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_20 <= s2_pc_dup_2[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_20 <= 20'(s2_pc_dup_2[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_20 <= 20'(s2_pc_dup_2[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] end - if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 - higher_r_21 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_21 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_21 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_22 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_22 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_22 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} - higher_r_23 <= s2_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 - higher_plus_one_r_23 <= 18'(s2_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} - higher_minus_one_r_23 <= 18'(s2_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + if (io_s2_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_3 <= s2_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88] + higher_r_21 <= s2_pc_dup_3[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_21 <= 28'(s2_pc_dup_3[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_21 <= 28'(s2_pc_dup_3[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_22 <= s2_pc_dup_3[40:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_22 <= 28'(s2_pc_dup_3[40:13] + 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_22 <= 28'(s2_pc_dup_3[40:13] - 28'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] + higher_r_23 <= s2_pc_dup_3[40:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28] + higher_plus_one_r_23 <= 20'(s2_pc_dup_3[40:21] + 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}] + higher_minus_one_r_23 <= 20'(s2_pc_dup_3[40:21] - 20'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}] end - REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} - io_s1_ready_REG <= update_need_read; // src/main/scala/xiangshan/frontend/FTB.scala:481:34, :483:76 - ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :499:76 - ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :500:{76,77} + REG <= reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + REG_1 <= REG & ~reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24,39,42}] + io_s1_ready_REG <= update_need_read; // @[src/main/scala/xiangshan/frontend/FTB.scala:481:34, :483:76] + ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :499:76] + ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23, :500:{76,77}] + io_perf_0_value_REG <= io_update_valid & io_update_bits_meta[0]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FTB.scala:473:36, :515:55] + io_perf_0_value_REG_1 <= io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_1_value_REG <= io_update_valid & ~(io_update_bits_meta[0]); // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FTB.scala:473:36, :481:37, :524:54] + io_perf_1_value_REG_1 <= io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) begin - s2_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s3_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_hit_dup_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s3_hit_dup_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] end - else begin - if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_hit_dup_0 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 - if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_hit_dup_1 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 - if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_hit_dup_2 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 - if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_hit_dup_3 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 - if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_hit_dup_0 <= s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 - if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_hit_dup_1 <= s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 - if (io_s2_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_hit_dup_2 <= s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 - if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_hit_dup_3 <= s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 + else begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + if (io_s1_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_hit_dup_0 <= s1_hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49] + if (io_s1_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_hit_dup_1 <= s1_hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49] + if (io_s1_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_hit_dup_2 <= s1_hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49] + if (io_s1_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_hit_dup_3 <= s1_hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49] + if (io_s2_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_hit_dup_0 <= s2_hit_dup_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76] + if (io_s2_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_hit_dup_1 <= s2_hit_dup_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76] + if (io_s2_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_hit_dup_2 <= s2_hit_dup_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76] + if (io_s2_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_hit_dup_3 <= s2_hit_dup_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:84]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - initial begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + logic [31:0] _RANDOM[0:90]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + initial begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - for (logic [6:0] i = 7'h0; i < 7'h55; i += 7'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - end // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s1_pc_dup_1 = {_RANDOM[7'h1][31:7], _RANDOM[7'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s1_pc_dup_2 = {_RANDOM[7'h2][31:14], _RANDOM[7'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s1_pc_dup_3 = {_RANDOM[7'h3][31:21], _RANDOM[7'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_pc_dup_0 = {_RANDOM[7'h4][31:28], _RANDOM[7'h5], _RANDOM[7'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_pc_dup_1 = {_RANDOM[7'h6][31:3], _RANDOM[7'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_pc_dup_2 = {_RANDOM[7'h7][31:10], _RANDOM[7'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_pc_dup_3 = {_RANDOM[7'h8][31:17], _RANDOM[7'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s3_pc_dup_0 = {_RANDOM[7'h9][31:24], _RANDOM[7'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s3_pc_dup_1 = {_RANDOM[7'hA][31], _RANDOM[7'hB], _RANDOM[7'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s3_pc_dup_2 = {_RANDOM[7'hC][31:6], _RANDOM[7'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s3_pc_dup_3 = {_RANDOM[7'hD][31:13], _RANDOM[7'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - REG = _RANDOM[7'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - REG_1 = _RANDOM[7'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_ftb_entry_dup_0_valid = _RANDOM[7'hE][23]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hE][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_brSlots_0_lower = {_RANDOM[7'hE][31:28], _RANDOM[7'hF][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'hF][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'hF][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'hF][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'hF][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'hF][31:16], _RANDOM[7'h10][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h10][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_carry = _RANDOM[7'h10][12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_isCall = _RANDOM[7'h10][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_isRet = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h10][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h10][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h10][17]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h10][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h10][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_brSlots_0_lower = {_RANDOM[7'h10][31:24], _RANDOM[7'h11][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h11][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h11][31:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_carry = _RANDOM[7'h12][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h12][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h12][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h12][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h12][31:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h13][27:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h13][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h13][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h13][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h14][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h14][9]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h14][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h14][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h14][27:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h14][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h14][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h15][23:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h15][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h15][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h15][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h15][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h16][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h16][23:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h16][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h16][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h16][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h16][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 - s3_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h17][19:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h17][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h17][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h17][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h17][27:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_carry = _RANDOM[7'h17][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_isCall = _RANDOM[7'h17][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_isRet = _RANDOM[7'h17][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h17][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][1]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h18][19:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h18][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h18][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h18][31:28], _RANDOM[7'h19][15:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h19][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h19][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h19][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_carry = _RANDOM[7'h19][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h19][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h19][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h1A][15:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1A][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1A][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1A][31:24], _RANDOM[7'h1B][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1B][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1B][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1B][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1B][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_carry = _RANDOM[7'h1B][20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1B][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1B][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1B][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1B][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1B][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1B][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h1C][11:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1C][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1C][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1C][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h1C][31:20], _RANDOM[7'h1D][7:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1D][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1D][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1D][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1D][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_carry = _RANDOM[7'h1D][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1D][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1D][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - s2_hit_dup_0 = _RANDOM[7'h1D][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 - s2_hit_dup_1 = _RANDOM[7'h1D][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 - s2_hit_dup_2 = _RANDOM[7'h1D][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 - s2_hit_dup_3 = _RANDOM[7'h1D][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 - s3_hit_dup_0 = _RANDOM[7'h1D][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 - s3_hit_dup_1 = _RANDOM[7'h1D][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 - s3_hit_dup_2 = _RANDOM[7'h1D][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 - s3_hit_dup_3 = _RANDOM[7'h1D][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 - higher_r = {_RANDOM[7'h1D][31], _RANDOM[7'h1E][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7, :429:88 - higher_plus_one_r = {_RANDOM[7'h1E][31:25], _RANDOM[7'h1F][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_1 = {_RANDOM[7'h20][31:13], _RANDOM[7'h21][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_1 = {_RANDOM[7'h21][31:7], _RANDOM[7'h22][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_1 = _RANDOM[7'h22][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_2 = {_RANDOM[7'h22][31:27], _RANDOM[7'h23][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_plus_one_r_2 = _RANDOM[7'h23][30:13]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h24][17]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 - higher_r_3 = {_RANDOM[7'h24][31:18], _RANDOM[7'h25][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_3 = {_RANDOM[7'h25][31:12], _RANDOM[7'h26][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_3 = _RANDOM[7'h26][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_4 = _RANDOM[7'h27][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7 - higher_plus_one_r_4 = {_RANDOM[7'h27][31:26], _RANDOM[7'h28][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_4 = {_RANDOM[7'h28][31:20], _RANDOM[7'h29][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_5 = _RANDOM[7'h29][31:14]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_5 = _RANDOM[7'h2A][17:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7 - higher_minus_one_r_5 = {_RANDOM[7'h2A][31:18], _RANDOM[7'h2B][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2B][4]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 - higher_r_6 = _RANDOM[7'h2B][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_6 = {_RANDOM[7'h2B][31], _RANDOM[7'h2C][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_minus_one_r_6 = {_RANDOM[7'h2C][31:25], _RANDOM[7'h2D][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_7 = {_RANDOM[7'h2D][31:19], _RANDOM[7'h2E][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_7 = {_RANDOM[7'h2E][31:13], _RANDOM[7'h2F][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_7 = {_RANDOM[7'h2F][31:7], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_8 = _RANDOM[7'h30][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_8 = {_RANDOM[7'h30][31:19], _RANDOM[7'h31][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_minus_one_r_8 = _RANDOM[7'h31][22:5]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h31][23]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :177:36, :284:7 - higher_r_9 = {_RANDOM[7'h31][31:24], _RANDOM[7'h32][17:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_plus_one_r_9 = {_RANDOM[7'h32][31:18], _RANDOM[7'h33][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_9 = {_RANDOM[7'h33][31:12], _RANDOM[7'h34][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_10 = _RANDOM[7'h34][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_10 = _RANDOM[7'h35][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7 - higher_minus_one_r_10 = {_RANDOM[7'h35][31:26], _RANDOM[7'h36][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_11 = {_RANDOM[7'h36][31:20], _RANDOM[7'h37][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_11 = _RANDOM[7'h37][23:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_11 = {_RANDOM[7'h37][31:24], _RANDOM[7'h38][9:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h38][10]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 - higher_r_12 = {_RANDOM[7'h38][31:11], _RANDOM[7'h39][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_12 = _RANDOM[7'h39][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_12 = {_RANDOM[7'h39][31], _RANDOM[7'h3A][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_r_13 = {_RANDOM[7'h3A][31:25], _RANDOM[7'h3B][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_13 = {_RANDOM[7'h3B][31:19], _RANDOM[7'h3C][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_13 = {_RANDOM[7'h3C][31:13], _RANDOM[7'h3D][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_14 = _RANDOM[7'h3D][24:7]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_14 = {_RANDOM[7'h3D][31:25], _RANDOM[7'h3E][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_minus_one_r_14 = _RANDOM[7'h3E][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_15 = {_RANDOM[7'h3E][31:29], _RANDOM[7'h3F][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_plus_one_r_15 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_15 = {_RANDOM[7'h40][31:17], _RANDOM[7'h41][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_16 = {_RANDOM[7'h41][31:11], _RANDOM[7'h42][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_16 = _RANDOM[7'h42][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_16 = {_RANDOM[7'h42][31], _RANDOM[7'h43][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_r_17 = {_RANDOM[7'h43][31:25], _RANDOM[7'h44][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_17 = _RANDOM[7'h44][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_17 = {_RANDOM[7'h44][31:29], _RANDOM[7'h45][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_r_18 = {_RANDOM[7'h45][31:15], _RANDOM[7'h46][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_18 = {_RANDOM[7'h46][31:9], _RANDOM[7'h47][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_18 = _RANDOM[7'h47][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_19 = {_RANDOM[7'h47][31:29], _RANDOM[7'h48][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_plus_one_r_19 = {_RANDOM[7'h48][31:23], _RANDOM[7'h49][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_19 = {_RANDOM[7'h49][31:17], _RANDOM[7'h4A][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_20 = _RANDOM[7'h4A][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_20 = {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_minus_one_r_20 = {_RANDOM[7'h4B][31:15], _RANDOM[7'h4C][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_21 = _RANDOM[7'h4C][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_21 = {_RANDOM[7'h4C][31:27], _RANDOM[7'h4D][20:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_minus_one_r_21 = {_RANDOM[7'h4D][31:21], _RANDOM[7'h4E][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_22 = {_RANDOM[7'h4E][31:15], _RANDOM[7'h4F][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 - higher_plus_one_r_22 = {_RANDOM[7'h4F][31:9], _RANDOM[7'h50][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_22 = _RANDOM[7'h50][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - higher_r_23 = {_RANDOM[7'h50][31:29], _RANDOM[7'h51][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_plus_one_r_23 = {_RANDOM[7'h51][31:15], _RANDOM[7'h52][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 - higher_minus_one_r_23 = _RANDOM[7'h52][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 - io_out_last_stage_meta_r = _RANDOM[7'h54][21:19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48 - io_out_last_stage_meta_r_1 = _RANDOM[7'h54][24:22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{38,48} - io_s1_ready_REG = _RANDOM[7'h54][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :483:76 - ftbBank_io_update_write_way_REG = _RANDOM[7'h54][27:26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :499:76 - ftbBank_io_update_write_alloc_REG = _RANDOM[7'h54][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :500:76 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + for (logic [6:0] i = 7'h0; i < 7'h5B; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + end // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s1_pc_dup_1 = {_RANDOM[7'h1][31:9], _RANDOM[7'h2][17:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s1_pc_dup_2 = {_RANDOM[7'h2][31:18], _RANDOM[7'h3][26:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s1_pc_dup_3 = {_RANDOM[7'h3][31:27], _RANDOM[7'h4], _RANDOM[7'h5][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_pc_dup_0 = {_RANDOM[7'h5][31:4], _RANDOM[7'h6][12:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_pc_dup_1 = {_RANDOM[7'h6][31:13], _RANDOM[7'h7][21:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_pc_dup_2 = {_RANDOM[7'h7][31:22], _RANDOM[7'h8][30:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_pc_dup_3 = {_RANDOM[7'h8][31], _RANDOM[7'h9], _RANDOM[7'hA][7:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s3_pc_dup_0 = {_RANDOM[7'hA][31:8], _RANDOM[7'hB][16:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s3_pc_dup_1 = {_RANDOM[7'hB][31:17], _RANDOM[7'hC][25:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s3_pc_dup_2 = {_RANDOM[7'hC][31:26], _RANDOM[7'hD], _RANDOM[7'hE][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s3_pc_dup_3 = {_RANDOM[7'hE][31:3], _RANDOM[7'hF][11:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + REG = _RANDOM[7'hF][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, :191:24, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + REG_1 = _RANDOM[7'hF][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, :191:16, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_ftb_entry_dup_0_valid = _RANDOM[7'hF][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hF][19:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'hF][31:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h10][1:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h10][2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h10][3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h10][7:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h10][27:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][29:28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][30]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][31]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h11][3:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_carry = _RANDOM[7'h11][4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_isCall = _RANDOM[7'h11][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_isRet = _RANDOM[7'h11][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h11][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h11][8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h11][9]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h11][10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h11][15:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h11][27:16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][29:28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][31]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h12][3:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h12][23:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][25:24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][26]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][31:28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_carry = _RANDOM[7'h13][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h13][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h13][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h13][11:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h13][23:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][25:24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][31:28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h14][19:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h14][21:20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h14][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h14][23]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][27:24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][29]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][30]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][31]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h15][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h15][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h15][2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h15][7:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h15][19:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h15][21:20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h15][23]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][27:24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h15][31:28], _RANDOM[7'h16][15:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h16][17:16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h16][18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h16][19]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h16][23:20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][29]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][30]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][31]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88] + s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h17][3:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h17][15:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h17][17:16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h17][18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h17][19]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h17][23:20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'h17][31:24], _RANDOM[7'h18][11:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h18][13:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h18][14]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h18][15]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h18][19:16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_carry = _RANDOM[7'h18][20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_isCall = _RANDOM[7'h18][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_isRet = _RANDOM[7'h18][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h18][23]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][25]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][26]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h19][11:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h19][13:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h19][15]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h19][31:20], _RANDOM[7'h1A][7:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h1A][9:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h1A][10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h1A][11]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h1A][15:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_carry = _RANDOM[7'h1A][16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h1A][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h1A][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_brSlots_0_lower = {_RANDOM[7'h1A][31:28], _RANDOM[7'h1B][7:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1B][9:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1B][11]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1B][31:16], _RANDOM[7'h1C][3:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1C][5:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1C][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1C][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1C][11:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_carry = _RANDOM[7'h1C][12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1C][13]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1C][14]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1C][15]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1C][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1C][18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1C][23:20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_brSlots_0_lower = {_RANDOM[7'h1C][31:24], _RANDOM[7'h1D][3:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1D][5:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1D][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1D][11:8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h1D][31:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1E][1:0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1E][2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1E][3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1E][7:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_carry = _RANDOM[7'h1E][8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1E][13]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1E][14]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + s2_hit_dup_0 = _RANDOM[7'h1E][15]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49] + s2_hit_dup_1 = _RANDOM[7'h1E][16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49] + s2_hit_dup_2 = _RANDOM[7'h1E][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49] + s2_hit_dup_3 = _RANDOM[7'h1E][18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49] + s3_hit_dup_0 = _RANDOM[7'h1E][19]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76] + s3_hit_dup_1 = _RANDOM[7'h1E][20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76] + s3_hit_dup_2 = _RANDOM[7'h1E][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76] + s3_hit_dup_3 = _RANDOM[7'h1E][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76] + higher_r = {_RANDOM[7'h1E][31:23], _RANDOM[7'h1F][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7, :429:88] + higher_plus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][14:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r = {_RANDOM[7'h20][31:15], _RANDOM[7'h21][10:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_1 = {_RANDOM[7'h21][31:11], _RANDOM[7'h22][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_1 = {_RANDOM[7'h22][31:7], _RANDOM[7'h23][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_1 = _RANDOM[7'h23][30:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_plus_one_r_2 = {_RANDOM[7'h24][31:19], _RANDOM[7'h25][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_2 = _RANDOM[7'h25][26:7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h25][27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :177:36, :284:7] + higher_r_3 = {_RANDOM[7'h25][31:28], _RANDOM[7'h26][23:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_plus_one_r_3 = {_RANDOM[7'h26][31:24], _RANDOM[7'h27][19:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_3 = {_RANDOM[7'h27][31:20], _RANDOM[7'h28][15:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_4 = {_RANDOM[7'h28][31:16], _RANDOM[7'h29][11:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_4 = {_RANDOM[7'h29][31:12], _RANDOM[7'h2A][7:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_4 = {_RANDOM[7'h2A][31:8], _RANDOM[7'h2B][3:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_5 = _RANDOM[7'h2B][23:4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_5 = {_RANDOM[7'h2B][31:24], _RANDOM[7'h2C][11:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_minus_one_r_5 = _RANDOM[7'h2C][31:12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2D][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7] + higher_r_6 = _RANDOM[7'h2D][28:1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :177:36, :284:7] + higher_plus_one_r_6 = {_RANDOM[7'h2D][31:29], _RANDOM[7'h2E][24:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :177:36, :284:7] + higher_minus_one_r_6 = {_RANDOM[7'h2E][31:25], _RANDOM[7'h2F][20:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_7 = {_RANDOM[7'h2F][31:21], _RANDOM[7'h30][16:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_7 = {_RANDOM[7'h30][31:17], _RANDOM[7'h31][12:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_7 = {_RANDOM[7'h31][31:13], _RANDOM[7'h32][8:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_8 = _RANDOM[7'h32][28:9]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_8 = {_RANDOM[7'h32][31:29], _RANDOM[7'h33][16:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_minus_one_r_8 = {_RANDOM[7'h33][31:17], _RANDOM[7'h34][4:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h34][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7] + higher_r_9 = {_RANDOM[7'h34][31:6], _RANDOM[7'h35][1:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_9 = _RANDOM[7'h35][29:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_9 = {_RANDOM[7'h35][31:30], _RANDOM[7'h36][25:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_r_10 = {_RANDOM[7'h36][31:26], _RANDOM[7'h37][21:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_10 = {_RANDOM[7'h37][31:22], _RANDOM[7'h38][17:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_10 = {_RANDOM[7'h38][31:18], _RANDOM[7'h39][13:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_11 = {_RANDOM[7'h39][31:14], _RANDOM[7'h3A][1:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_11 = _RANDOM[7'h3A][21:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_11 = {_RANDOM[7'h3A][31:22], _RANDOM[7'h3B][9:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h3B][10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7] + higher_r_12 = {_RANDOM[7'h3B][31:11], _RANDOM[7'h3C][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_12 = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_12 = _RANDOM[7'h3D][30:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_13 = {_RANDOM[7'h3D][31], _RANDOM[7'h3E][26:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_plus_one_r_13 = {_RANDOM[7'h3E][31:27], _RANDOM[7'h3F][22:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_13 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_14 = {_RANDOM[7'h40][31:19], _RANDOM[7'h41][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_14 = _RANDOM[7'h41][26:7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_14 = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][14:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_r_15 = {_RANDOM[7'h42][31:15], _RANDOM[7'h43][10:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_15 = {_RANDOM[7'h43][31:11], _RANDOM[7'h44][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_15 = {_RANDOM[7'h44][31:7], _RANDOM[7'h45][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_16 = _RANDOM[7'h45][30:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_16 = {_RANDOM[7'h45][31], _RANDOM[7'h46][26:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_minus_one_r_16 = {_RANDOM[7'h46][31:27], _RANDOM[7'h47][22:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_17 = {_RANDOM[7'h47][31:23], _RANDOM[7'h48][10:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_17 = _RANDOM[7'h48][30:11]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_17 = {_RANDOM[7'h48][31], _RANDOM[7'h49][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_r_18 = {_RANDOM[7'h49][31:19], _RANDOM[7'h4A][14:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_18 = {_RANDOM[7'h4A][31:15], _RANDOM[7'h4B][10:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_18 = {_RANDOM[7'h4B][31:11], _RANDOM[7'h4C][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_19 = {_RANDOM[7'h4C][31:7], _RANDOM[7'h4D][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_19 = _RANDOM[7'h4D][30:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_19 = {_RANDOM[7'h4D][31], _RANDOM[7'h4E][26:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_r_20 = {_RANDOM[7'h4E][31:27], _RANDOM[7'h4F][14:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_20 = {_RANDOM[7'h4F][31:15], _RANDOM[7'h50][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_20 = _RANDOM[7'h50][22:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_21 = {_RANDOM[7'h50][31:23], _RANDOM[7'h51][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_plus_one_r_21 = {_RANDOM[7'h51][31:19], _RANDOM[7'h52][14:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_21 = {_RANDOM[7'h52][31:15], _RANDOM[7'h53][10:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_22 = {_RANDOM[7'h53][31:11], _RANDOM[7'h54][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7] + higher_plus_one_r_22 = {_RANDOM[7'h54][31:7], _RANDOM[7'h55][2:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_22 = _RANDOM[7'h55][30:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + higher_r_23 = {_RANDOM[7'h55][31], _RANDOM[7'h56][18:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_plus_one_r_23 = {_RANDOM[7'h56][31:19], _RANDOM[7'h57][6:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7] + higher_minus_one_r_23 = _RANDOM[7'h57][26:7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7] + io_out_last_stage_meta_r = _RANDOM[7'h59][29:27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48] + io_out_last_stage_meta_r_1 = {_RANDOM[7'h59][31:30], _RANDOM[7'h5A][0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{38,48}] + io_s1_ready_REG = _RANDOM[7'h5A][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38, :483:76] + ftbBank_io_update_write_way_REG = _RANDOM[7'h5A][3:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38, :499:76] + ftbBank_io_update_write_alloc_REG = _RANDOM[7'h5A][4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38, :500:76] + io_perf_0_value_REG = _RANDOM[7'h5A][7]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38] + io_perf_0_value_REG_1 = _RANDOM[7'h5A][8]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38] + io_perf_1_value_REG = _RANDOM[7'h5A][9]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38] + io_perf_1_value_REG_1 = _RANDOM[7'h5A][10]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:38] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - s2_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s2_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 - s3_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 - s3_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + if (reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + s2_hit_dup_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s2_hit_dup_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49] + s3_hit_dup_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] + s3_hit_dup_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_2 reset_vector_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in (io_reset_vector), .io_out (_reset_vector_delay_io_out) ); - FTBBank ftbBank ( // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + FTBBank ftbBank ( // @[src/main/scala/xiangshan/frontend/FTB.scala:422:23] .clock (clock), .reset (reset), .io_s1_fire (io_s1_fire_0), @@ -1212,406 +1224,421 @@ module FTB( // src/main/scala/xiangshan/frontend/FTB.scala:284:7 (_ftbBank_io_read_resp_always_taken_1), .io_read_hits_valid (_ftbBank_io_read_hits_valid), .io_read_hits_bits (_ftbBank_io_read_hits_bits), - .io_u_req_pc_valid (update_need_read), // src/main/scala/xiangshan/frontend/FTB.scala:481:34 + .io_u_req_pc_valid (update_need_read), // @[src/main/scala/xiangshan/frontend/FTB.scala:481:34] .io_u_req_pc_bits (io_update_bits_pc), .io_update_hits_valid (_ftbBank_io_update_hits_valid), .io_update_hits_bits (_ftbBank_io_update_hits_bits), .io_update_access - (u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :501:39 - .io_update_pc (_ftb_write_tag_WIRE_2), // src/main/scala/xiangshan/frontend/FTB.scala:492:40 + (u_valid & ~(io_update_bits_meta[0])), // @[src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :501:39] + .io_update_pc (_ftbBank_io_update_pc_T), // @[src/main/scala/xiangshan/frontend/FTB.scala:492:40] .io_update_write_data_valid - (update_now | _write_valid_delay_io_out), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :494:32, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now | _write_valid_delay_io_out), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :494:32, utility/src/main/scala/utility/Hold.scala:100:23] .io_update_write_data_bits_entry_valid - (update_now ? io_update_bits_ftb_entry_valid : _delay2_entry_delay_io_out_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now + ? io_update_bits_ftb_entry_valid + : _delay2_entry_pipMod_io_out_bits_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_brSlots_0_offset (update_now ? io_update_bits_ftb_entry_brSlots_0_offset - : _delay2_entry_delay_io_out_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_brSlots_0_lower (update_now ? io_update_bits_ftb_entry_brSlots_0_lower - : _delay2_entry_delay_io_out_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_brSlots_0_tarStat (update_now ? io_update_bits_ftb_entry_brSlots_0_tarStat - : _delay2_entry_delay_io_out_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_brSlots_0_sharing (update_now ? io_update_bits_ftb_entry_brSlots_0_sharing - : _delay2_entry_delay_io_out_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_brSlots_0_valid (update_now ? io_update_bits_ftb_entry_brSlots_0_valid - : _delay2_entry_delay_io_out_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_tailSlot_offset (update_now ? io_update_bits_ftb_entry_tailSlot_offset - : _delay2_entry_delay_io_out_tailSlot_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_tailSlot_lower (update_now ? io_update_bits_ftb_entry_tailSlot_lower - : _delay2_entry_delay_io_out_tailSlot_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_tailSlot_tarStat (update_now ? io_update_bits_ftb_entry_tailSlot_tarStat - : _delay2_entry_delay_io_out_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_tailSlot_sharing (update_now ? io_update_bits_ftb_entry_tailSlot_sharing - : _delay2_entry_delay_io_out_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_tailSlot_valid (update_now ? io_update_bits_ftb_entry_tailSlot_valid - : _delay2_entry_delay_io_out_tailSlot_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_pftAddr (update_now ? io_update_bits_ftb_entry_pftAddr - : _delay2_entry_delay_io_out_pftAddr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_pftAddr), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_carry - (update_now ? io_update_bits_ftb_entry_carry : _delay2_entry_delay_io_out_carry), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now + ? io_update_bits_ftb_entry_carry + : _delay2_entry_pipMod_io_out_bits_carry), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_isCall - (update_now ? io_update_bits_ftb_entry_isCall : _delay2_entry_delay_io_out_isCall), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now + ? io_update_bits_ftb_entry_isCall + : _delay2_entry_pipMod_io_out_bits_isCall), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_isRet - (update_now ? io_update_bits_ftb_entry_isRet : _delay2_entry_delay_io_out_isRet), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now + ? io_update_bits_ftb_entry_isRet + : _delay2_entry_pipMod_io_out_bits_isRet), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_isJalr - (update_now ? io_update_bits_ftb_entry_isJalr : _delay2_entry_delay_io_out_isJalr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + (update_now + ? io_update_bits_ftb_entry_isJalr + : _delay2_entry_pipMod_io_out_bits_isJalr), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_last_may_be_rvi_call (update_now ? io_update_bits_ftb_entry_last_may_be_rvi_call - : _delay2_entry_delay_io_out_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_always_taken_0 (update_now ? io_update_bits_ftb_entry_always_taken_0 - : _delay2_entry_delay_io_out_always_taken_0), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + : _delay2_entry_pipMod_io_out_bits_always_taken_0), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] .io_update_write_data_bits_entry_always_taken_1 (update_now ? io_update_bits_ftb_entry_always_taken_1 - : _delay2_entry_delay_io_out_always_taken_1), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 - .io_update_write_data_bits_tag (_ftb_write_tag_WIRE_2[29:10]), // src/main/scala/xiangshan/frontend/FTB.scala:492:{40,75} + : _delay2_entry_pipMod_io_out_bits_always_taken_1), // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:130:24] + .io_update_write_data_bits_tag + (_ftbBank_io_update_pc_T[29:10]), // @[src/main/scala/xiangshan/frontend/FTB.scala:492:{40,75}] .io_update_write_way - (update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :480:28, :499:{39,76} + (update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG), // @[src/main/scala/xiangshan/frontend/FTB.scala:473:36, :480:28, :499:{39,76}] .io_update_write_alloc - (~update_now & ftbBank_io_update_write_alloc_REG) // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :500:{39,76} + (~update_now & ftbBank_io_update_write_alloc_REG) // @[src/main/scala/xiangshan/frontend/FTB.scala:480:28, :500:{39,76}] ); - DelayN_4 delay2_pc_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayNWithValid delay2_pc_pipMod ( // @[utility/src/main/scala/utility/Hold.scala:130:24] + .clock (clock), + .reset (reset), + .io_in_bits (io_update_bits_pc), + .io_in_valid (u_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:474:33] + .io_out_bits (_delay2_pc_pipMod_io_out_bits) + ); + DelayNWithValid_1 delay2_entry_pipMod ( // @[utility/src/main/scala/utility/Hold.scala:130:24] + .clock (clock), + .reset (reset), + .io_in_bits_valid (io_update_bits_ftb_entry_valid), + .io_in_bits_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset), + .io_in_bits_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower), + .io_in_bits_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_in_bits_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing), + .io_in_bits_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid), + .io_in_bits_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset), + .io_in_bits_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), + .io_in_bits_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_in_bits_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing), + .io_in_bits_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), + .io_in_bits_pftAddr (io_update_bits_ftb_entry_pftAddr), + .io_in_bits_carry (io_update_bits_ftb_entry_carry), + .io_in_bits_isCall (io_update_bits_ftb_entry_isCall), + .io_in_bits_isRet (io_update_bits_ftb_entry_isRet), + .io_in_bits_isJalr (io_update_bits_ftb_entry_isJalr), + .io_in_bits_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call), + .io_in_bits_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), + .io_in_bits_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), + .io_in_valid (u_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:474:33] + .io_out_bits_valid (_delay2_entry_pipMod_io_out_bits_valid), + .io_out_bits_brSlots_0_offset (_delay2_entry_pipMod_io_out_bits_brSlots_0_offset), + .io_out_bits_brSlots_0_lower (_delay2_entry_pipMod_io_out_bits_brSlots_0_lower), + .io_out_bits_brSlots_0_tarStat + (_delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat), + .io_out_bits_brSlots_0_sharing + (_delay2_entry_pipMod_io_out_bits_brSlots_0_sharing), + .io_out_bits_brSlots_0_valid (_delay2_entry_pipMod_io_out_bits_brSlots_0_valid), + .io_out_bits_tailSlot_offset (_delay2_entry_pipMod_io_out_bits_tailSlot_offset), + .io_out_bits_tailSlot_lower (_delay2_entry_pipMod_io_out_bits_tailSlot_lower), + .io_out_bits_tailSlot_tarStat (_delay2_entry_pipMod_io_out_bits_tailSlot_tarStat), + .io_out_bits_tailSlot_sharing (_delay2_entry_pipMod_io_out_bits_tailSlot_sharing), + .io_out_bits_tailSlot_valid (_delay2_entry_pipMod_io_out_bits_tailSlot_valid), + .io_out_bits_pftAddr (_delay2_entry_pipMod_io_out_bits_pftAddr), + .io_out_bits_carry (_delay2_entry_pipMod_io_out_bits_carry), + .io_out_bits_isCall (_delay2_entry_pipMod_io_out_bits_isCall), + .io_out_bits_isRet (_delay2_entry_pipMod_io_out_bits_isRet), + .io_out_bits_isJalr (_delay2_entry_pipMod_io_out_bits_isJalr), + .io_out_bits_last_may_be_rvi_call + (_delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call), + .io_out_bits_always_taken_0 (_delay2_entry_pipMod_io_out_bits_always_taken_0), + .io_out_bits_always_taken_1 (_delay2_entry_pipMod_io_out_bits_always_taken_1) + ); + DelayN_4 write_valid_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), - .io_in (io_update_bits_pc), - .io_out (_delay2_pc_delay_io_out) - ); - DelayN_5 delay2_entry_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 - .clock (clock), - .io_in_valid (io_update_bits_ftb_entry_valid), - .io_in_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset), - .io_in_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower), - .io_in_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat), - .io_in_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing), - .io_in_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid), - .io_in_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset), - .io_in_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), - .io_in_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat), - .io_in_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing), - .io_in_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), - .io_in_pftAddr (io_update_bits_ftb_entry_pftAddr), - .io_in_carry (io_update_bits_ftb_entry_carry), - .io_in_isCall (io_update_bits_ftb_entry_isCall), - .io_in_isRet (io_update_bits_ftb_entry_isRet), - .io_in_isJalr (io_update_bits_ftb_entry_isJalr), - .io_in_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call), - .io_in_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), - .io_in_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), - .io_out_valid (_delay2_entry_delay_io_out_valid), - .io_out_brSlots_0_offset (_delay2_entry_delay_io_out_brSlots_0_offset), - .io_out_brSlots_0_lower (_delay2_entry_delay_io_out_brSlots_0_lower), - .io_out_brSlots_0_tarStat (_delay2_entry_delay_io_out_brSlots_0_tarStat), - .io_out_brSlots_0_sharing (_delay2_entry_delay_io_out_brSlots_0_sharing), - .io_out_brSlots_0_valid (_delay2_entry_delay_io_out_brSlots_0_valid), - .io_out_tailSlot_offset (_delay2_entry_delay_io_out_tailSlot_offset), - .io_out_tailSlot_lower (_delay2_entry_delay_io_out_tailSlot_lower), - .io_out_tailSlot_tarStat (_delay2_entry_delay_io_out_tailSlot_tarStat), - .io_out_tailSlot_sharing (_delay2_entry_delay_io_out_tailSlot_sharing), - .io_out_tailSlot_valid (_delay2_entry_delay_io_out_tailSlot_valid), - .io_out_pftAddr (_delay2_entry_delay_io_out_pftAddr), - .io_out_carry (_delay2_entry_delay_io_out_carry), - .io_out_isCall (_delay2_entry_delay_io_out_isCall), - .io_out_isRet (_delay2_entry_delay_io_out_isRet), - .io_out_isJalr (_delay2_entry_delay_io_out_isJalr), - .io_out_last_may_be_rvi_call (_delay2_entry_delay_io_out_last_may_be_rvi_call), - .io_out_always_taken_0 (_delay2_entry_delay_io_out_always_taken_0), - .io_out_always_taken_1 (_delay2_entry_delay_io_out_always_taken_1) - ); - DelayN_6 write_valid_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 - .clock (clock), - .io_in (u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :494:50 + .io_in (u_valid & ~(io_update_bits_meta[0])), // @[src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :494:50] .io_out (_write_valid_delay_io_out) ); assign io_out_s2_full_pred_0_br_taken_mask_0 = io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0 - & s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + & s2_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] assign io_out_s2_full_pred_0_br_taken_mask_1 = io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0 - & s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} - assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + & s2_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] + assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_0_targets_0 = - {(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 26'h0) - | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 26'h0) - | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 26'h0), + {(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 28'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 28'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 28'h0), s2_ftb_entry_dup_0_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 - assign io_out_s2_full_pred_0_targets_1 = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_0_jalr_target = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55] + assign io_out_s2_full_pred_0_targets_1 = io_out_s2_full_pred_0_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_0_jalr_target = io_out_s2_full_pred_0_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_0_fallThroughAddr = {1'h0, s2_pc_dup_0[4:1]} >= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr} - ? 39'(s2_pc_dup_0 + 39'h20) + ? 41'(s2_pc_dup_0 + 41'h20) : {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry - ? 34'(s2_pc_dup_0[38:5] + 34'h1) - : s2_pc_dup_0[38:5], + ? 36'(s2_pc_dup_0[40:5] + 36'h1) + : s2_pc_dup_0[40:5], s2_ftb_entry_dup_0_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34, :551:{27,47}] assign io_out_s2_full_pred_0_is_br_sharing = - s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s2_full_pred_0_hit = s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s2_full_pred_0_hit = s2_hit_dup_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49] assign io_out_s2_full_pred_1_br_taken_mask_0 = io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1 - & s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + & s2_ftb_entry_dup_1_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] assign io_out_s2_full_pred_1_br_taken_mask_1 = io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1 - & s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} - assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + & s2_ftb_entry_dup_1_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] + assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_1_targets_0 = - {(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 26'h0) - | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 26'h0) - | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 26'h0), + {(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 28'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 28'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 28'h0), s2_ftb_entry_dup_1_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 - assign io_out_s2_full_pred_1_targets_1 = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_1_jalr_target = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55] + assign io_out_s2_full_pred_1_targets_1 = io_out_s2_full_pred_1_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_1_jalr_target = io_out_s2_full_pred_1_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_1_fallThroughAddr = {1'h0, s2_pc_dup_1[4:1]} >= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr} - ? 39'(s2_pc_dup_1 + 39'h20) + ? 41'(s2_pc_dup_1 + 41'h20) : {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry - ? 34'(s2_pc_dup_1[38:5] + 34'h1) - : s2_pc_dup_1[38:5], + ? 36'(s2_pc_dup_1[40:5] + 36'h1) + : s2_pc_dup_1[40:5], s2_ftb_entry_dup_1_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34, :551:{27,47}] assign io_out_s2_full_pred_1_is_br_sharing = - s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s2_full_pred_1_hit = s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s2_full_pred_1_hit = s2_hit_dup_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49] assign io_out_s2_full_pred_2_br_taken_mask_0 = io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2 - & s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + & s2_ftb_entry_dup_2_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] assign io_out_s2_full_pred_2_br_taken_mask_1 = io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2 - & s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} - assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + & s2_ftb_entry_dup_2_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] + assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_2_targets_0 = - {(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 26'h0) - | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 26'h0) - | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 26'h0), + {(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 28'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 28'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 28'h0), s2_ftb_entry_dup_2_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 - assign io_out_s2_full_pred_2_targets_1 = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_2_jalr_target = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55] + assign io_out_s2_full_pred_2_targets_1 = io_out_s2_full_pred_2_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_2_jalr_target = io_out_s2_full_pred_2_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_2_fallThroughAddr = {1'h0, s2_pc_dup_2[4:1]} >= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr} - ? 39'(s2_pc_dup_2 + 39'h20) + ? 41'(s2_pc_dup_2 + 41'h20) : {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry - ? 34'(s2_pc_dup_2[38:5] + 34'h1) - : s2_pc_dup_2[38:5], + ? 36'(s2_pc_dup_2[40:5] + 36'h1) + : s2_pc_dup_2[40:5], s2_ftb_entry_dup_2_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34, :551:{27,47}] assign io_out_s2_full_pred_2_is_jalr = - s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37 + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37] assign io_out_s2_full_pred_2_is_call = - s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37 + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:37] assign io_out_s2_full_pred_2_is_ret = - s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36 + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:543:36] assign io_out_s2_full_pred_2_last_may_be_rvi_call = - s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_2_is_br_sharing = - s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s2_full_pred_2_hit = s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s2_full_pred_2_hit = s2_hit_dup_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49] assign io_out_s2_full_pred_3_br_taken_mask_0 = io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3 - & s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + & s2_ftb_entry_dup_3_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] assign io_out_s2_full_pred_3_br_taken_mask_1 = io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3 - & s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} - assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + & s2_ftb_entry_dup_3_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}] + assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_3_targets_0 = - {(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 26'h0) - | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 26'h0) - | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 26'h0), + {(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 28'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 28'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 28'h0), s2_ftb_entry_dup_3_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 - assign io_out_s2_full_pred_3_targets_1 = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_3_jalr_target = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 - assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55] + assign io_out_s2_full_pred_3_targets_1 = io_out_s2_full_pred_3_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_3_jalr_target = io_out_s2_full_pred_3_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] + assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55] assign io_out_s2_full_pred_3_fallThroughAddr = - _io_out_s2_full_pred_3_fallThroughErr_output - ? 39'(s2_pc_dup_3 + 39'h20) + io_out_s2_full_pred_3_fallThroughErr_0 + ? 41'(s2_pc_dup_3 + 41'h20) : {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry - ? 34'(s2_pc_dup_3[38:5] + 34'h1) - : s2_pc_dup_3[38:5], + ? 36'(s2_pc_dup_3[40:5] + 36'h1) + : s2_pc_dup_3[40:5], s2_ftb_entry_dup_3_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - assign io_out_s2_full_pred_3_fallThroughErr = - _io_out_s2_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + assign io_out_s2_full_pred_3_fallThroughErr = io_out_s2_full_pred_3_fallThroughErr_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] assign io_out_s2_full_pred_3_is_br_sharing = - s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s2_full_pred_3_hit = s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s2_full_pred_3_hit = s2_hit_dup_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49] assign io_out_s3_full_pred_0_br_taken_mask_0 = io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0 - & s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + & s3_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] assign io_out_s3_full_pred_0_br_taken_mask_1 = io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0 - & s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} - assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + & s3_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] + assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_s3_full_pred_0_targets_0 = - {(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 26'h0) - | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 26'h0) - | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 26'h0), + {(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 28'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 28'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 28'h0), s3_ftb_entry_dup_0_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 - assign io_out_s3_full_pred_0_targets_1 = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s3_full_pred_0_jalr_target = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88] + assign io_out_s3_full_pred_0_targets_1 = io_out_s3_full_pred_0_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s3_full_pred_0_jalr_target = io_out_s3_full_pred_0_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] assign io_out_s3_full_pred_0_fallThroughAddr = - _io_out_s3_full_pred_0_fallThroughErr_output - ? 39'(s3_pc_dup_0 + 39'h20) - : {s3_ftb_entry_dup_0_carry ? 34'(s3_pc_dup_0[38:5] + 34'h1) : s3_pc_dup_0[38:5], + io_out_s3_full_pred_0_fallThroughErr_0 + ? 41'(s3_pc_dup_0 + 41'h20) + : {s3_ftb_entry_dup_0_carry ? 36'(s3_pc_dup_0[40:5] + 36'h1) : s3_pc_dup_0[40:5], s3_ftb_entry_dup_0_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - assign io_out_s3_full_pred_0_fallThroughErr = - _io_out_s3_full_pred_0_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + assign io_out_s3_full_pred_0_fallThroughErr = io_out_s3_full_pred_0_fallThroughErr_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] assign io_out_s3_full_pred_0_is_br_sharing = - s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s3_full_pred_0_hit = s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s3_full_pred_0_hit = s3_hit_dup_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76] assign io_out_s3_full_pred_1_br_taken_mask_0 = io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1 - & s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + & s3_ftb_entry_dup_1_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] assign io_out_s3_full_pred_1_br_taken_mask_1 = io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1 - & s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} - assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + & s3_ftb_entry_dup_1_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] + assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_s3_full_pred_1_targets_0 = - {(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 26'h0) - | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 26'h0) - | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 26'h0), + {(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 28'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 28'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 28'h0), s3_ftb_entry_dup_1_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 - assign io_out_s3_full_pred_1_targets_1 = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s3_full_pred_1_jalr_target = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88] + assign io_out_s3_full_pred_1_targets_1 = io_out_s3_full_pred_1_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s3_full_pred_1_jalr_target = io_out_s3_full_pred_1_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] assign io_out_s3_full_pred_1_fallThroughAddr = - _io_out_s3_full_pred_1_fallThroughErr_output - ? 39'(s3_pc_dup_1 + 39'h20) - : {s3_ftb_entry_dup_1_carry ? 34'(s3_pc_dup_1[38:5] + 34'h1) : s3_pc_dup_1[38:5], + io_out_s3_full_pred_1_fallThroughErr_0 + ? 41'(s3_pc_dup_1 + 41'h20) + : {s3_ftb_entry_dup_1_carry ? 36'(s3_pc_dup_1[40:5] + 36'h1) : s3_pc_dup_1[40:5], s3_ftb_entry_dup_1_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - assign io_out_s3_full_pred_1_fallThroughErr = - _io_out_s3_full_pred_1_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + assign io_out_s3_full_pred_1_fallThroughErr = io_out_s3_full_pred_1_fallThroughErr_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] assign io_out_s3_full_pred_1_is_br_sharing = - s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s3_full_pred_1_hit = s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s3_full_pred_1_hit = s3_hit_dup_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76] assign io_out_s3_full_pred_2_br_taken_mask_0 = io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2 - & s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + & s3_ftb_entry_dup_2_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] assign io_out_s3_full_pred_2_br_taken_mask_1 = io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2 - & s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} - assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + & s3_ftb_entry_dup_2_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] + assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_s3_full_pred_2_targets_0 = - {(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 26'h0) - | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 26'h0) - | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 26'h0), + {(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 28'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 28'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 28'h0), s3_ftb_entry_dup_2_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 - assign io_out_s3_full_pred_2_targets_1 = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s3_full_pred_2_jalr_target = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88] + assign io_out_s3_full_pred_2_targets_1 = io_out_s3_full_pred_2_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s3_full_pred_2_jalr_target = io_out_s3_full_pred_2_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] assign io_out_s3_full_pred_2_fallThroughAddr = - _io_out_s3_full_pred_2_fallThroughErr_output - ? 39'(s3_pc_dup_2 + 39'h20) - : {s3_ftb_entry_dup_2_carry ? 34'(s3_pc_dup_2[38:5] + 34'h1) : s3_pc_dup_2[38:5], + io_out_s3_full_pred_2_fallThroughErr_0 + ? 41'(s3_pc_dup_2 + 41'h20) + : {s3_ftb_entry_dup_2_carry ? 36'(s3_pc_dup_2[40:5] + 36'h1) : s3_pc_dup_2[40:5], s3_ftb_entry_dup_2_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - assign io_out_s3_full_pred_2_fallThroughErr = - _io_out_s3_full_pred_2_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + assign io_out_s3_full_pred_2_fallThroughErr = io_out_s3_full_pred_2_fallThroughErr_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] assign io_out_s3_full_pred_2_is_jalr = - s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37 + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37] assign io_out_s3_full_pred_2_is_call = - s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37 + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:37] assign io_out_s3_full_pred_2_is_ret = - s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36 + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:543:36] assign io_out_s3_full_pred_2_is_br_sharing = - s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s3_full_pred_2_hit = s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s3_full_pred_2_hit = s3_hit_dup_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76] assign io_out_s3_full_pred_3_br_taken_mask_0 = io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3 - & s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + & s3_ftb_entry_dup_3_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] assign io_out_s3_full_pred_3_br_taken_mask_1 = io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3 - & s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} - assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + & s3_ftb_entry_dup_3_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}] + assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_s3_full_pred_3_targets_0 = - {(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 26'h0) - | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 26'h0) - | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 26'h0), + {(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 28'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 28'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 28'h0), s3_ftb_entry_dup_3_brSlots_0_lower, - 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 - assign io_out_s3_full_pred_3_targets_1 = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s3_full_pred_3_jalr_target = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 - assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + 1'h0}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88] + assign io_out_s3_full_pred_3_targets_1 = io_out_s3_full_pred_3_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s3_full_pred_3_jalr_target = io_out_s3_full_pred_3_targets_1_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7] + assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_s3_full_pred_3_fallThroughAddr = - _io_out_s3_full_pred_3_fallThroughErr_output - ? 39'(s3_pc_dup_3 + 39'h20) - : {s3_ftb_entry_dup_3_carry ? 34'(s3_pc_dup_3[38:5] + 34'h1) : s3_pc_dup_3[38:5], + io_out_s3_full_pred_3_fallThroughErr_0 + ? 41'(s3_pc_dup_3 + 41'h20) + : {s3_ftb_entry_dup_3_carry ? 36'(s3_pc_dup_3[40:5] + 36'h1) : s3_pc_dup_3[40:5], s3_ftb_entry_dup_3_pftAddr, - 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - assign io_out_s3_full_pred_3_fallThroughErr = - _io_out_s3_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + 1'h0}; // @[src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :189:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + assign io_out_s3_full_pred_3_fallThroughErr = io_out_s3_full_pred_3_fallThroughErr_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] assign io_out_s3_full_pred_3_is_br_sharing = - s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 - assign io_out_s3_full_pred_3_hit = s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 - assign io_out_last_stage_meta = {216'h0, io_out_last_stage_meta_r_1}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{26,38} - assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:545:43] + assign io_out_s3_full_pred_3_hit = s3_hit_dup_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76] + assign io_out_last_stage_meta = {220'h0, io_out_last_stage_meta_r_1}; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{26,38}] + assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_brSlots_0_offset = - s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = - s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_brSlots_0_sharing = - s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_tailSlot_tarStat = - s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_tailSlot_sharing = - s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = - s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 - assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :422:23, :481:34, :483:{45,65,68,76} + s3_ftb_entry_dup_0_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88] + assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:284:7, :422:23, :481:34, :483:{45,65,68,76}] + assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/BPU.scala:192:39, src/main/scala/xiangshan/frontend/FTB.scala:284:7] + assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/BPU.scala:192:39, src/main/scala/xiangshan/frontend/FTB.scala:284:7] endmodule diff --git a/rtl/FTB/FTBBank.sv b/rtl/FTB/FTBBank.sv index 277e35b..b7226cf 100644 --- a/rtl/FTB/FTBBank.sv +++ b/rtl/FTB/FTBBank.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,793 +55,792 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - input clock, - input reset, - input io_s1_fire, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_req_pc_ready, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_req_pc_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [38:0] io_req_pc_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [3:0] io_read_resp_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [11:0] io_read_resp_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [1:0] io_read_resp_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [3:0] io_read_resp_tailSlot_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [19:0] io_read_resp_tailSlot_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [1:0] io_read_resp_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_tailSlot_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [3:0] io_read_resp_pftAddr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_carry, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_isCall, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_isRet, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_isJalr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_always_taken_0, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_resp_always_taken_1, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_read_hits_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [1:0] io_read_hits_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_u_req_pc_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [38:0] io_u_req_pc_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output io_update_hits_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - output [1:0] io_update_hits_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_access, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [3:0] io_update_write_data_bits_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [11:0] io_update_write_data_bits_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [1:0] io_update_write_data_bits_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [3:0] io_update_write_data_bits_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [19:0] io_update_write_data_bits_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [1:0] io_update_write_data_bits_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [3:0] io_update_write_data_bits_entry_pftAddr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_carry, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_isCall, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_isRet, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_isJalr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_always_taken_0, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_data_bits_entry_always_taken_1, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [19:0] io_update_write_data_bits_tag, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input [1:0] io_update_write_way, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - input io_update_write_alloc // src/main/scala/xiangshan/frontend/FTB.scala:291:16 +module FTBBank( // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + input clock, // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + input reset, // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + input io_s1_fire, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_req_pc_ready, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_req_pc_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [40:0] io_req_pc_bits, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [3:0] io_read_resp_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [11:0] io_read_resp_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [1:0] io_read_resp_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [3:0] io_read_resp_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [19:0] io_read_resp_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [1:0] io_read_resp_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [3:0] io_read_resp_pftAddr, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_carry, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_isCall, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_isRet, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_isJalr, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_always_taken_0, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_resp_always_taken_1, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_read_hits_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [1:0] io_read_hits_bits, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_u_req_pc_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [40:0] io_u_req_pc_bits, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output io_update_hits_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + output [1:0] io_update_hits_bits, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_access, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [3:0] io_update_write_data_bits_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [11:0] io_update_write_data_bits_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [1:0] io_update_write_data_bits_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [3:0] io_update_write_data_bits_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [19:0] io_update_write_data_bits_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [1:0] io_update_write_data_bits_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [3:0] io_update_write_data_bits_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_carry, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_isCall, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_isRet, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_isJalr, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_data_bits_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [19:0] io_update_write_data_bits_tag, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input [1:0] io_update_write_way, // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + input io_update_write_alloc // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] ); - wire _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [11:0] _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_0_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_0_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_0_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_0_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [11:0] _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_1_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_1_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_1_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_1_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [11:0] _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_2_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_2_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_2_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_2_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_2_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [11:0] _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_3_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_3_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [1:0] _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [3:0] _ftb_io_r_resp_data_3_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire _ftb_io_r_resp_data_3_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - wire [19:0] _ftb_io_r_resp_data_3_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 - reg pred_rdata_REG; // src/main/scala/xiangshan/frontend/FTB.scala:315:62 - reg pred_rdata_hold_data_0_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [11:0] pred_rdata_hold_data_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_0_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_0_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_0_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_0_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_0_tag; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [11:0] pred_rdata_hold_data_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_1_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_1_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_1_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_1_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_1_tag; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [11:0] pred_rdata_hold_data_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_2_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_2_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_2_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_2_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_2_tag; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [11:0] pred_rdata_hold_data_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_3_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_3_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] pred_rdata_hold_data_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [3:0] pred_rdata_hold_data_3_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg pred_rdata_hold_data_3_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [19:0] pred_rdata_hold_data_3_tag; // utility/src/main/scala/utility/Hold.scala:24:82 + wire _ftb_io_r_resp_data_0_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [11:0] _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_0_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_0_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_0_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_0_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [11:0] _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_1_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_1_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_1_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_1_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [11:0] _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_2_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_2_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_2_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_2_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_2_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [11:0] _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_3_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_3_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [1:0] _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [3:0] _ftb_io_r_resp_data_3_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire _ftb_io_r_resp_data_3_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + wire [19:0] _ftb_io_r_resp_data_3_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] + reg pred_rdata_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:315:62] + reg pred_rdata_hold_data_0_entry_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_0_entry_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [11:0] pred_rdata_hold_data_0_entry_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_0_entry_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_0_entry_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_0_entry_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_0_entry_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_0_entry_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_carry; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_isCall; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_isRet; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_isJalr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_0_entry_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_0_tag; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_1_entry_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [11:0] pred_rdata_hold_data_1_entry_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_1_entry_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_1_entry_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_1_entry_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_1_entry_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_1_entry_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_carry; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_isCall; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_isRet; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_isJalr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_1_entry_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_1_tag; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_2_entry_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [11:0] pred_rdata_hold_data_2_entry_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_2_entry_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_2_entry_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_2_entry_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_2_entry_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_2_entry_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_carry; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_isCall; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_isRet; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_isJalr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_2_entry_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_2_tag; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_3_entry_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [11:0] pred_rdata_hold_data_3_entry_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_3_entry_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_3_entry_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_3_entry_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] pred_rdata_hold_data_3_entry_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [3:0] pred_rdata_hold_data_3_entry_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_carry; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_isCall; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_isRet; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_isJalr; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg pred_rdata_hold_data_3_entry_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [19:0] pred_rdata_hold_data_3_tag; // @[utility/src/main/scala/utility/Hold.scala:24:82] wire pred_rdata_0_entry_valid = pred_rdata_REG ? _ftb_io_r_resp_data_0_entry_valid - : pred_rdata_hold_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_0_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire pred_rdata_1_entry_valid = pred_rdata_REG ? _ftb_io_r_resp_data_1_entry_valid - : pred_rdata_hold_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_1_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire pred_rdata_2_entry_valid = pred_rdata_REG ? _ftb_io_r_resp_data_2_entry_valid - : pred_rdata_hold_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_2_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire pred_rdata_3_entry_valid = pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_valid - : pred_rdata_hold_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 - reg [19:0] req_tag; // src/main/scala/xiangshan/frontend/FTB.scala:324:28 - reg [8:0] req_idx; // src/main/scala/xiangshan/frontend/FTB.scala:325:28 - reg [19:0] u_req_tag; // src/main/scala/xiangshan/frontend/FTB.scala:327:30 + : pred_rdata_hold_data_3_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] + reg [19:0] req_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:324:28] + reg [8:0] req_idx; // @[src/main/scala/xiangshan/frontend/FTB.scala:325:28] + reg [19:0] u_req_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:327:30] wire total_hits_0 = (pred_rdata_REG ? _ftb_io_r_resp_data_0_tag : pred_rdata_hold_data_0_tag) == req_tag - & pred_rdata_0_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + & pred_rdata_0_entry_valid & io_s1_fire; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire total_hits_1 = (pred_rdata_REG ? _ftb_io_r_resp_data_1_tag : pred_rdata_hold_data_1_tag) == req_tag - & pred_rdata_1_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + & pred_rdata_1_entry_valid & io_s1_fire; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire total_hits_2 = (pred_rdata_REG ? _ftb_io_r_resp_data_2_tag : pred_rdata_hold_data_2_tag) == req_tag - & pred_rdata_2_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + & pred_rdata_2_entry_valid & io_s1_fire; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] wire total_hits_3 = (pred_rdata_REG ? _ftb_io_r_resp_data_3_tag : pred_rdata_hold_data_3_tag) == req_tag - & pred_rdata_3_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 - wire read_way_valid = - total_hits_0 | total_hits_1 | total_hits_2 | total_hits_3; // src/main/scala/xiangshan/frontend/FTB.scala:332:107, :333:34 - wire [1:0] read_way_bits = - {|{total_hits_3, total_hits_2}, total_hits_3 | total_hits_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:332:107 - reg u_total_hits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 - reg u_total_hits_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + & pred_rdata_3_entry_valid & io_s1_fire; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] + wire hit = total_hits_0 | total_hits_1 | total_hits_2 | total_hits_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:332:107, :333:34] + wire [1:0] hit_way = + {|{total_hits_3, total_hits_2}, total_hits_3 | total_hits_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:332:107] + reg u_total_hits_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] + reg u_total_hits_REG_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] wire u_total_hits_1 = _ftb_io_r_resp_data_1_tag == u_req_tag & _ftb_io_r_resp_data_1_entry_valid - & u_total_hits_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} - reg u_total_hits_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + & u_total_hits_REG_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96}] + reg u_total_hits_REG_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] wire u_total_hits_2 = _ftb_io_r_resp_data_2_tag == u_req_tag & _ftb_io_r_resp_data_2_entry_valid - & u_total_hits_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} - reg u_total_hits_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + & u_total_hits_REG_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96}] + reg u_total_hits_REG_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] wire u_total_hits_3 = _ftb_io_r_resp_data_3_tag == u_req_tag & _ftb_io_r_resp_data_3_entry_valid - & u_total_hits_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} - reg [2:0] state_vec_0; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_1; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_2; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_3; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_4; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_5; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_6; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_7; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_8; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_9; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_10; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_11; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_12; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_13; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_14; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_15; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_16; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_17; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_18; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_19; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_20; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_21; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_22; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_23; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_24; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_25; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_26; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_27; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_28; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_29; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_30; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_31; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_32; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_33; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_34; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_35; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_36; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_37; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_38; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_39; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_40; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_41; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_42; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_43; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_44; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_45; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_46; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_47; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_48; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_49; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_50; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_51; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_52; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_53; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_54; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_55; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_56; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_57; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_58; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_59; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_60; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_61; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_62; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_63; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_64; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_65; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_66; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_67; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_68; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_69; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_70; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_71; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_72; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_73; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_74; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_75; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_76; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_77; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_78; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_79; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_80; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_81; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_82; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_83; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_84; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_85; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_86; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_87; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_88; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_89; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_90; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_91; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_92; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_93; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_94; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_95; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_96; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_97; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_98; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_99; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_100; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_101; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_102; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_103; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_104; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_105; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_106; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_107; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_108; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_109; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_110; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_111; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_112; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_113; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_114; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_115; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_116; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_117; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_118; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_119; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_120; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_121; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_122; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_123; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_124; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_125; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_126; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_127; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_128; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_129; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_130; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_131; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_132; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_133; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_134; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_135; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_136; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_137; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_138; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_139; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_140; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_141; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_142; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_143; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_144; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_145; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_146; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_147; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_148; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_149; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_150; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_151; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_152; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_153; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_154; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_155; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_156; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_157; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_158; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_159; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_160; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_161; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_162; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_163; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_164; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_165; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_166; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_167; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_168; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_169; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_170; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_171; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_172; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_173; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_174; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_175; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_176; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_177; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_178; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_179; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_180; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_181; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_182; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_183; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_184; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_185; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_186; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_187; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_188; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_189; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_190; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_191; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_192; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_193; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_194; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_195; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_196; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_197; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_198; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_199; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_200; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_201; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_202; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_203; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_204; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_205; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_206; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_207; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_208; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_209; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_210; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_211; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_212; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_213; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_214; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_215; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_216; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_217; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_218; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_219; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_220; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_221; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_222; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_223; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_224; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_225; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_226; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_227; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_228; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_229; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_230; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_231; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_232; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_233; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_234; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_235; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_236; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_237; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_238; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_239; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_240; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_241; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_242; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_243; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_244; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_245; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_246; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_247; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_248; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_249; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_250; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_251; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_252; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_253; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_254; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_255; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_256; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_257; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_258; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_259; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_260; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_261; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_262; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_263; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_264; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_265; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_266; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_267; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_268; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_269; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_270; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_271; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_272; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_273; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_274; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_275; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_276; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_277; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_278; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_279; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_280; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_281; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_282; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_283; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_284; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_285; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_286; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_287; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_288; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_289; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_290; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_291; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_292; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_293; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_294; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_295; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_296; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_297; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_298; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_299; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_300; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_301; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_302; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_303; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_304; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_305; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_306; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_307; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_308; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_309; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_310; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_311; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_312; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_313; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_314; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_315; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_316; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_317; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_318; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_319; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_320; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_321; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_322; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_323; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_324; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_325; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_326; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_327; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_328; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_329; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_330; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_331; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_332; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_333; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_334; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_335; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_336; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_337; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_338; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_339; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_340; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_341; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_342; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_343; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_344; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_345; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_346; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_347; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_348; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_349; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_350; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_351; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_352; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_353; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_354; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_355; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_356; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_357; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_358; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_359; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_360; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_361; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_362; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_363; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_364; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_365; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_366; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_367; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_368; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_369; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_370; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_371; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_372; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_373; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_374; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_375; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_376; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_377; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_378; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_379; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_380; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_381; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_382; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_383; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_384; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_385; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_386; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_387; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_388; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_389; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_390; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_391; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_392; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_393; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_394; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_395; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_396; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_397; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_398; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_399; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_400; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_401; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_402; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_403; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_404; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_405; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_406; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_407; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_408; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_409; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_410; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_411; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_412; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_413; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_414; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_415; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_416; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_417; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_418; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_419; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_420; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_421; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_422; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_423; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_424; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_425; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_426; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_427; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_428; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_429; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_430; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_431; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_432; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_433; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_434; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_435; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_436; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_437; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_438; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_439; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_440; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_441; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_442; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_443; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_444; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_445; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_446; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_447; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_448; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_449; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_450; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_451; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_452; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_453; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_454; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_455; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_456; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_457; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_458; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_459; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_460; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_461; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_462; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_463; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_464; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_465; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_466; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_467; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_468; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_469; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_470; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_471; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_472; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_473; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_474; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_475; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_476; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_477; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_478; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_479; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_480; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_481; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_482; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_483; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_484; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_485; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_486; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_487; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_488; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_489; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_490; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_491; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_492; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_493; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_494; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_495; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_496; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_497; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_498; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_499; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_500; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_501; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_502; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_503; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_504; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_505; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_506; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_507; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_508; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_509; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_510; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [2:0] state_vec_511; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 - reg [8:0] touch_set_0_REG; // src/main/scala/xiangshan/frontend/FTB.scala:368:60 - reg touch_way_0_valid_REG; // src/main/scala/xiangshan/frontend/FTB.scala:369:53 - reg [1:0] touch_way_0_bits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:370:70 - reg allocWriteWay_REG_0; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 - reg allocWriteWay_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 - reg allocWriteWay_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 - reg allocWriteWay_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 + & u_total_hits_REG_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96}] + reg [2:0] state_vec_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_2; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_3; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_4; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_5; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_6; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_7; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_8; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_9; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_10; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_11; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_12; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_13; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_14; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_15; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_16; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_17; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_18; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_19; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_20; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_21; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_22; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_23; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_24; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_25; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_26; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_27; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_28; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_29; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_30; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_31; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_32; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_33; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_34; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_35; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_36; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_37; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_38; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_39; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_40; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_41; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_42; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_43; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_44; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_45; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_46; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_47; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_48; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_49; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_50; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_51; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_52; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_53; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_54; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_55; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_56; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_57; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_58; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_59; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_60; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_61; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_62; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_63; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_64; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_65; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_66; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_67; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_68; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_69; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_70; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_71; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_72; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_73; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_74; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_75; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_76; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_77; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_78; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_79; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_80; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_81; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_82; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_83; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_84; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_85; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_86; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_87; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_88; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_89; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_90; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_91; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_92; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_93; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_94; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_95; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_96; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_97; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_98; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_99; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_100; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_101; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_102; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_103; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_104; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_105; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_106; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_107; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_108; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_109; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_110; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_111; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_112; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_113; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_114; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_115; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_116; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_117; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_118; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_119; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_120; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_121; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_122; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_123; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_124; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_125; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_126; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_127; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_128; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_129; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_130; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_131; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_132; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_133; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_134; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_135; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_136; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_137; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_138; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_139; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_140; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_141; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_142; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_143; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_144; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_145; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_146; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_147; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_148; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_149; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_150; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_151; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_152; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_153; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_154; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_155; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_156; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_157; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_158; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_159; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_160; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_161; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_162; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_163; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_164; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_165; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_166; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_167; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_168; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_169; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_170; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_171; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_172; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_173; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_174; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_175; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_176; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_177; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_178; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_179; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_180; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_181; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_182; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_183; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_184; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_185; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_186; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_187; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_188; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_189; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_190; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_191; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_192; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_193; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_194; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_195; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_196; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_197; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_198; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_199; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_200; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_201; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_202; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_203; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_204; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_205; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_206; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_207; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_208; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_209; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_210; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_211; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_212; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_213; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_214; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_215; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_216; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_217; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_218; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_219; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_220; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_221; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_222; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_223; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_224; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_225; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_226; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_227; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_228; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_229; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_230; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_231; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_232; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_233; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_234; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_235; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_236; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_237; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_238; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_239; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_240; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_241; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_242; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_243; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_244; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_245; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_246; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_247; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_248; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_249; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_250; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_251; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_252; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_253; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_254; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_255; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_256; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_257; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_258; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_259; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_260; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_261; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_262; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_263; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_264; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_265; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_266; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_267; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_268; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_269; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_270; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_271; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_272; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_273; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_274; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_275; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_276; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_277; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_278; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_279; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_280; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_281; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_282; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_283; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_284; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_285; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_286; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_287; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_288; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_289; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_290; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_291; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_292; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_293; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_294; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_295; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_296; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_297; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_298; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_299; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_300; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_301; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_302; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_303; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_304; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_305; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_306; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_307; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_308; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_309; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_310; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_311; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_312; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_313; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_314; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_315; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_316; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_317; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_318; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_319; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_320; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_321; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_322; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_323; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_324; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_325; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_326; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_327; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_328; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_329; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_330; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_331; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_332; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_333; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_334; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_335; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_336; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_337; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_338; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_339; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_340; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_341; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_342; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_343; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_344; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_345; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_346; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_347; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_348; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_349; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_350; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_351; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_352; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_353; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_354; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_355; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_356; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_357; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_358; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_359; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_360; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_361; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_362; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_363; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_364; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_365; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_366; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_367; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_368; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_369; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_370; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_371; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_372; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_373; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_374; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_375; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_376; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_377; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_378; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_379; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_380; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_381; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_382; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_383; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_384; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_385; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_386; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_387; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_388; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_389; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_390; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_391; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_392; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_393; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_394; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_395; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_396; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_397; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_398; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_399; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_400; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_401; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_402; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_403; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_404; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_405; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_406; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_407; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_408; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_409; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_410; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_411; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_412; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_413; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_414; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_415; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_416; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_417; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_418; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_419; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_420; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_421; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_422; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_423; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_424; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_425; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_426; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_427; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_428; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_429; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_430; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_431; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_432; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_433; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_434; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_435; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_436; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_437; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_438; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_439; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_440; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_441; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_442; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_443; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_444; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_445; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_446; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_447; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_448; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_449; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_450; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_451; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_452; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_453; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_454; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_455; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_456; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_457; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_458; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_459; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_460; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_461; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_462; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_463; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_464; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_465; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_466; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_467; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_468; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_469; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_470; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_471; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_472; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_473; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_474; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_475; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_476; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_477; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_478; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_479; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_480; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_481; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_482; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_483; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_484; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_485; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_486; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_487; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_488; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_489; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_490; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_491; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_492; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_493; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_494; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_495; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_496; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_497; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_498; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_499; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_500; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_501; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_502; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_503; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_504; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_505; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_506; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_507; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_508; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_509; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_510; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [2:0] state_vec_511; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17] + reg [8:0] touch_set_0_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:368:60] + reg touch_way_0_valid_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:369:53] + reg [1:0] touch_way_0_bits_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:370:70] + reg allocWriteWay_REG_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:401:41] + reg allocWriteWay_REG_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:401:41] + reg allocWriteWay_REG_2; // @[src/main/scala/xiangshan/frontend/FTB.scala:401:41] + reg allocWriteWay_REG_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:401:41] wire [511:0][2:0] _GEN = {{state_vec_511}, {state_vec_510}, @@ -1354,11 +1353,11 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 {state_vec_3}, {state_vec_2}, {state_vec_1}, - {state_vec_0}}; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, :374:17 - wire [2:0] _GEN_0 = _GEN[io_update_pc[9:1]]; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + {state_vec_0}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:243:38, :374:17] + wire [2:0] _GEN_0 = _GEN[io_update_pc[9:1]]; // @[rocket-chip/src/main/scala/util/Replacement.scala:243:38, src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] wire [2:0] _allocWriteWay_w_T_4 = - ~{allocWriteWay_REG_2, allocWriteWay_REG_1, allocWriteWay_REG_0}; // src/main/scala/xiangshan/frontend/FTB.scala:382:60, :401:{41,79} - wire [1:0] write_way_bits = + ~{allocWriteWay_REG_2, allocWriteWay_REG_1, allocWriteWay_REG_0}; // @[src/main/scala/xiangshan/frontend/FTB.scala:382:60, :401:{41,79}] + wire [1:0] u_way = io_update_write_alloc ? ((&{allocWriteWay_REG_3, allocWriteWay_REG_2, @@ -1368,6445 +1367,4397 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : _allocWriteWay_w_T_4[0] ? 2'h0 : _allocWriteWay_w_T_4[1] ? 2'h1 : {1'h1, ~(_allocWriteWay_w_T_4[2])}) - : io_update_write_way; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/Mux.scala:30:73, :50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/FTB.scala:346:71, :381:37, :382:{17,60}, :401:{41,79}, :402:20 - always @(posedge clock) begin - pred_rdata_REG <= io_req_pc_valid & ~io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:315:{62,79,82} - if (pred_rdata_REG) begin // src/main/scala/xiangshan/frontend/FTB.scala:315:62 - pred_rdata_hold_data_0_entry_valid <= _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + : io_update_write_way; // @[rocket-chip/src/main/scala/util/Replacement.scala:243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/Mux.scala:30:73, :50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/FTB.scala:346:71, :381:37, :382:{17,60}, :401:{41,79}, :402:20] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + pred_rdata_REG <= io_req_pc_valid & ~io_update_access; // @[src/main/scala/xiangshan/frontend/FTB.scala:315:{62,79,82}] + if (pred_rdata_REG) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:315:62] + pred_rdata_hold_data_0_entry_valid <= _ftb_io_r_resp_data_0_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_brSlots_0_offset <= - _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_brSlots_0_lower <= - _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_brSlots_0_tarStat <= - _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_brSlots_0_sharing <= - _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_brSlots_0_valid <= - _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_offset <= - _ftb_io_r_resp_data_0_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_lower <= - _ftb_io_r_resp_data_0_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_tarStat <= - _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_sharing <= - _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_valid <= - _ftb_io_r_resp_data_0_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_pftAddr <= _ftb_io_r_resp_data_0_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_carry <= _ftb_io_r_resp_data_0_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isCall <= _ftb_io_r_resp_data_0_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isRet <= _ftb_io_r_resp_data_0_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isJalr <= _ftb_io_r_resp_data_0_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_pftAddr <= _ftb_io_r_resp_data_0_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_carry <= _ftb_io_r_resp_data_0_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isCall <= _ftb_io_r_resp_data_0_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isRet <= _ftb_io_r_resp_data_0_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isJalr <= _ftb_io_r_resp_data_0_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_last_may_be_rvi_call <= - _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_always_taken_0 <= - _ftb_io_r_resp_data_0_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_always_taken_1 <= - _ftb_io_r_resp_data_0_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_tag <= _ftb_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_valid <= _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_0_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_tag <= _ftb_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_valid <= _ftb_io_r_resp_data_1_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_offset <= - _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_lower <= - _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_tarStat <= - _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_sharing <= - _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_valid <= - _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_tailSlot_offset <= - _ftb_io_r_resp_data_1_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_tailSlot_lower <= - _ftb_io_r_resp_data_1_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_tailSlot_tarStat <= - _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_tailSlot_sharing <= - _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_tailSlot_valid <= - _ftb_io_r_resp_data_1_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_pftAddr <= _ftb_io_r_resp_data_1_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_carry <= _ftb_io_r_resp_data_1_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isCall <= _ftb_io_r_resp_data_1_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isRet <= _ftb_io_r_resp_data_1_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isJalr <= _ftb_io_r_resp_data_1_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_pftAddr <= _ftb_io_r_resp_data_1_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_carry <= _ftb_io_r_resp_data_1_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isCall <= _ftb_io_r_resp_data_1_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isRet <= _ftb_io_r_resp_data_1_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isJalr <= _ftb_io_r_resp_data_1_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_last_may_be_rvi_call <= - _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_always_taken_0 <= - _ftb_io_r_resp_data_1_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_always_taken_1 <= - _ftb_io_r_resp_data_1_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_tag <= _ftb_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_valid <= _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_1_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_tag <= _ftb_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_valid <= _ftb_io_r_resp_data_2_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_brSlots_0_offset <= - _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_brSlots_0_lower <= - _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_brSlots_0_tarStat <= - _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_brSlots_0_sharing <= - _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_brSlots_0_valid <= - _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_offset <= - _ftb_io_r_resp_data_2_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_lower <= - _ftb_io_r_resp_data_2_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_tarStat <= - _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_sharing <= - _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_valid <= - _ftb_io_r_resp_data_2_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_pftAddr <= _ftb_io_r_resp_data_2_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_carry <= _ftb_io_r_resp_data_2_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isCall <= _ftb_io_r_resp_data_2_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isRet <= _ftb_io_r_resp_data_2_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isJalr <= _ftb_io_r_resp_data_2_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_pftAddr <= _ftb_io_r_resp_data_2_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_carry <= _ftb_io_r_resp_data_2_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isCall <= _ftb_io_r_resp_data_2_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isRet <= _ftb_io_r_resp_data_2_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isJalr <= _ftb_io_r_resp_data_2_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_last_may_be_rvi_call <= - _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_always_taken_0 <= - _ftb_io_r_resp_data_2_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_always_taken_1 <= - _ftb_io_r_resp_data_2_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_tag <= _ftb_io_r_resp_data_2_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_valid <= _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_2_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_tag <= _ftb_io_r_resp_data_2_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_valid <= _ftb_io_r_resp_data_3_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_offset <= - _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_lower <= - _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_tarStat <= - _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_sharing <= - _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_valid <= - _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_tailSlot_offset <= - _ftb_io_r_resp_data_3_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_tailSlot_lower <= - _ftb_io_r_resp_data_3_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_tailSlot_tarStat <= - _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_tailSlot_sharing <= - _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_tailSlot_valid <= - _ftb_io_r_resp_data_3_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_pftAddr <= _ftb_io_r_resp_data_3_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_carry <= _ftb_io_r_resp_data_3_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isCall <= _ftb_io_r_resp_data_3_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isRet <= _ftb_io_r_resp_data_3_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isJalr <= _ftb_io_r_resp_data_3_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_pftAddr <= _ftb_io_r_resp_data_3_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_carry <= _ftb_io_r_resp_data_3_entry_carry; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isCall <= _ftb_io_r_resp_data_3_entry_isCall; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isRet <= _ftb_io_r_resp_data_3_entry_isRet; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isJalr <= _ftb_io_r_resp_data_3_entry_isJalr; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_last_may_be_rvi_call <= - _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_always_taken_0 <= - _ftb_io_r_resp_data_3_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_always_taken_1 <= - _ftb_io_r_resp_data_3_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_tag <= _ftb_io_r_resp_data_3_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + _ftb_io_r_resp_data_3_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_tag <= _ftb_io_r_resp_data_3_tag; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82] end - if (io_req_pc_valid) begin // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - req_tag <= io_req_pc_bits[29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:324:{28,59} - req_idx <= io_req_pc_bits[9:1]; // src/main/scala/xiangshan/frontend/FTB.scala:325:28, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + if (io_req_pc_valid) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + req_tag <= io_req_pc_bits[29:10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:324:{28,59}] + req_idx <= io_req_pc_bits[9:1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:325:28, src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] end - if (io_u_req_pc_valid) // src/main/scala/xiangshan/frontend/FTB.scala:291:16 - u_req_tag <= io_u_req_pc_bits[29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:327:{30,63} - u_total_hits_REG <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 - u_total_hits_REG_1 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 - u_total_hits_REG_2 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 - u_total_hits_REG_3 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 - touch_set_0_REG <= req_idx; // src/main/scala/xiangshan/frontend/FTB.scala:325:28, :368:60 - touch_way_0_valid_REG <= read_way_valid; // src/main/scala/xiangshan/frontend/FTB.scala:333:34, :369:53 - touch_way_0_bits_REG <= read_way_bits; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:370:70 - allocWriteWay_REG_0 <= _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 - allocWriteWay_REG_1 <= _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 - allocWriteWay_REG_2 <= _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 - allocWriteWay_REG_3 <= _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 + if (io_u_req_pc_valid) // @[src/main/scala/xiangshan/frontend/FTB.scala:291:16] + u_req_tag <= io_u_req_pc_bits[29:10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:327:{30,63}] + u_total_hits_REG <= io_update_access; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] + u_total_hits_REG_1 <= io_update_access; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] + u_total_hits_REG_2 <= io_update_access; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] + u_total_hits_REG_3 <= io_update_access; // @[src/main/scala/xiangshan/frontend/FTB.scala:338:96] + touch_set_0_REG <= req_idx; // @[src/main/scala/xiangshan/frontend/FTB.scala:325:28, :368:60] + touch_way_0_valid_REG <= hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:333:34, :369:53] + touch_way_0_bits_REG <= hit_way; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:370:70] + allocWriteWay_REG_0 <= _ftb_io_r_resp_data_0_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41] + allocWriteWay_REG_1 <= _ftb_io_r_resp_data_1_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41] + allocWriteWay_REG_2 <= _ftb_io_r_resp_data_2_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41] + allocWriteWay_REG_3 <= _ftb_io_r_resp_data_3_entry_valid; // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41] end // always @(posedge) wire [8:0] touch_set_0 = - io_update_write_data_valid ? io_update_pc[9:1] : touch_set_0_REG; // src/main/scala/xiangshan/frontend/FTB.scala:368:{24,60}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + io_update_write_data_valid ? io_update_pc[9:1] : touch_set_0_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:368:{24,60}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] wire touch_way_0_valid = - io_update_write_data_valid | touch_way_0_valid_REG; // src/main/scala/xiangshan/frontend/FTB.scala:369:{43,53} - wire [1:0] set_touch_ways_0_511_bits = - io_update_write_data_valid ? write_way_bits : touch_way_0_bits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:370:{29,70}, :402:20 - always @(posedge clock or posedge reset) begin - if (reset) begin - state_vec_0 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_1 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_2 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_3 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_4 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_5 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_6 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_7 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_8 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_9 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_10 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_11 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_12 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_13 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_14 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_15 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_16 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_17 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_18 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_19 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_20 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_21 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_22 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_23 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_24 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_25 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_26 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_27 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_28 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_29 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_30 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_31 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_32 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_33 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_34 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_35 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_36 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_37 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_38 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_39 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_40 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_41 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_42 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_43 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_44 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_45 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_46 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_47 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_48 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_49 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_50 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_51 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_52 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_53 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_54 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_55 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_56 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_57 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_58 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_59 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_60 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_61 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_62 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_63 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_64 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_65 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_66 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_67 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_68 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_69 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_70 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_71 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_72 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_73 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_74 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_75 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_76 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_77 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_78 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_79 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_80 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_81 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_82 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_83 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_84 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_85 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_86 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_87 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_88 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_89 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_90 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_91 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_92 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_93 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_94 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_95 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_96 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_97 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_98 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_99 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_100 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_101 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_102 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_103 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_104 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_105 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_106 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_107 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_108 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_109 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_110 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_111 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_112 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_113 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_114 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_115 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_116 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_117 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_118 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_119 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_120 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_121 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_122 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_123 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_124 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_125 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_126 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_127 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_128 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_129 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_130 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_131 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_132 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_133 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_134 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_135 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_136 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_137 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_138 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_139 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_140 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_141 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_142 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_143 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_144 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_145 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_146 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_147 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_148 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_149 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_150 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_151 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_152 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_153 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_154 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_155 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_156 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_157 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_158 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_159 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_160 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_161 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_162 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_163 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_164 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_165 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_166 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_167 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_168 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_169 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_170 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_171 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_172 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_173 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_174 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_175 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_176 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_177 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_178 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_179 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_180 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_181 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_182 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_183 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_184 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_185 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_186 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_187 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_188 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_189 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_190 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_191 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_192 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_193 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_194 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_195 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_196 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_197 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_198 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_199 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_200 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_201 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_202 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_203 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_204 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_205 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_206 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_207 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_208 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_209 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_210 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_211 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_212 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_213 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_214 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_215 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_216 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_217 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_218 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_219 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_220 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_221 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_222 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_223 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_224 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_225 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_226 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_227 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_228 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_229 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_230 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_231 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_232 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_233 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_234 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_235 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_236 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_237 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_238 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_239 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_240 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_241 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_242 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_243 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_244 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_245 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_246 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_247 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_248 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_249 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_250 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_251 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_252 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_253 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_254 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_255 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_256 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_257 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_258 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_259 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_260 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_261 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_262 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_263 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_264 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_265 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_266 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_267 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_268 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_269 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_270 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_271 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_272 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_273 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_274 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_275 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_276 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_277 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_278 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_279 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_280 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_281 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_282 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_283 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_284 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_285 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_286 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_287 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_288 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_289 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_290 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_291 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_292 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_293 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_294 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_295 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_296 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_297 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_298 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_299 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_300 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_301 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_302 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_303 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_304 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_305 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_306 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_307 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_308 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_309 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_310 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_311 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_312 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_313 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_314 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_315 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_316 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_317 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_318 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_319 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_320 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_321 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_322 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_323 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_324 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_325 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_326 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_327 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_328 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_329 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_330 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_331 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_332 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_333 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_334 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_335 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_336 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_337 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_338 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_339 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_340 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_341 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_342 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_343 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_344 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_345 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_346 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_347 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_348 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_349 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_350 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_351 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_352 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_353 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_354 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_355 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_356 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_357 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_358 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_359 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_360 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_361 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_362 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_363 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_364 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_365 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_366 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_367 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_368 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_369 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_370 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_371 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_372 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_373 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_374 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_375 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_376 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_377 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_378 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_379 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_380 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_381 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_382 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_383 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_384 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_385 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_386 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_387 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_388 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_389 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_390 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_391 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_392 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_393 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_394 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_395 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_396 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_397 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_398 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_399 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_400 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_401 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_402 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_403 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_404 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_405 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_406 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_407 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_408 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_409 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_410 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_411 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_412 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_413 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_414 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_415 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_416 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_417 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_418 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_419 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_420 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_421 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_422 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_423 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_424 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_425 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_426 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_427 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_428 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_429 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_430 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_431 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_432 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_433 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_434 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_435 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_436 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_437 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_438 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_439 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_440 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_441 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_442 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_443 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_444 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_445 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_446 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_447 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_448 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_449 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_450 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_451 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_452 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_453 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_454 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_455 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_456 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_457 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_458 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_459 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_460 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_461 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_462 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_463 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_464 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_465 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_466 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_467 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_468 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_469 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_470 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_471 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_472 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_473 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_474 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_475 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_476 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_477 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_478 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_479 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_480 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_481 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_482 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_483 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_484 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_485 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_486 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_487 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_488 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_489 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_490 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_491 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_492 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_493 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_494 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_495 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_496 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_497 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_498 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_499 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_500 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_501 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_502 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_503 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_504 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_505 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_506 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_507 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_508 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_509 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_510 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_511 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + io_update_write_data_valid | touch_way_0_valid_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:369:{43,53}] + wire [1:0] touch_way_0_bits = + io_update_write_data_valid ? u_way : touch_way_0_bits_REG; // @[src/main/scala/xiangshan/frontend/FTB.scala:370:{29,70}, :402:20] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + if (reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_0 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_1 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_2 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_3 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_4 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_5 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_6 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_7 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_8 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_9 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_10 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_11 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_12 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_13 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_14 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_15 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_16 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_17 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_18 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_19 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_20 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_21 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_22 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_23 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_24 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_25 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_26 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_27 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_28 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_29 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_30 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_31 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_32 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_33 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_34 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_35 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_36 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_37 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_38 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_39 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_40 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_41 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_42 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_43 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_44 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_45 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_46 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_47 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_48 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_49 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_50 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_51 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_52 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_53 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_54 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_55 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_56 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_57 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_58 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_59 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_60 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_61 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_62 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_63 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_64 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_65 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_66 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_67 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_68 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_69 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_70 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_71 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_72 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_73 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_74 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_75 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_76 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_77 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_78 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_79 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_80 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_81 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_82 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_83 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_84 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_85 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_86 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_87 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_88 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_89 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_90 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_91 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_92 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_93 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_94 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_95 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_96 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_97 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_98 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_99 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_100 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_101 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_102 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_103 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_104 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_105 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_106 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_107 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_108 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_109 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_110 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_111 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_112 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_113 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_114 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_115 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_116 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_117 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_118 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_119 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_120 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_121 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_122 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_123 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_124 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_125 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_126 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_127 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_128 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_129 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_130 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_131 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_132 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_133 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_134 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_135 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_136 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_137 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_138 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_139 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_140 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_141 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_142 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_143 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_144 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_145 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_146 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_147 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_148 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_149 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_150 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_151 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_152 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_153 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_154 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_155 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_156 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_157 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_158 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_159 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_160 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_161 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_162 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_163 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_164 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_165 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_166 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_167 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_168 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_169 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_170 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_171 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_172 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_173 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_174 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_175 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_176 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_177 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_178 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_179 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_180 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_181 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_182 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_183 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_184 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_185 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_186 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_187 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_188 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_189 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_190 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_191 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_192 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_193 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_194 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_195 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_196 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_197 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_198 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_199 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_200 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_201 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_202 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_203 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_204 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_205 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_206 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_207 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_208 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_209 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_210 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_211 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_212 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_213 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_214 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_215 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_216 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_217 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_218 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_219 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_220 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_221 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_222 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_223 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_224 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_225 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_226 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_227 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_228 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_229 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_230 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_231 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_232 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_233 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_234 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_235 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_236 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_237 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_238 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_239 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_240 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_241 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_242 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_243 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_244 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_245 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_246 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_247 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_248 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_249 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_250 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_251 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_252 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_253 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_254 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_255 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_256 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_257 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_258 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_259 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_260 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_261 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_262 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_263 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_264 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_265 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_266 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_267 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_268 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_269 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_270 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_271 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_272 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_273 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_274 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_275 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_276 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_277 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_278 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_279 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_280 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_281 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_282 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_283 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_284 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_285 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_286 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_287 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_288 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_289 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_290 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_291 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_292 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_293 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_294 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_295 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_296 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_297 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_298 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_299 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_300 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_301 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_302 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_303 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_304 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_305 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_306 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_307 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_308 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_309 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_310 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_311 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_312 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_313 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_314 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_315 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_316 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_317 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_318 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_319 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_320 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_321 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_322 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_323 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_324 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_325 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_326 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_327 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_328 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_329 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_330 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_331 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_332 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_333 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_334 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_335 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_336 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_337 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_338 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_339 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_340 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_341 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_342 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_343 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_344 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_345 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_346 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_347 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_348 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_349 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_350 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_351 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_352 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_353 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_354 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_355 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_356 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_357 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_358 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_359 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_360 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_361 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_362 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_363 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_364 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_365 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_366 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_367 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_368 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_369 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_370 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_371 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_372 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_373 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_374 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_375 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_376 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_377 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_378 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_379 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_380 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_381 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_382 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_383 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_384 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_385 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_386 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_387 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_388 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_389 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_390 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_391 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_392 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_393 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_394 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_395 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_396 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_397 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_398 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_399 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_400 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_401 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_402 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_403 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_404 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_405 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_406 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_407 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_408 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_409 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_410 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_411 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_412 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_413 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_414 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_415 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_416 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_417 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_418 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_419 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_420 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_421 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_422 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_423 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_424 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_425 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_426 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_427 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_428 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_429 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_430 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_431 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_432 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_433 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_434 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_435 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_436 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_437 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_438 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_439 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_440 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_441 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_442 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_443 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_444 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_445 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_446 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_447 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_448 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_449 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_450 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_451 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_452 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_453 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_454 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_455 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_456 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_457 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_458 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_459 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_460 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_461 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_462 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_463 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_464 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_465 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_466 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_467 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_468 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_469 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_470 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_471 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_472 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_473 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_474 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_475 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_476 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_477 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_478 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_479 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_480 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_481 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_482 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_483 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_484 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_485 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_486 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_487 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_488 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_489 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_490 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_491 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_492 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_493 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_494 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_495 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_496 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_497 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_498 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_499 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_500 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_501 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_502 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_503 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_504 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_505 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_506 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_507 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_508 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_509 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_510 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_511 <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] end - else begin - if (touch_way_0_valid & touch_set_0 == 9'h0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + else begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + if (touch_way_0_valid & touch_set_0 == 9'h0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_0 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_0[1], - set_touch_ways_0_511_bits[1] - ? state_vec_0[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_0[1], + touch_way_0_bits[1] ? state_vec_0[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_1 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_1[1], - set_touch_ways_0_511_bits[1] - ? state_vec_1[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_1[1], + touch_way_0_bits[1] ? state_vec_1[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_2 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_2[1], - set_touch_ways_0_511_bits[1] - ? state_vec_2[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_2[1], + touch_way_0_bits[1] ? state_vec_2[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_3 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_3[1], - set_touch_ways_0_511_bits[1] - ? state_vec_3[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_3[1], + touch_way_0_bits[1] ? state_vec_3[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_4 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_4[1], - set_touch_ways_0_511_bits[1] - ? state_vec_4[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_4[1], + touch_way_0_bits[1] ? state_vec_4[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_5 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_5[1], - set_touch_ways_0_511_bits[1] - ? state_vec_5[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_5[1], + touch_way_0_bits[1] ? state_vec_5[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_6 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_6[1], - set_touch_ways_0_511_bits[1] - ? state_vec_6[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_6[1], + touch_way_0_bits[1] ? state_vec_6[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_7 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_7[1], - set_touch_ways_0_511_bits[1] - ? state_vec_7[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_7[1], + touch_way_0_bits[1] ? state_vec_7[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_8 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_8[1], - set_touch_ways_0_511_bits[1] - ? state_vec_8[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_8[1], + touch_way_0_bits[1] ? state_vec_8[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_9 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_9[1], - set_touch_ways_0_511_bits[1] - ? state_vec_9[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_9[1], + touch_way_0_bits[1] ? state_vec_9[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_10 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_10[1], - set_touch_ways_0_511_bits[1] - ? state_vec_10[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_10[1], + touch_way_0_bits[1] ? state_vec_10[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_11 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_11[1], - set_touch_ways_0_511_bits[1] - ? state_vec_11[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_11[1], + touch_way_0_bits[1] ? state_vec_11[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_12 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_12[1], - set_touch_ways_0_511_bits[1] - ? state_vec_12[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_12[1], + touch_way_0_bits[1] ? state_vec_12[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_13 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_13[1], - set_touch_ways_0_511_bits[1] - ? state_vec_13[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_13[1], + touch_way_0_bits[1] ? state_vec_13[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_14 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_14[1], - set_touch_ways_0_511_bits[1] - ? state_vec_14[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_14[1], + touch_way_0_bits[1] ? state_vec_14[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_15 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_15[1], - set_touch_ways_0_511_bits[1] - ? state_vec_15[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_15[1], + touch_way_0_bits[1] ? state_vec_15[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_16 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_16[1], - set_touch_ways_0_511_bits[1] - ? state_vec_16[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_16[1], + touch_way_0_bits[1] ? state_vec_16[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_17 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_17[1], - set_touch_ways_0_511_bits[1] - ? state_vec_17[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_17[1], + touch_way_0_bits[1] ? state_vec_17[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_18 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_18[1], - set_touch_ways_0_511_bits[1] - ? state_vec_18[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_18[1], + touch_way_0_bits[1] ? state_vec_18[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_19 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_19[1], - set_touch_ways_0_511_bits[1] - ? state_vec_19[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_19[1], + touch_way_0_bits[1] ? state_vec_19[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_20 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_20[1], - set_touch_ways_0_511_bits[1] - ? state_vec_20[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_20[1], + touch_way_0_bits[1] ? state_vec_20[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_21 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_21[1], - set_touch_ways_0_511_bits[1] - ? state_vec_21[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_21[1], + touch_way_0_bits[1] ? state_vec_21[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_22 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_22[1], - set_touch_ways_0_511_bits[1] - ? state_vec_22[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_22[1], + touch_way_0_bits[1] ? state_vec_22[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_23 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_23[1], - set_touch_ways_0_511_bits[1] - ? state_vec_23[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_23[1], + touch_way_0_bits[1] ? state_vec_23[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_24 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_24[1], - set_touch_ways_0_511_bits[1] - ? state_vec_24[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_24[1], + touch_way_0_bits[1] ? state_vec_24[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_25 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_25[1], - set_touch_ways_0_511_bits[1] - ? state_vec_25[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_25[1], + touch_way_0_bits[1] ? state_vec_25[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_26 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_26[1], - set_touch_ways_0_511_bits[1] - ? state_vec_26[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_26[1], + touch_way_0_bits[1] ? state_vec_26[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_27 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_27[1], - set_touch_ways_0_511_bits[1] - ? state_vec_27[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_27[1], + touch_way_0_bits[1] ? state_vec_27[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_28 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_28[1], - set_touch_ways_0_511_bits[1] - ? state_vec_28[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_28[1], + touch_way_0_bits[1] ? state_vec_28[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_29 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_29[1], - set_touch_ways_0_511_bits[1] - ? state_vec_29[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_29[1], + touch_way_0_bits[1] ? state_vec_29[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_30 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_30[1], - set_touch_ways_0_511_bits[1] - ? state_vec_30[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_30[1], + touch_way_0_bits[1] ? state_vec_30[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_31 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_31[1], - set_touch_ways_0_511_bits[1] - ? state_vec_31[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h20) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_31[1], + touch_way_0_bits[1] ? state_vec_31[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h20) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_32 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_32[1], - set_touch_ways_0_511_bits[1] - ? state_vec_32[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h21) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_32[1], + touch_way_0_bits[1] ? state_vec_32[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h21) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_33 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_33[1], - set_touch_ways_0_511_bits[1] - ? state_vec_33[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h22) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_33[1], + touch_way_0_bits[1] ? state_vec_33[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h22) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_34 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_34[1], - set_touch_ways_0_511_bits[1] - ? state_vec_34[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h23) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_34[1], + touch_way_0_bits[1] ? state_vec_34[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h23) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_35 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_35[1], - set_touch_ways_0_511_bits[1] - ? state_vec_35[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h24) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_35[1], + touch_way_0_bits[1] ? state_vec_35[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h24) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_36 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_36[1], - set_touch_ways_0_511_bits[1] - ? state_vec_36[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h25) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_36[1], + touch_way_0_bits[1] ? state_vec_36[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h25) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_37 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_37[1], - set_touch_ways_0_511_bits[1] - ? state_vec_37[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h26) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_37[1], + touch_way_0_bits[1] ? state_vec_37[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h26) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_38 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_38[1], - set_touch_ways_0_511_bits[1] - ? state_vec_38[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h27) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_38[1], + touch_way_0_bits[1] ? state_vec_38[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h27) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_39 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_39[1], - set_touch_ways_0_511_bits[1] - ? state_vec_39[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h28) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_39[1], + touch_way_0_bits[1] ? state_vec_39[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h28) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_40 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_40[1], - set_touch_ways_0_511_bits[1] - ? state_vec_40[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h29) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_40[1], + touch_way_0_bits[1] ? state_vec_40[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h29) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_41 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_41[1], - set_touch_ways_0_511_bits[1] - ? state_vec_41[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_41[1], + touch_way_0_bits[1] ? state_vec_41[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_42 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_42[1], - set_touch_ways_0_511_bits[1] - ? state_vec_42[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_42[1], + touch_way_0_bits[1] ? state_vec_42[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_43 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_43[1], - set_touch_ways_0_511_bits[1] - ? state_vec_43[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_43[1], + touch_way_0_bits[1] ? state_vec_43[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_44 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_44[1], - set_touch_ways_0_511_bits[1] - ? state_vec_44[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_44[1], + touch_way_0_bits[1] ? state_vec_44[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_45 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_45[1], - set_touch_ways_0_511_bits[1] - ? state_vec_45[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_45[1], + touch_way_0_bits[1] ? state_vec_45[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_46 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_46[1], - set_touch_ways_0_511_bits[1] - ? state_vec_46[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h2F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_46[1], + touch_way_0_bits[1] ? state_vec_46[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h2F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_47 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_47[1], - set_touch_ways_0_511_bits[1] - ? state_vec_47[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h30) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_47[1], + touch_way_0_bits[1] ? state_vec_47[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h30) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_48 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_48[1], - set_touch_ways_0_511_bits[1] - ? state_vec_48[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h31) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_48[1], + touch_way_0_bits[1] ? state_vec_48[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h31) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_49 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_49[1], - set_touch_ways_0_511_bits[1] - ? state_vec_49[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h32) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_49[1], + touch_way_0_bits[1] ? state_vec_49[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h32) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_50 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_50[1], - set_touch_ways_0_511_bits[1] - ? state_vec_50[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h33) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_50[1], + touch_way_0_bits[1] ? state_vec_50[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h33) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_51 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_51[1], - set_touch_ways_0_511_bits[1] - ? state_vec_51[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h34) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_51[1], + touch_way_0_bits[1] ? state_vec_51[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h34) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_52 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_52[1], - set_touch_ways_0_511_bits[1] - ? state_vec_52[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h35) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_52[1], + touch_way_0_bits[1] ? state_vec_52[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h35) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_53 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_53[1], - set_touch_ways_0_511_bits[1] - ? state_vec_53[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h36) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_53[1], + touch_way_0_bits[1] ? state_vec_53[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h36) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_54 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_54[1], - set_touch_ways_0_511_bits[1] - ? state_vec_54[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h37) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_54[1], + touch_way_0_bits[1] ? state_vec_54[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h37) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_55 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_55[1], - set_touch_ways_0_511_bits[1] - ? state_vec_55[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h38) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_55[1], + touch_way_0_bits[1] ? state_vec_55[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h38) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_56 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_56[1], - set_touch_ways_0_511_bits[1] - ? state_vec_56[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h39) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_56[1], + touch_way_0_bits[1] ? state_vec_56[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h39) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_57 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_57[1], - set_touch_ways_0_511_bits[1] - ? state_vec_57[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_57[1], + touch_way_0_bits[1] ? state_vec_57[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_58 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_58[1], - set_touch_ways_0_511_bits[1] - ? state_vec_58[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_58[1], + touch_way_0_bits[1] ? state_vec_58[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_59 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_59[1], - set_touch_ways_0_511_bits[1] - ? state_vec_59[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_59[1], + touch_way_0_bits[1] ? state_vec_59[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_60 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_60[1], - set_touch_ways_0_511_bits[1] - ? state_vec_60[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_60[1], + touch_way_0_bits[1] ? state_vec_60[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_61 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_61[1], - set_touch_ways_0_511_bits[1] - ? state_vec_61[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_61[1], + touch_way_0_bits[1] ? state_vec_61[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_62 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_62[1], - set_touch_ways_0_511_bits[1] - ? state_vec_62[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h3F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_62[1], + touch_way_0_bits[1] ? state_vec_62[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h3F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_63 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_63[1], - set_touch_ways_0_511_bits[1] - ? state_vec_63[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h40) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_63[1], + touch_way_0_bits[1] ? state_vec_63[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h40) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_64 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_64[1], - set_touch_ways_0_511_bits[1] - ? state_vec_64[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h41) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_64[1], + touch_way_0_bits[1] ? state_vec_64[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h41) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_65 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_65[1], - set_touch_ways_0_511_bits[1] - ? state_vec_65[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h42) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_65[1], + touch_way_0_bits[1] ? state_vec_65[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h42) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_66 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_66[1], - set_touch_ways_0_511_bits[1] - ? state_vec_66[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h43) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_66[1], + touch_way_0_bits[1] ? state_vec_66[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h43) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_67 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_67[1], - set_touch_ways_0_511_bits[1] - ? state_vec_67[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h44) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_67[1], + touch_way_0_bits[1] ? state_vec_67[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h44) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_68 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_68[1], - set_touch_ways_0_511_bits[1] - ? state_vec_68[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h45) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_68[1], + touch_way_0_bits[1] ? state_vec_68[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h45) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_69 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_69[1], - set_touch_ways_0_511_bits[1] - ? state_vec_69[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h46) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_69[1], + touch_way_0_bits[1] ? state_vec_69[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h46) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_70 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_70[1], - set_touch_ways_0_511_bits[1] - ? state_vec_70[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h47) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_70[1], + touch_way_0_bits[1] ? state_vec_70[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h47) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_71 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_71[1], - set_touch_ways_0_511_bits[1] - ? state_vec_71[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h48) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_71[1], + touch_way_0_bits[1] ? state_vec_71[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h48) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_72 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_72[1], - set_touch_ways_0_511_bits[1] - ? state_vec_72[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h49) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_72[1], + touch_way_0_bits[1] ? state_vec_72[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h49) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_73 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_73[1], - set_touch_ways_0_511_bits[1] - ? state_vec_73[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_73[1], + touch_way_0_bits[1] ? state_vec_73[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_74 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_74[1], - set_touch_ways_0_511_bits[1] - ? state_vec_74[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_74[1], + touch_way_0_bits[1] ? state_vec_74[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_75 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_75[1], - set_touch_ways_0_511_bits[1] - ? state_vec_75[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_75[1], + touch_way_0_bits[1] ? state_vec_75[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_76 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_76[1], - set_touch_ways_0_511_bits[1] - ? state_vec_76[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_76[1], + touch_way_0_bits[1] ? state_vec_76[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_77 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_77[1], - set_touch_ways_0_511_bits[1] - ? state_vec_77[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_77[1], + touch_way_0_bits[1] ? state_vec_77[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_78 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_78[1], - set_touch_ways_0_511_bits[1] - ? state_vec_78[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h4F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_78[1], + touch_way_0_bits[1] ? state_vec_78[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h4F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_79 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_79[1], - set_touch_ways_0_511_bits[1] - ? state_vec_79[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h50) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_79[1], + touch_way_0_bits[1] ? state_vec_79[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h50) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_80 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_80[1], - set_touch_ways_0_511_bits[1] - ? state_vec_80[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h51) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_80[1], + touch_way_0_bits[1] ? state_vec_80[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h51) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_81 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_81[1], - set_touch_ways_0_511_bits[1] - ? state_vec_81[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h52) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_81[1], + touch_way_0_bits[1] ? state_vec_81[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h52) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_82 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_82[1], - set_touch_ways_0_511_bits[1] - ? state_vec_82[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h53) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_82[1], + touch_way_0_bits[1] ? state_vec_82[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h53) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_83 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_83[1], - set_touch_ways_0_511_bits[1] - ? state_vec_83[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h54) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_83[1], + touch_way_0_bits[1] ? state_vec_83[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h54) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_84 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_84[1], - set_touch_ways_0_511_bits[1] - ? state_vec_84[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h55) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_84[1], + touch_way_0_bits[1] ? state_vec_84[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h55) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_85 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_85[1], - set_touch_ways_0_511_bits[1] - ? state_vec_85[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h56) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_85[1], + touch_way_0_bits[1] ? state_vec_85[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h56) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_86 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_86[1], - set_touch_ways_0_511_bits[1] - ? state_vec_86[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h57) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_86[1], + touch_way_0_bits[1] ? state_vec_86[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h57) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_87 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_87[1], - set_touch_ways_0_511_bits[1] - ? state_vec_87[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h58) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_87[1], + touch_way_0_bits[1] ? state_vec_87[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h58) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_88 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_88[1], - set_touch_ways_0_511_bits[1] - ? state_vec_88[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h59) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_88[1], + touch_way_0_bits[1] ? state_vec_88[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h59) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_89 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_89[1], - set_touch_ways_0_511_bits[1] - ? state_vec_89[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_89[1], + touch_way_0_bits[1] ? state_vec_89[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_90 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_90[1], - set_touch_ways_0_511_bits[1] - ? state_vec_90[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_90[1], + touch_way_0_bits[1] ? state_vec_90[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_91 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_91[1], - set_touch_ways_0_511_bits[1] - ? state_vec_91[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_91[1], + touch_way_0_bits[1] ? state_vec_91[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_92 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_92[1], - set_touch_ways_0_511_bits[1] - ? state_vec_92[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_92[1], + touch_way_0_bits[1] ? state_vec_92[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_93 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_93[1], - set_touch_ways_0_511_bits[1] - ? state_vec_93[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_93[1], + touch_way_0_bits[1] ? state_vec_93[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_94 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_94[1], - set_touch_ways_0_511_bits[1] - ? state_vec_94[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h5F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_94[1], + touch_way_0_bits[1] ? state_vec_94[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h5F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_95 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_95[1], - set_touch_ways_0_511_bits[1] - ? state_vec_95[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h60) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_95[1], + touch_way_0_bits[1] ? state_vec_95[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h60) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_96 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_96[1], - set_touch_ways_0_511_bits[1] - ? state_vec_96[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h61) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_96[1], + touch_way_0_bits[1] ? state_vec_96[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h61) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_97 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_97[1], - set_touch_ways_0_511_bits[1] - ? state_vec_97[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h62) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_97[1], + touch_way_0_bits[1] ? state_vec_97[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h62) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_98 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_98[1], - set_touch_ways_0_511_bits[1] - ? state_vec_98[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h63) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_98[1], + touch_way_0_bits[1] ? state_vec_98[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h63) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_99 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_99[1], - set_touch_ways_0_511_bits[1] - ? state_vec_99[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h64) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_99[1], + touch_way_0_bits[1] ? state_vec_99[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h64) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_100 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_100[1], - set_touch_ways_0_511_bits[1] - ? state_vec_100[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h65) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_100[1], + touch_way_0_bits[1] ? state_vec_100[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h65) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_101 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_101[1], - set_touch_ways_0_511_bits[1] - ? state_vec_101[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h66) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_101[1], + touch_way_0_bits[1] ? state_vec_101[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h66) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_102 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_102[1], - set_touch_ways_0_511_bits[1] - ? state_vec_102[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h67) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_102[1], + touch_way_0_bits[1] ? state_vec_102[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h67) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_103 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_103[1], - set_touch_ways_0_511_bits[1] - ? state_vec_103[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h68) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_103[1], + touch_way_0_bits[1] ? state_vec_103[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h68) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_104 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_104[1], - set_touch_ways_0_511_bits[1] - ? state_vec_104[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h69) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_104[1], + touch_way_0_bits[1] ? state_vec_104[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h69) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_105 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_105[1], - set_touch_ways_0_511_bits[1] - ? state_vec_105[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_105[1], + touch_way_0_bits[1] ? state_vec_105[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_106 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_106[1], - set_touch_ways_0_511_bits[1] - ? state_vec_106[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_106[1], + touch_way_0_bits[1] ? state_vec_106[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_107 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_107[1], - set_touch_ways_0_511_bits[1] - ? state_vec_107[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_107[1], + touch_way_0_bits[1] ? state_vec_107[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_108 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_108[1], - set_touch_ways_0_511_bits[1] - ? state_vec_108[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_108[1], + touch_way_0_bits[1] ? state_vec_108[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_109 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_109[1], - set_touch_ways_0_511_bits[1] - ? state_vec_109[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_109[1], + touch_way_0_bits[1] ? state_vec_109[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_110 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_110[1], - set_touch_ways_0_511_bits[1] - ? state_vec_110[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h6F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_110[1], + touch_way_0_bits[1] ? state_vec_110[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h6F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_111 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_111[1], - set_touch_ways_0_511_bits[1] - ? state_vec_111[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h70) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_111[1], + touch_way_0_bits[1] ? state_vec_111[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h70) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_112 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_112[1], - set_touch_ways_0_511_bits[1] - ? state_vec_112[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h71) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_112[1], + touch_way_0_bits[1] ? state_vec_112[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h71) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_113 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_113[1], - set_touch_ways_0_511_bits[1] - ? state_vec_113[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h72) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_113[1], + touch_way_0_bits[1] ? state_vec_113[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h72) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_114 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_114[1], - set_touch_ways_0_511_bits[1] - ? state_vec_114[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h73) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_114[1], + touch_way_0_bits[1] ? state_vec_114[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h73) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_115 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_115[1], - set_touch_ways_0_511_bits[1] - ? state_vec_115[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h74) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_115[1], + touch_way_0_bits[1] ? state_vec_115[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h74) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_116 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_116[1], - set_touch_ways_0_511_bits[1] - ? state_vec_116[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h75) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_116[1], + touch_way_0_bits[1] ? state_vec_116[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h75) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_117 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_117[1], - set_touch_ways_0_511_bits[1] - ? state_vec_117[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h76) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_117[1], + touch_way_0_bits[1] ? state_vec_117[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h76) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_118 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_118[1], - set_touch_ways_0_511_bits[1] - ? state_vec_118[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h77) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_118[1], + touch_way_0_bits[1] ? state_vec_118[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h77) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_119 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_119[1], - set_touch_ways_0_511_bits[1] - ? state_vec_119[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h78) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_119[1], + touch_way_0_bits[1] ? state_vec_119[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h78) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_120 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_120[1], - set_touch_ways_0_511_bits[1] - ? state_vec_120[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h79) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_120[1], + touch_way_0_bits[1] ? state_vec_120[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h79) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_121 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_121[1], - set_touch_ways_0_511_bits[1] - ? state_vec_121[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_121[1], + touch_way_0_bits[1] ? state_vec_121[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_122 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_122[1], - set_touch_ways_0_511_bits[1] - ? state_vec_122[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_122[1], + touch_way_0_bits[1] ? state_vec_122[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_123 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_123[1], - set_touch_ways_0_511_bits[1] - ? state_vec_123[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_123[1], + touch_way_0_bits[1] ? state_vec_123[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_124 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_124[1], - set_touch_ways_0_511_bits[1] - ? state_vec_124[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_124[1], + touch_way_0_bits[1] ? state_vec_124[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_125 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_125[1], - set_touch_ways_0_511_bits[1] - ? state_vec_125[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_125[1], + touch_way_0_bits[1] ? state_vec_125[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_126 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_126[1], - set_touch_ways_0_511_bits[1] - ? state_vec_126[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h7F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_126[1], + touch_way_0_bits[1] ? state_vec_126[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h7F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_127 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_127[1], - set_touch_ways_0_511_bits[1] - ? state_vec_127[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h80) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_127[1], + touch_way_0_bits[1] ? state_vec_127[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h80) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_128 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_128[1], - set_touch_ways_0_511_bits[1] - ? state_vec_128[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h81) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_128[1], + touch_way_0_bits[1] ? state_vec_128[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h81) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_129 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_129[1], - set_touch_ways_0_511_bits[1] - ? state_vec_129[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h82) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_129[1], + touch_way_0_bits[1] ? state_vec_129[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h82) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_130 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_130[1], - set_touch_ways_0_511_bits[1] - ? state_vec_130[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h83) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_130[1], + touch_way_0_bits[1] ? state_vec_130[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h83) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_131 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_131[1], - set_touch_ways_0_511_bits[1] - ? state_vec_131[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h84) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_131[1], + touch_way_0_bits[1] ? state_vec_131[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h84) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_132 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_132[1], - set_touch_ways_0_511_bits[1] - ? state_vec_132[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h85) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_132[1], + touch_way_0_bits[1] ? state_vec_132[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h85) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_133 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_133[1], - set_touch_ways_0_511_bits[1] - ? state_vec_133[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h86) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_133[1], + touch_way_0_bits[1] ? state_vec_133[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h86) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_134 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_134[1], - set_touch_ways_0_511_bits[1] - ? state_vec_134[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h87) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_134[1], + touch_way_0_bits[1] ? state_vec_134[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h87) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_135 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_135[1], - set_touch_ways_0_511_bits[1] - ? state_vec_135[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h88) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_135[1], + touch_way_0_bits[1] ? state_vec_135[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h88) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_136 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_136[1], - set_touch_ways_0_511_bits[1] - ? state_vec_136[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h89) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_136[1], + touch_way_0_bits[1] ? state_vec_136[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h89) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_137 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_137[1], - set_touch_ways_0_511_bits[1] - ? state_vec_137[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_137[1], + touch_way_0_bits[1] ? state_vec_137[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_138 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_138[1], - set_touch_ways_0_511_bits[1] - ? state_vec_138[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_138[1], + touch_way_0_bits[1] ? state_vec_138[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_139 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_139[1], - set_touch_ways_0_511_bits[1] - ? state_vec_139[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_139[1], + touch_way_0_bits[1] ? state_vec_139[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_140 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_140[1], - set_touch_ways_0_511_bits[1] - ? state_vec_140[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_140[1], + touch_way_0_bits[1] ? state_vec_140[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_141 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_141[1], - set_touch_ways_0_511_bits[1] - ? state_vec_141[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_141[1], + touch_way_0_bits[1] ? state_vec_141[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_142 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_142[1], - set_touch_ways_0_511_bits[1] - ? state_vec_142[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h8F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_142[1], + touch_way_0_bits[1] ? state_vec_142[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h8F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_143 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_143[1], - set_touch_ways_0_511_bits[1] - ? state_vec_143[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h90) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_143[1], + touch_way_0_bits[1] ? state_vec_143[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h90) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_144 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_144[1], - set_touch_ways_0_511_bits[1] - ? state_vec_144[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h91) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_144[1], + touch_way_0_bits[1] ? state_vec_144[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h91) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_145 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_145[1], - set_touch_ways_0_511_bits[1] - ? state_vec_145[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h92) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_145[1], + touch_way_0_bits[1] ? state_vec_145[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h92) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_146 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_146[1], - set_touch_ways_0_511_bits[1] - ? state_vec_146[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h93) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_146[1], + touch_way_0_bits[1] ? state_vec_146[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h93) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_147 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_147[1], - set_touch_ways_0_511_bits[1] - ? state_vec_147[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h94) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_147[1], + touch_way_0_bits[1] ? state_vec_147[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h94) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_148 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_148[1], - set_touch_ways_0_511_bits[1] - ? state_vec_148[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h95) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_148[1], + touch_way_0_bits[1] ? state_vec_148[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h95) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_149 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_149[1], - set_touch_ways_0_511_bits[1] - ? state_vec_149[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h96) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_149[1], + touch_way_0_bits[1] ? state_vec_149[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h96) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_150 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_150[1], - set_touch_ways_0_511_bits[1] - ? state_vec_150[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h97) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_150[1], + touch_way_0_bits[1] ? state_vec_150[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h97) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_151 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_151[1], - set_touch_ways_0_511_bits[1] - ? state_vec_151[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h98) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_151[1], + touch_way_0_bits[1] ? state_vec_151[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h98) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_152 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_152[1], - set_touch_ways_0_511_bits[1] - ? state_vec_152[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h99) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_152[1], + touch_way_0_bits[1] ? state_vec_152[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h99) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_153 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_153[1], - set_touch_ways_0_511_bits[1] - ? state_vec_153[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_153[1], + touch_way_0_bits[1] ? state_vec_153[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_154 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_154[1], - set_touch_ways_0_511_bits[1] - ? state_vec_154[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_154[1], + touch_way_0_bits[1] ? state_vec_154[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_155 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_155[1], - set_touch_ways_0_511_bits[1] - ? state_vec_155[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_155[1], + touch_way_0_bits[1] ? state_vec_155[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_156 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_156[1], - set_touch_ways_0_511_bits[1] - ? state_vec_156[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_156[1], + touch_way_0_bits[1] ? state_vec_156[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_157 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_157[1], - set_touch_ways_0_511_bits[1] - ? state_vec_157[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_157[1], + touch_way_0_bits[1] ? state_vec_157[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_158 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_158[1], - set_touch_ways_0_511_bits[1] - ? state_vec_158[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h9F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_158[1], + touch_way_0_bits[1] ? state_vec_158[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h9F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_159 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_159[1], - set_touch_ways_0_511_bits[1] - ? state_vec_159[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_159[1], + touch_way_0_bits[1] ? state_vec_159[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_160 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_160[1], - set_touch_ways_0_511_bits[1] - ? state_vec_160[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_160[1], + touch_way_0_bits[1] ? state_vec_160[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_161 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_161[1], - set_touch_ways_0_511_bits[1] - ? state_vec_161[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_161[1], + touch_way_0_bits[1] ? state_vec_161[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_162 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_162[1], - set_touch_ways_0_511_bits[1] - ? state_vec_162[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_162[1], + touch_way_0_bits[1] ? state_vec_162[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_163 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_163[1], - set_touch_ways_0_511_bits[1] - ? state_vec_163[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_163[1], + touch_way_0_bits[1] ? state_vec_163[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_164 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_164[1], - set_touch_ways_0_511_bits[1] - ? state_vec_164[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_164[1], + touch_way_0_bits[1] ? state_vec_164[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_165 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_165[1], - set_touch_ways_0_511_bits[1] - ? state_vec_165[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_165[1], + touch_way_0_bits[1] ? state_vec_165[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_166 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_166[1], - set_touch_ways_0_511_bits[1] - ? state_vec_166[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_166[1], + touch_way_0_bits[1] ? state_vec_166[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_167 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_167[1], - set_touch_ways_0_511_bits[1] - ? state_vec_167[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_167[1], + touch_way_0_bits[1] ? state_vec_167[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_168 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_168[1], - set_touch_ways_0_511_bits[1] - ? state_vec_168[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hA9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_168[1], + touch_way_0_bits[1] ? state_vec_168[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hA9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_169 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_169[1], - set_touch_ways_0_511_bits[1] - ? state_vec_169[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_169[1], + touch_way_0_bits[1] ? state_vec_169[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_170 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_170[1], - set_touch_ways_0_511_bits[1] - ? state_vec_170[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_170[1], + touch_way_0_bits[1] ? state_vec_170[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_171 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_171[1], - set_touch_ways_0_511_bits[1] - ? state_vec_171[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_171[1], + touch_way_0_bits[1] ? state_vec_171[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_172 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_172[1], - set_touch_ways_0_511_bits[1] - ? state_vec_172[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_172[1], + touch_way_0_bits[1] ? state_vec_172[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_173 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_173[1], - set_touch_ways_0_511_bits[1] - ? state_vec_173[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_173[1], + touch_way_0_bits[1] ? state_vec_173[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_174 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_174[1], - set_touch_ways_0_511_bits[1] - ? state_vec_174[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hAF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_174[1], + touch_way_0_bits[1] ? state_vec_174[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hAF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_175 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_175[1], - set_touch_ways_0_511_bits[1] - ? state_vec_175[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_175[1], + touch_way_0_bits[1] ? state_vec_175[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_176 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_176[1], - set_touch_ways_0_511_bits[1] - ? state_vec_176[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_176[1], + touch_way_0_bits[1] ? state_vec_176[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_177 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_177[1], - set_touch_ways_0_511_bits[1] - ? state_vec_177[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_177[1], + touch_way_0_bits[1] ? state_vec_177[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_178 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_178[1], - set_touch_ways_0_511_bits[1] - ? state_vec_178[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_178[1], + touch_way_0_bits[1] ? state_vec_178[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_179 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_179[1], - set_touch_ways_0_511_bits[1] - ? state_vec_179[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_179[1], + touch_way_0_bits[1] ? state_vec_179[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_180 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_180[1], - set_touch_ways_0_511_bits[1] - ? state_vec_180[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_180[1], + touch_way_0_bits[1] ? state_vec_180[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_181 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_181[1], - set_touch_ways_0_511_bits[1] - ? state_vec_181[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_181[1], + touch_way_0_bits[1] ? state_vec_181[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_182 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_182[1], - set_touch_ways_0_511_bits[1] - ? state_vec_182[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_182[1], + touch_way_0_bits[1] ? state_vec_182[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_183 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_183[1], - set_touch_ways_0_511_bits[1] - ? state_vec_183[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_183[1], + touch_way_0_bits[1] ? state_vec_183[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_184 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_184[1], - set_touch_ways_0_511_bits[1] - ? state_vec_184[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hB9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_184[1], + touch_way_0_bits[1] ? state_vec_184[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hB9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_185 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_185[1], - set_touch_ways_0_511_bits[1] - ? state_vec_185[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_185[1], + touch_way_0_bits[1] ? state_vec_185[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_186 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_186[1], - set_touch_ways_0_511_bits[1] - ? state_vec_186[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_186[1], + touch_way_0_bits[1] ? state_vec_186[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_187 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_187[1], - set_touch_ways_0_511_bits[1] - ? state_vec_187[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_187[1], + touch_way_0_bits[1] ? state_vec_187[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_188 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_188[1], - set_touch_ways_0_511_bits[1] - ? state_vec_188[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_188[1], + touch_way_0_bits[1] ? state_vec_188[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_189 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_189[1], - set_touch_ways_0_511_bits[1] - ? state_vec_189[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_189[1], + touch_way_0_bits[1] ? state_vec_189[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_190 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_190[1], - set_touch_ways_0_511_bits[1] - ? state_vec_190[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hBF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_190[1], + touch_way_0_bits[1] ? state_vec_190[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hBF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_191 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_191[1], - set_touch_ways_0_511_bits[1] - ? state_vec_191[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_191[1], + touch_way_0_bits[1] ? state_vec_191[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_192 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_192[1], - set_touch_ways_0_511_bits[1] - ? state_vec_192[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_192[1], + touch_way_0_bits[1] ? state_vec_192[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_193 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_193[1], - set_touch_ways_0_511_bits[1] - ? state_vec_193[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_193[1], + touch_way_0_bits[1] ? state_vec_193[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_194 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_194[1], - set_touch_ways_0_511_bits[1] - ? state_vec_194[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_194[1], + touch_way_0_bits[1] ? state_vec_194[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_195 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_195[1], - set_touch_ways_0_511_bits[1] - ? state_vec_195[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_195[1], + touch_way_0_bits[1] ? state_vec_195[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_196 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_196[1], - set_touch_ways_0_511_bits[1] - ? state_vec_196[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_196[1], + touch_way_0_bits[1] ? state_vec_196[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_197 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_197[1], - set_touch_ways_0_511_bits[1] - ? state_vec_197[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_197[1], + touch_way_0_bits[1] ? state_vec_197[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_198 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_198[1], - set_touch_ways_0_511_bits[1] - ? state_vec_198[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_198[1], + touch_way_0_bits[1] ? state_vec_198[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_199 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_199[1], - set_touch_ways_0_511_bits[1] - ? state_vec_199[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_199[1], + touch_way_0_bits[1] ? state_vec_199[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_200 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_200[1], - set_touch_ways_0_511_bits[1] - ? state_vec_200[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hC9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_200[1], + touch_way_0_bits[1] ? state_vec_200[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hC9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_201 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_201[1], - set_touch_ways_0_511_bits[1] - ? state_vec_201[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_201[1], + touch_way_0_bits[1] ? state_vec_201[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_202 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_202[1], - set_touch_ways_0_511_bits[1] - ? state_vec_202[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_202[1], + touch_way_0_bits[1] ? state_vec_202[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_203 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_203[1], - set_touch_ways_0_511_bits[1] - ? state_vec_203[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_203[1], + touch_way_0_bits[1] ? state_vec_203[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_204 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_204[1], - set_touch_ways_0_511_bits[1] - ? state_vec_204[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_204[1], + touch_way_0_bits[1] ? state_vec_204[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_205 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_205[1], - set_touch_ways_0_511_bits[1] - ? state_vec_205[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_205[1], + touch_way_0_bits[1] ? state_vec_205[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_206 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_206[1], - set_touch_ways_0_511_bits[1] - ? state_vec_206[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hCF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_206[1], + touch_way_0_bits[1] ? state_vec_206[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hCF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_207 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_207[1], - set_touch_ways_0_511_bits[1] - ? state_vec_207[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_207[1], + touch_way_0_bits[1] ? state_vec_207[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_208 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_208[1], - set_touch_ways_0_511_bits[1] - ? state_vec_208[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_208[1], + touch_way_0_bits[1] ? state_vec_208[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_209 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_209[1], - set_touch_ways_0_511_bits[1] - ? state_vec_209[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_209[1], + touch_way_0_bits[1] ? state_vec_209[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_210 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_210[1], - set_touch_ways_0_511_bits[1] - ? state_vec_210[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_210[1], + touch_way_0_bits[1] ? state_vec_210[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_211 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_211[1], - set_touch_ways_0_511_bits[1] - ? state_vec_211[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_211[1], + touch_way_0_bits[1] ? state_vec_211[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_212 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_212[1], - set_touch_ways_0_511_bits[1] - ? state_vec_212[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_212[1], + touch_way_0_bits[1] ? state_vec_212[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_213 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_213[1], - set_touch_ways_0_511_bits[1] - ? state_vec_213[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_213[1], + touch_way_0_bits[1] ? state_vec_213[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_214 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_214[1], - set_touch_ways_0_511_bits[1] - ? state_vec_214[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_214[1], + touch_way_0_bits[1] ? state_vec_214[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_215 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_215[1], - set_touch_ways_0_511_bits[1] - ? state_vec_215[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_215[1], + touch_way_0_bits[1] ? state_vec_215[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_216 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_216[1], - set_touch_ways_0_511_bits[1] - ? state_vec_216[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hD9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_216[1], + touch_way_0_bits[1] ? state_vec_216[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hD9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_217 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_217[1], - set_touch_ways_0_511_bits[1] - ? state_vec_217[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_217[1], + touch_way_0_bits[1] ? state_vec_217[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_218 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_218[1], - set_touch_ways_0_511_bits[1] - ? state_vec_218[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_218[1], + touch_way_0_bits[1] ? state_vec_218[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_219 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_219[1], - set_touch_ways_0_511_bits[1] - ? state_vec_219[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_219[1], + touch_way_0_bits[1] ? state_vec_219[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_220 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_220[1], - set_touch_ways_0_511_bits[1] - ? state_vec_220[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_220[1], + touch_way_0_bits[1] ? state_vec_220[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_221 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_221[1], - set_touch_ways_0_511_bits[1] - ? state_vec_221[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_221[1], + touch_way_0_bits[1] ? state_vec_221[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_222 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_222[1], - set_touch_ways_0_511_bits[1] - ? state_vec_222[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hDF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_222[1], + touch_way_0_bits[1] ? state_vec_222[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hDF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_223 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_223[1], - set_touch_ways_0_511_bits[1] - ? state_vec_223[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_223[1], + touch_way_0_bits[1] ? state_vec_223[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_224 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_224[1], - set_touch_ways_0_511_bits[1] - ? state_vec_224[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_224[1], + touch_way_0_bits[1] ? state_vec_224[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_225 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_225[1], - set_touch_ways_0_511_bits[1] - ? state_vec_225[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_225[1], + touch_way_0_bits[1] ? state_vec_225[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_226 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_226[1], - set_touch_ways_0_511_bits[1] - ? state_vec_226[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_226[1], + touch_way_0_bits[1] ? state_vec_226[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_227 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_227[1], - set_touch_ways_0_511_bits[1] - ? state_vec_227[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_227[1], + touch_way_0_bits[1] ? state_vec_227[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_228 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_228[1], - set_touch_ways_0_511_bits[1] - ? state_vec_228[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_228[1], + touch_way_0_bits[1] ? state_vec_228[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_229 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_229[1], - set_touch_ways_0_511_bits[1] - ? state_vec_229[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_229[1], + touch_way_0_bits[1] ? state_vec_229[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_230 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_230[1], - set_touch_ways_0_511_bits[1] - ? state_vec_230[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_230[1], + touch_way_0_bits[1] ? state_vec_230[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_231 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_231[1], - set_touch_ways_0_511_bits[1] - ? state_vec_231[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_231[1], + touch_way_0_bits[1] ? state_vec_231[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_232 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_232[1], - set_touch_ways_0_511_bits[1] - ? state_vec_232[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hE9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_232[1], + touch_way_0_bits[1] ? state_vec_232[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hE9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_233 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_233[1], - set_touch_ways_0_511_bits[1] - ? state_vec_233[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hEA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_233[1], + touch_way_0_bits[1] ? state_vec_233[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hEA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_234 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_234[1], - set_touch_ways_0_511_bits[1] - ? state_vec_234[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hEB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_234[1], + touch_way_0_bits[1] ? state_vec_234[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hEB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_235 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_235[1], - set_touch_ways_0_511_bits[1] - ? state_vec_235[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hEC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_235[1], + touch_way_0_bits[1] ? state_vec_235[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hEC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_236 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_236[1], - set_touch_ways_0_511_bits[1] - ? state_vec_236[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hED) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_236[1], + touch_way_0_bits[1] ? state_vec_236[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hED) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_237 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_237[1], - set_touch_ways_0_511_bits[1] - ? state_vec_237[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hEE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_237[1], + touch_way_0_bits[1] ? state_vec_237[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hEE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_238 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_238[1], - set_touch_ways_0_511_bits[1] - ? state_vec_238[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hEF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_238[1], + touch_way_0_bits[1] ? state_vec_238[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hEF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_239 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_239[1], - set_touch_ways_0_511_bits[1] - ? state_vec_239[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_239[1], + touch_way_0_bits[1] ? state_vec_239[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_240 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_240[1], - set_touch_ways_0_511_bits[1] - ? state_vec_240[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_240[1], + touch_way_0_bits[1] ? state_vec_240[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_241 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_241[1], - set_touch_ways_0_511_bits[1] - ? state_vec_241[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_241[1], + touch_way_0_bits[1] ? state_vec_241[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_242 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_242[1], - set_touch_ways_0_511_bits[1] - ? state_vec_242[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_242[1], + touch_way_0_bits[1] ? state_vec_242[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_243 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_243[1], - set_touch_ways_0_511_bits[1] - ? state_vec_243[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_243[1], + touch_way_0_bits[1] ? state_vec_243[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_244 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_244[1], - set_touch_ways_0_511_bits[1] - ? state_vec_244[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_244[1], + touch_way_0_bits[1] ? state_vec_244[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_245 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_245[1], - set_touch_ways_0_511_bits[1] - ? state_vec_245[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_245[1], + touch_way_0_bits[1] ? state_vec_245[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_246 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_246[1], - set_touch_ways_0_511_bits[1] - ? state_vec_246[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_246[1], + touch_way_0_bits[1] ? state_vec_246[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_247 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_247[1], - set_touch_ways_0_511_bits[1] - ? state_vec_247[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_247[1], + touch_way_0_bits[1] ? state_vec_247[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_248 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_248[1], - set_touch_ways_0_511_bits[1] - ? state_vec_248[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hF9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_248[1], + touch_way_0_bits[1] ? state_vec_248[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hF9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_249 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_249[1], - set_touch_ways_0_511_bits[1] - ? state_vec_249[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_249[1], + touch_way_0_bits[1] ? state_vec_249[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_250 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_250[1], - set_touch_ways_0_511_bits[1] - ? state_vec_250[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_250[1], + touch_way_0_bits[1] ? state_vec_250[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_251 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_251[1], - set_touch_ways_0_511_bits[1] - ? state_vec_251[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_251[1], + touch_way_0_bits[1] ? state_vec_251[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_252 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_252[1], - set_touch_ways_0_511_bits[1] - ? state_vec_252[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_252[1], + touch_way_0_bits[1] ? state_vec_252[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_253 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_253[1], - set_touch_ways_0_511_bits[1] - ? state_vec_253[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_253[1], + touch_way_0_bits[1] ? state_vec_253[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_254 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_254[1], - set_touch_ways_0_511_bits[1] - ? state_vec_254[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'hFF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_254[1], + touch_way_0_bits[1] ? state_vec_254[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'hFF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_255 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_255[1], - set_touch_ways_0_511_bits[1] - ? state_vec_255[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h100) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_255[1], + touch_way_0_bits[1] ? state_vec_255[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h100) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_256 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_256[1], - set_touch_ways_0_511_bits[1] - ? state_vec_256[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h101) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_256[1], + touch_way_0_bits[1] ? state_vec_256[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h101) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_257 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_257[1], - set_touch_ways_0_511_bits[1] - ? state_vec_257[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h102) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_257[1], + touch_way_0_bits[1] ? state_vec_257[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h102) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_258 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_258[1], - set_touch_ways_0_511_bits[1] - ? state_vec_258[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h103) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_258[1], + touch_way_0_bits[1] ? state_vec_258[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h103) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_259 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_259[1], - set_touch_ways_0_511_bits[1] - ? state_vec_259[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h104) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_259[1], + touch_way_0_bits[1] ? state_vec_259[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h104) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_260 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_260[1], - set_touch_ways_0_511_bits[1] - ? state_vec_260[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h105) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_260[1], + touch_way_0_bits[1] ? state_vec_260[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h105) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_261 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_261[1], - set_touch_ways_0_511_bits[1] - ? state_vec_261[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h106) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_261[1], + touch_way_0_bits[1] ? state_vec_261[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h106) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_262 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_262[1], - set_touch_ways_0_511_bits[1] - ? state_vec_262[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h107) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_262[1], + touch_way_0_bits[1] ? state_vec_262[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h107) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_263 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_263[1], - set_touch_ways_0_511_bits[1] - ? state_vec_263[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h108) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_263[1], + touch_way_0_bits[1] ? state_vec_263[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h108) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_264 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_264[1], - set_touch_ways_0_511_bits[1] - ? state_vec_264[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h109) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_264[1], + touch_way_0_bits[1] ? state_vec_264[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h109) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_265 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_265[1], - set_touch_ways_0_511_bits[1] - ? state_vec_265[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_265[1], + touch_way_0_bits[1] ? state_vec_265[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_266 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_266[1], - set_touch_ways_0_511_bits[1] - ? state_vec_266[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_266[1], + touch_way_0_bits[1] ? state_vec_266[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_267 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_267[1], - set_touch_ways_0_511_bits[1] - ? state_vec_267[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_267[1], + touch_way_0_bits[1] ? state_vec_267[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_268 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_268[1], - set_touch_ways_0_511_bits[1] - ? state_vec_268[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_268[1], + touch_way_0_bits[1] ? state_vec_268[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_269 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_269[1], - set_touch_ways_0_511_bits[1] - ? state_vec_269[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_269[1], + touch_way_0_bits[1] ? state_vec_269[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_270 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_270[1], - set_touch_ways_0_511_bits[1] - ? state_vec_270[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h10F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_270[1], + touch_way_0_bits[1] ? state_vec_270[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h10F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_271 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_271[1], - set_touch_ways_0_511_bits[1] - ? state_vec_271[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h110) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_271[1], + touch_way_0_bits[1] ? state_vec_271[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h110) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_272 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_272[1], - set_touch_ways_0_511_bits[1] - ? state_vec_272[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h111) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_272[1], + touch_way_0_bits[1] ? state_vec_272[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h111) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_273 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_273[1], - set_touch_ways_0_511_bits[1] - ? state_vec_273[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h112) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_273[1], + touch_way_0_bits[1] ? state_vec_273[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h112) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_274 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_274[1], - set_touch_ways_0_511_bits[1] - ? state_vec_274[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h113) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_274[1], + touch_way_0_bits[1] ? state_vec_274[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h113) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_275 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_275[1], - set_touch_ways_0_511_bits[1] - ? state_vec_275[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h114) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_275[1], + touch_way_0_bits[1] ? state_vec_275[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h114) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_276 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_276[1], - set_touch_ways_0_511_bits[1] - ? state_vec_276[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h115) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_276[1], + touch_way_0_bits[1] ? state_vec_276[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h115) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_277 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_277[1], - set_touch_ways_0_511_bits[1] - ? state_vec_277[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h116) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_277[1], + touch_way_0_bits[1] ? state_vec_277[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h116) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_278 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_278[1], - set_touch_ways_0_511_bits[1] - ? state_vec_278[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h117) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_278[1], + touch_way_0_bits[1] ? state_vec_278[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h117) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_279 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_279[1], - set_touch_ways_0_511_bits[1] - ? state_vec_279[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h118) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_279[1], + touch_way_0_bits[1] ? state_vec_279[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h118) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_280 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_280[1], - set_touch_ways_0_511_bits[1] - ? state_vec_280[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h119) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_280[1], + touch_way_0_bits[1] ? state_vec_280[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h119) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_281 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_281[1], - set_touch_ways_0_511_bits[1] - ? state_vec_281[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_281[1], + touch_way_0_bits[1] ? state_vec_281[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_282 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_282[1], - set_touch_ways_0_511_bits[1] - ? state_vec_282[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_282[1], + touch_way_0_bits[1] ? state_vec_282[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_283 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_283[1], - set_touch_ways_0_511_bits[1] - ? state_vec_283[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_283[1], + touch_way_0_bits[1] ? state_vec_283[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_284 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_284[1], - set_touch_ways_0_511_bits[1] - ? state_vec_284[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_284[1], + touch_way_0_bits[1] ? state_vec_284[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_285 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_285[1], - set_touch_ways_0_511_bits[1] - ? state_vec_285[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_285[1], + touch_way_0_bits[1] ? state_vec_285[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_286 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_286[1], - set_touch_ways_0_511_bits[1] - ? state_vec_286[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h11F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_286[1], + touch_way_0_bits[1] ? state_vec_286[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h11F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_287 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_287[1], - set_touch_ways_0_511_bits[1] - ? state_vec_287[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h120) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_287[1], + touch_way_0_bits[1] ? state_vec_287[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h120) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_288 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_288[1], - set_touch_ways_0_511_bits[1] - ? state_vec_288[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h121) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_288[1], + touch_way_0_bits[1] ? state_vec_288[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h121) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_289 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_289[1], - set_touch_ways_0_511_bits[1] - ? state_vec_289[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h122) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_289[1], + touch_way_0_bits[1] ? state_vec_289[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h122) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_290 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_290[1], - set_touch_ways_0_511_bits[1] - ? state_vec_290[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h123) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_290[1], + touch_way_0_bits[1] ? state_vec_290[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h123) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_291 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_291[1], - set_touch_ways_0_511_bits[1] - ? state_vec_291[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h124) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_291[1], + touch_way_0_bits[1] ? state_vec_291[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h124) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_292 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_292[1], - set_touch_ways_0_511_bits[1] - ? state_vec_292[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h125) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_292[1], + touch_way_0_bits[1] ? state_vec_292[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h125) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_293 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_293[1], - set_touch_ways_0_511_bits[1] - ? state_vec_293[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h126) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_293[1], + touch_way_0_bits[1] ? state_vec_293[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h126) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_294 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_294[1], - set_touch_ways_0_511_bits[1] - ? state_vec_294[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h127) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_294[1], + touch_way_0_bits[1] ? state_vec_294[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h127) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_295 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_295[1], - set_touch_ways_0_511_bits[1] - ? state_vec_295[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h128) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_295[1], + touch_way_0_bits[1] ? state_vec_295[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h128) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_296 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_296[1], - set_touch_ways_0_511_bits[1] - ? state_vec_296[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h129) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_296[1], + touch_way_0_bits[1] ? state_vec_296[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h129) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_297 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_297[1], - set_touch_ways_0_511_bits[1] - ? state_vec_297[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_297[1], + touch_way_0_bits[1] ? state_vec_297[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_298 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_298[1], - set_touch_ways_0_511_bits[1] - ? state_vec_298[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_298[1], + touch_way_0_bits[1] ? state_vec_298[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_299 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_299[1], - set_touch_ways_0_511_bits[1] - ? state_vec_299[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_299[1], + touch_way_0_bits[1] ? state_vec_299[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_300 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_300[1], - set_touch_ways_0_511_bits[1] - ? state_vec_300[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_300[1], + touch_way_0_bits[1] ? state_vec_300[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_301 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_301[1], - set_touch_ways_0_511_bits[1] - ? state_vec_301[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_301[1], + touch_way_0_bits[1] ? state_vec_301[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_302 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_302[1], - set_touch_ways_0_511_bits[1] - ? state_vec_302[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h12F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_302[1], + touch_way_0_bits[1] ? state_vec_302[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h12F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_303 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_303[1], - set_touch_ways_0_511_bits[1] - ? state_vec_303[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h130) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_303[1], + touch_way_0_bits[1] ? state_vec_303[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h130) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_304 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_304[1], - set_touch_ways_0_511_bits[1] - ? state_vec_304[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h131) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_304[1], + touch_way_0_bits[1] ? state_vec_304[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h131) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_305 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_305[1], - set_touch_ways_0_511_bits[1] - ? state_vec_305[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h132) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_305[1], + touch_way_0_bits[1] ? state_vec_305[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h132) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_306 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_306[1], - set_touch_ways_0_511_bits[1] - ? state_vec_306[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h133) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_306[1], + touch_way_0_bits[1] ? state_vec_306[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h133) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_307 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_307[1], - set_touch_ways_0_511_bits[1] - ? state_vec_307[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h134) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_307[1], + touch_way_0_bits[1] ? state_vec_307[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h134) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_308 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_308[1], - set_touch_ways_0_511_bits[1] - ? state_vec_308[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h135) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_308[1], + touch_way_0_bits[1] ? state_vec_308[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h135) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_309 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_309[1], - set_touch_ways_0_511_bits[1] - ? state_vec_309[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h136) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_309[1], + touch_way_0_bits[1] ? state_vec_309[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h136) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_310 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_310[1], - set_touch_ways_0_511_bits[1] - ? state_vec_310[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h137) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_310[1], + touch_way_0_bits[1] ? state_vec_310[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h137) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_311 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_311[1], - set_touch_ways_0_511_bits[1] - ? state_vec_311[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h138) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_311[1], + touch_way_0_bits[1] ? state_vec_311[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h138) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_312 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_312[1], - set_touch_ways_0_511_bits[1] - ? state_vec_312[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h139) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_312[1], + touch_way_0_bits[1] ? state_vec_312[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h139) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_313 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_313[1], - set_touch_ways_0_511_bits[1] - ? state_vec_313[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_313[1], + touch_way_0_bits[1] ? state_vec_313[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_314 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_314[1], - set_touch_ways_0_511_bits[1] - ? state_vec_314[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_314[1], + touch_way_0_bits[1] ? state_vec_314[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_315 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_315[1], - set_touch_ways_0_511_bits[1] - ? state_vec_315[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_315[1], + touch_way_0_bits[1] ? state_vec_315[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_316 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_316[1], - set_touch_ways_0_511_bits[1] - ? state_vec_316[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_316[1], + touch_way_0_bits[1] ? state_vec_316[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_317 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_317[1], - set_touch_ways_0_511_bits[1] - ? state_vec_317[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_317[1], + touch_way_0_bits[1] ? state_vec_317[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_318 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_318[1], - set_touch_ways_0_511_bits[1] - ? state_vec_318[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h13F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_318[1], + touch_way_0_bits[1] ? state_vec_318[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h13F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_319 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_319[1], - set_touch_ways_0_511_bits[1] - ? state_vec_319[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h140) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_319[1], + touch_way_0_bits[1] ? state_vec_319[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h140) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_320 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_320[1], - set_touch_ways_0_511_bits[1] - ? state_vec_320[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h141) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_320[1], + touch_way_0_bits[1] ? state_vec_320[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h141) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_321 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_321[1], - set_touch_ways_0_511_bits[1] - ? state_vec_321[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h142) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_321[1], + touch_way_0_bits[1] ? state_vec_321[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h142) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_322 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_322[1], - set_touch_ways_0_511_bits[1] - ? state_vec_322[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h143) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_322[1], + touch_way_0_bits[1] ? state_vec_322[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h143) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_323 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_323[1], - set_touch_ways_0_511_bits[1] - ? state_vec_323[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h144) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_323[1], + touch_way_0_bits[1] ? state_vec_323[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h144) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_324 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_324[1], - set_touch_ways_0_511_bits[1] - ? state_vec_324[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h145) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_324[1], + touch_way_0_bits[1] ? state_vec_324[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h145) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_325 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_325[1], - set_touch_ways_0_511_bits[1] - ? state_vec_325[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h146) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_325[1], + touch_way_0_bits[1] ? state_vec_325[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h146) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_326 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_326[1], - set_touch_ways_0_511_bits[1] - ? state_vec_326[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h147) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_326[1], + touch_way_0_bits[1] ? state_vec_326[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h147) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_327 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_327[1], - set_touch_ways_0_511_bits[1] - ? state_vec_327[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h148) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_327[1], + touch_way_0_bits[1] ? state_vec_327[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h148) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_328 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_328[1], - set_touch_ways_0_511_bits[1] - ? state_vec_328[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h149) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_328[1], + touch_way_0_bits[1] ? state_vec_328[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h149) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_329 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_329[1], - set_touch_ways_0_511_bits[1] - ? state_vec_329[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_329[1], + touch_way_0_bits[1] ? state_vec_329[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_330 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_330[1], - set_touch_ways_0_511_bits[1] - ? state_vec_330[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_330[1], + touch_way_0_bits[1] ? state_vec_330[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_331 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_331[1], - set_touch_ways_0_511_bits[1] - ? state_vec_331[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_331[1], + touch_way_0_bits[1] ? state_vec_331[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_332 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_332[1], - set_touch_ways_0_511_bits[1] - ? state_vec_332[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_332[1], + touch_way_0_bits[1] ? state_vec_332[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_333 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_333[1], - set_touch_ways_0_511_bits[1] - ? state_vec_333[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_333[1], + touch_way_0_bits[1] ? state_vec_333[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_334 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_334[1], - set_touch_ways_0_511_bits[1] - ? state_vec_334[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h14F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_334[1], + touch_way_0_bits[1] ? state_vec_334[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h14F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_335 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_335[1], - set_touch_ways_0_511_bits[1] - ? state_vec_335[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h150) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_335[1], + touch_way_0_bits[1] ? state_vec_335[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h150) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_336 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_336[1], - set_touch_ways_0_511_bits[1] - ? state_vec_336[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h151) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_336[1], + touch_way_0_bits[1] ? state_vec_336[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h151) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_337 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_337[1], - set_touch_ways_0_511_bits[1] - ? state_vec_337[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h152) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_337[1], + touch_way_0_bits[1] ? state_vec_337[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h152) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_338 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_338[1], - set_touch_ways_0_511_bits[1] - ? state_vec_338[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h153) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_338[1], + touch_way_0_bits[1] ? state_vec_338[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h153) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_339 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_339[1], - set_touch_ways_0_511_bits[1] - ? state_vec_339[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h154) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_339[1], + touch_way_0_bits[1] ? state_vec_339[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h154) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_340 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_340[1], - set_touch_ways_0_511_bits[1] - ? state_vec_340[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h155) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_340[1], + touch_way_0_bits[1] ? state_vec_340[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h155) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_341 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_341[1], - set_touch_ways_0_511_bits[1] - ? state_vec_341[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h156) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_341[1], + touch_way_0_bits[1] ? state_vec_341[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h156) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_342 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_342[1], - set_touch_ways_0_511_bits[1] - ? state_vec_342[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h157) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_342[1], + touch_way_0_bits[1] ? state_vec_342[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h157) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_343 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_343[1], - set_touch_ways_0_511_bits[1] - ? state_vec_343[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h158) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_343[1], + touch_way_0_bits[1] ? state_vec_343[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h158) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_344 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_344[1], - set_touch_ways_0_511_bits[1] - ? state_vec_344[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h159) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_344[1], + touch_way_0_bits[1] ? state_vec_344[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h159) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_345 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_345[1], - set_touch_ways_0_511_bits[1] - ? state_vec_345[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_345[1], + touch_way_0_bits[1] ? state_vec_345[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_346 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_346[1], - set_touch_ways_0_511_bits[1] - ? state_vec_346[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_346[1], + touch_way_0_bits[1] ? state_vec_346[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_347 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_347[1], - set_touch_ways_0_511_bits[1] - ? state_vec_347[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_347[1], + touch_way_0_bits[1] ? state_vec_347[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_348 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_348[1], - set_touch_ways_0_511_bits[1] - ? state_vec_348[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_348[1], + touch_way_0_bits[1] ? state_vec_348[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_349 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_349[1], - set_touch_ways_0_511_bits[1] - ? state_vec_349[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_349[1], + touch_way_0_bits[1] ? state_vec_349[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_350 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_350[1], - set_touch_ways_0_511_bits[1] - ? state_vec_350[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h15F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_350[1], + touch_way_0_bits[1] ? state_vec_350[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h15F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_351 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_351[1], - set_touch_ways_0_511_bits[1] - ? state_vec_351[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h160) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_351[1], + touch_way_0_bits[1] ? state_vec_351[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h160) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_352 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_352[1], - set_touch_ways_0_511_bits[1] - ? state_vec_352[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h161) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_352[1], + touch_way_0_bits[1] ? state_vec_352[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h161) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_353 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_353[1], - set_touch_ways_0_511_bits[1] - ? state_vec_353[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h162) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_353[1], + touch_way_0_bits[1] ? state_vec_353[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h162) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_354 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_354[1], - set_touch_ways_0_511_bits[1] - ? state_vec_354[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h163) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_354[1], + touch_way_0_bits[1] ? state_vec_354[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h163) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_355 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_355[1], - set_touch_ways_0_511_bits[1] - ? state_vec_355[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h164) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_355[1], + touch_way_0_bits[1] ? state_vec_355[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h164) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_356 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_356[1], - set_touch_ways_0_511_bits[1] - ? state_vec_356[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h165) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_356[1], + touch_way_0_bits[1] ? state_vec_356[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h165) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_357 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_357[1], - set_touch_ways_0_511_bits[1] - ? state_vec_357[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h166) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_357[1], + touch_way_0_bits[1] ? state_vec_357[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h166) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_358 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_358[1], - set_touch_ways_0_511_bits[1] - ? state_vec_358[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h167) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_358[1], + touch_way_0_bits[1] ? state_vec_358[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h167) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_359 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_359[1], - set_touch_ways_0_511_bits[1] - ? state_vec_359[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h168) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_359[1], + touch_way_0_bits[1] ? state_vec_359[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h168) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_360 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_360[1], - set_touch_ways_0_511_bits[1] - ? state_vec_360[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h169) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_360[1], + touch_way_0_bits[1] ? state_vec_360[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h169) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_361 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_361[1], - set_touch_ways_0_511_bits[1] - ? state_vec_361[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_361[1], + touch_way_0_bits[1] ? state_vec_361[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_362 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_362[1], - set_touch_ways_0_511_bits[1] - ? state_vec_362[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_362[1], + touch_way_0_bits[1] ? state_vec_362[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_363 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_363[1], - set_touch_ways_0_511_bits[1] - ? state_vec_363[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_363[1], + touch_way_0_bits[1] ? state_vec_363[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_364 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_364[1], - set_touch_ways_0_511_bits[1] - ? state_vec_364[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_364[1], + touch_way_0_bits[1] ? state_vec_364[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_365 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_365[1], - set_touch_ways_0_511_bits[1] - ? state_vec_365[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_365[1], + touch_way_0_bits[1] ? state_vec_365[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_366 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_366[1], - set_touch_ways_0_511_bits[1] - ? state_vec_366[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h16F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_366[1], + touch_way_0_bits[1] ? state_vec_366[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h16F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_367 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_367[1], - set_touch_ways_0_511_bits[1] - ? state_vec_367[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h170) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_367[1], + touch_way_0_bits[1] ? state_vec_367[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h170) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_368 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_368[1], - set_touch_ways_0_511_bits[1] - ? state_vec_368[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h171) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_368[1], + touch_way_0_bits[1] ? state_vec_368[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h171) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_369 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_369[1], - set_touch_ways_0_511_bits[1] - ? state_vec_369[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h172) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_369[1], + touch_way_0_bits[1] ? state_vec_369[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h172) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_370 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_370[1], - set_touch_ways_0_511_bits[1] - ? state_vec_370[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h173) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_370[1], + touch_way_0_bits[1] ? state_vec_370[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h173) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_371 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_371[1], - set_touch_ways_0_511_bits[1] - ? state_vec_371[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h174) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_371[1], + touch_way_0_bits[1] ? state_vec_371[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h174) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_372 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_372[1], - set_touch_ways_0_511_bits[1] - ? state_vec_372[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h175) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_372[1], + touch_way_0_bits[1] ? state_vec_372[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h175) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_373 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_373[1], - set_touch_ways_0_511_bits[1] - ? state_vec_373[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h176) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_373[1], + touch_way_0_bits[1] ? state_vec_373[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h176) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_374 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_374[1], - set_touch_ways_0_511_bits[1] - ? state_vec_374[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h177) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_374[1], + touch_way_0_bits[1] ? state_vec_374[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h177) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_375 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_375[1], - set_touch_ways_0_511_bits[1] - ? state_vec_375[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h178) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_375[1], + touch_way_0_bits[1] ? state_vec_375[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h178) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_376 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_376[1], - set_touch_ways_0_511_bits[1] - ? state_vec_376[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h179) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_376[1], + touch_way_0_bits[1] ? state_vec_376[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h179) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_377 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_377[1], - set_touch_ways_0_511_bits[1] - ? state_vec_377[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_377[1], + touch_way_0_bits[1] ? state_vec_377[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_378 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_378[1], - set_touch_ways_0_511_bits[1] - ? state_vec_378[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_378[1], + touch_way_0_bits[1] ? state_vec_378[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_379 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_379[1], - set_touch_ways_0_511_bits[1] - ? state_vec_379[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_379[1], + touch_way_0_bits[1] ? state_vec_379[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_380 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_380[1], - set_touch_ways_0_511_bits[1] - ? state_vec_380[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_380[1], + touch_way_0_bits[1] ? state_vec_380[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_381 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_381[1], - set_touch_ways_0_511_bits[1] - ? state_vec_381[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_381[1], + touch_way_0_bits[1] ? state_vec_381[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_382 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_382[1], - set_touch_ways_0_511_bits[1] - ? state_vec_382[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h17F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_382[1], + touch_way_0_bits[1] ? state_vec_382[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h17F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_383 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_383[1], - set_touch_ways_0_511_bits[1] - ? state_vec_383[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h180) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_383[1], + touch_way_0_bits[1] ? state_vec_383[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h180) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_384 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_384[1], - set_touch_ways_0_511_bits[1] - ? state_vec_384[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h181) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_384[1], + touch_way_0_bits[1] ? state_vec_384[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h181) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_385 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_385[1], - set_touch_ways_0_511_bits[1] - ? state_vec_385[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h182) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_385[1], + touch_way_0_bits[1] ? state_vec_385[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h182) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_386 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_386[1], - set_touch_ways_0_511_bits[1] - ? state_vec_386[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h183) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_386[1], + touch_way_0_bits[1] ? state_vec_386[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h183) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_387 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_387[1], - set_touch_ways_0_511_bits[1] - ? state_vec_387[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h184) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_387[1], + touch_way_0_bits[1] ? state_vec_387[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h184) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_388 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_388[1], - set_touch_ways_0_511_bits[1] - ? state_vec_388[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h185) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_388[1], + touch_way_0_bits[1] ? state_vec_388[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h185) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_389 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_389[1], - set_touch_ways_0_511_bits[1] - ? state_vec_389[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h186) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_389[1], + touch_way_0_bits[1] ? state_vec_389[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h186) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_390 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_390[1], - set_touch_ways_0_511_bits[1] - ? state_vec_390[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h187) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_390[1], + touch_way_0_bits[1] ? state_vec_390[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h187) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_391 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_391[1], - set_touch_ways_0_511_bits[1] - ? state_vec_391[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h188) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_391[1], + touch_way_0_bits[1] ? state_vec_391[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h188) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_392 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_392[1], - set_touch_ways_0_511_bits[1] - ? state_vec_392[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h189) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_392[1], + touch_way_0_bits[1] ? state_vec_392[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h189) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_393 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_393[1], - set_touch_ways_0_511_bits[1] - ? state_vec_393[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_393[1], + touch_way_0_bits[1] ? state_vec_393[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_394 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_394[1], - set_touch_ways_0_511_bits[1] - ? state_vec_394[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_394[1], + touch_way_0_bits[1] ? state_vec_394[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_395 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_395[1], - set_touch_ways_0_511_bits[1] - ? state_vec_395[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_395[1], + touch_way_0_bits[1] ? state_vec_395[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_396 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_396[1], - set_touch_ways_0_511_bits[1] - ? state_vec_396[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_396[1], + touch_way_0_bits[1] ? state_vec_396[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_397 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_397[1], - set_touch_ways_0_511_bits[1] - ? state_vec_397[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_397[1], + touch_way_0_bits[1] ? state_vec_397[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_398 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_398[1], - set_touch_ways_0_511_bits[1] - ? state_vec_398[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h18F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_398[1], + touch_way_0_bits[1] ? state_vec_398[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h18F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_399 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_399[1], - set_touch_ways_0_511_bits[1] - ? state_vec_399[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h190) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_399[1], + touch_way_0_bits[1] ? state_vec_399[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h190) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_400 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_400[1], - set_touch_ways_0_511_bits[1] - ? state_vec_400[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h191) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_400[1], + touch_way_0_bits[1] ? state_vec_400[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h191) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_401 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_401[1], - set_touch_ways_0_511_bits[1] - ? state_vec_401[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h192) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_401[1], + touch_way_0_bits[1] ? state_vec_401[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h192) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_402 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_402[1], - set_touch_ways_0_511_bits[1] - ? state_vec_402[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h193) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_402[1], + touch_way_0_bits[1] ? state_vec_402[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h193) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_403 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_403[1], - set_touch_ways_0_511_bits[1] - ? state_vec_403[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h194) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_403[1], + touch_way_0_bits[1] ? state_vec_403[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h194) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_404 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_404[1], - set_touch_ways_0_511_bits[1] - ? state_vec_404[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h195) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_404[1], + touch_way_0_bits[1] ? state_vec_404[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h195) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_405 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_405[1], - set_touch_ways_0_511_bits[1] - ? state_vec_405[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h196) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_405[1], + touch_way_0_bits[1] ? state_vec_405[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h196) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_406 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_406[1], - set_touch_ways_0_511_bits[1] - ? state_vec_406[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h197) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_406[1], + touch_way_0_bits[1] ? state_vec_406[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h197) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_407 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_407[1], - set_touch_ways_0_511_bits[1] - ? state_vec_407[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h198) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_407[1], + touch_way_0_bits[1] ? state_vec_407[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h198) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_408 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_408[1], - set_touch_ways_0_511_bits[1] - ? state_vec_408[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h199) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_408[1], + touch_way_0_bits[1] ? state_vec_408[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h199) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_409 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_409[1], - set_touch_ways_0_511_bits[1] - ? state_vec_409[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_409[1], + touch_way_0_bits[1] ? state_vec_409[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19A) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_410 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_410[1], - set_touch_ways_0_511_bits[1] - ? state_vec_410[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_410[1], + touch_way_0_bits[1] ? state_vec_410[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19B) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_411 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_411[1], - set_touch_ways_0_511_bits[1] - ? state_vec_411[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_411[1], + touch_way_0_bits[1] ? state_vec_411[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19C) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_412 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_412[1], - set_touch_ways_0_511_bits[1] - ? state_vec_412[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_412[1], + touch_way_0_bits[1] ? state_vec_412[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19D) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_413 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_413[1], - set_touch_ways_0_511_bits[1] - ? state_vec_413[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_413[1], + touch_way_0_bits[1] ? state_vec_413[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19E) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_414 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_414[1], - set_touch_ways_0_511_bits[1] - ? state_vec_414[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h19F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_414[1], + touch_way_0_bits[1] ? state_vec_414[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h19F) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_415 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_415[1], - set_touch_ways_0_511_bits[1] - ? state_vec_415[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_415[1], + touch_way_0_bits[1] ? state_vec_415[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_416 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_416[1], - set_touch_ways_0_511_bits[1] - ? state_vec_416[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_416[1], + touch_way_0_bits[1] ? state_vec_416[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_417 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_417[1], - set_touch_ways_0_511_bits[1] - ? state_vec_417[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_417[1], + touch_way_0_bits[1] ? state_vec_417[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_418 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_418[1], - set_touch_ways_0_511_bits[1] - ? state_vec_418[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_418[1], + touch_way_0_bits[1] ? state_vec_418[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_419 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_419[1], - set_touch_ways_0_511_bits[1] - ? state_vec_419[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_419[1], + touch_way_0_bits[1] ? state_vec_419[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_420 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_420[1], - set_touch_ways_0_511_bits[1] - ? state_vec_420[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_420[1], + touch_way_0_bits[1] ? state_vec_420[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_421 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_421[1], - set_touch_ways_0_511_bits[1] - ? state_vec_421[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_421[1], + touch_way_0_bits[1] ? state_vec_421[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_422 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_422[1], - set_touch_ways_0_511_bits[1] - ? state_vec_422[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_422[1], + touch_way_0_bits[1] ? state_vec_422[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_423 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_423[1], - set_touch_ways_0_511_bits[1] - ? state_vec_423[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_423[1], + touch_way_0_bits[1] ? state_vec_423[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_424 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_424[1], - set_touch_ways_0_511_bits[1] - ? state_vec_424[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1A9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_424[1], + touch_way_0_bits[1] ? state_vec_424[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1A9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_425 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_425[1], - set_touch_ways_0_511_bits[1] - ? state_vec_425[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_425[1], + touch_way_0_bits[1] ? state_vec_425[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_426 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_426[1], - set_touch_ways_0_511_bits[1] - ? state_vec_426[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_426[1], + touch_way_0_bits[1] ? state_vec_426[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_427 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_427[1], - set_touch_ways_0_511_bits[1] - ? state_vec_427[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_427[1], + touch_way_0_bits[1] ? state_vec_427[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_428 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_428[1], - set_touch_ways_0_511_bits[1] - ? state_vec_428[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_428[1], + touch_way_0_bits[1] ? state_vec_428[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_429 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_429[1], - set_touch_ways_0_511_bits[1] - ? state_vec_429[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_429[1], + touch_way_0_bits[1] ? state_vec_429[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_430 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_430[1], - set_touch_ways_0_511_bits[1] - ? state_vec_430[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1AF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_430[1], + touch_way_0_bits[1] ? state_vec_430[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1AF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_431 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_431[1], - set_touch_ways_0_511_bits[1] - ? state_vec_431[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_431[1], + touch_way_0_bits[1] ? state_vec_431[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_432 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_432[1], - set_touch_ways_0_511_bits[1] - ? state_vec_432[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_432[1], + touch_way_0_bits[1] ? state_vec_432[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_433 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_433[1], - set_touch_ways_0_511_bits[1] - ? state_vec_433[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_433[1], + touch_way_0_bits[1] ? state_vec_433[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_434 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_434[1], - set_touch_ways_0_511_bits[1] - ? state_vec_434[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_434[1], + touch_way_0_bits[1] ? state_vec_434[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_435 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_435[1], - set_touch_ways_0_511_bits[1] - ? state_vec_435[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_435[1], + touch_way_0_bits[1] ? state_vec_435[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_436 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_436[1], - set_touch_ways_0_511_bits[1] - ? state_vec_436[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_436[1], + touch_way_0_bits[1] ? state_vec_436[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_437 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_437[1], - set_touch_ways_0_511_bits[1] - ? state_vec_437[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_437[1], + touch_way_0_bits[1] ? state_vec_437[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_438 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_438[1], - set_touch_ways_0_511_bits[1] - ? state_vec_438[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_438[1], + touch_way_0_bits[1] ? state_vec_438[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_439 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_439[1], - set_touch_ways_0_511_bits[1] - ? state_vec_439[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_439[1], + touch_way_0_bits[1] ? state_vec_439[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_440 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_440[1], - set_touch_ways_0_511_bits[1] - ? state_vec_440[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1B9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_440[1], + touch_way_0_bits[1] ? state_vec_440[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1B9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_441 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_441[1], - set_touch_ways_0_511_bits[1] - ? state_vec_441[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_441[1], + touch_way_0_bits[1] ? state_vec_441[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_442 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_442[1], - set_touch_ways_0_511_bits[1] - ? state_vec_442[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_442[1], + touch_way_0_bits[1] ? state_vec_442[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_443 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_443[1], - set_touch_ways_0_511_bits[1] - ? state_vec_443[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_443[1], + touch_way_0_bits[1] ? state_vec_443[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_444 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_444[1], - set_touch_ways_0_511_bits[1] - ? state_vec_444[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_444[1], + touch_way_0_bits[1] ? state_vec_444[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_445 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_445[1], - set_touch_ways_0_511_bits[1] - ? state_vec_445[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_445[1], + touch_way_0_bits[1] ? state_vec_445[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_446 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_446[1], - set_touch_ways_0_511_bits[1] - ? state_vec_446[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1BF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_446[1], + touch_way_0_bits[1] ? state_vec_446[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1BF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_447 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_447[1], - set_touch_ways_0_511_bits[1] - ? state_vec_447[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_447[1], + touch_way_0_bits[1] ? state_vec_447[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_448 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_448[1], - set_touch_ways_0_511_bits[1] - ? state_vec_448[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_448[1], + touch_way_0_bits[1] ? state_vec_448[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_449 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_449[1], - set_touch_ways_0_511_bits[1] - ? state_vec_449[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_449[1], + touch_way_0_bits[1] ? state_vec_449[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_450 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_450[1], - set_touch_ways_0_511_bits[1] - ? state_vec_450[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_450[1], + touch_way_0_bits[1] ? state_vec_450[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_451 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_451[1], - set_touch_ways_0_511_bits[1] - ? state_vec_451[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_451[1], + touch_way_0_bits[1] ? state_vec_451[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_452 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_452[1], - set_touch_ways_0_511_bits[1] - ? state_vec_452[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_452[1], + touch_way_0_bits[1] ? state_vec_452[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_453 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_453[1], - set_touch_ways_0_511_bits[1] - ? state_vec_453[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_453[1], + touch_way_0_bits[1] ? state_vec_453[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_454 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_454[1], - set_touch_ways_0_511_bits[1] - ? state_vec_454[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_454[1], + touch_way_0_bits[1] ? state_vec_454[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_455 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_455[1], - set_touch_ways_0_511_bits[1] - ? state_vec_455[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_455[1], + touch_way_0_bits[1] ? state_vec_455[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_456 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_456[1], - set_touch_ways_0_511_bits[1] - ? state_vec_456[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1C9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_456[1], + touch_way_0_bits[1] ? state_vec_456[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1C9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_457 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_457[1], - set_touch_ways_0_511_bits[1] - ? state_vec_457[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_457[1], + touch_way_0_bits[1] ? state_vec_457[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_458 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_458[1], - set_touch_ways_0_511_bits[1] - ? state_vec_458[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_458[1], + touch_way_0_bits[1] ? state_vec_458[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_459 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_459[1], - set_touch_ways_0_511_bits[1] - ? state_vec_459[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_459[1], + touch_way_0_bits[1] ? state_vec_459[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_460 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_460[1], - set_touch_ways_0_511_bits[1] - ? state_vec_460[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_460[1], + touch_way_0_bits[1] ? state_vec_460[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_461 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_461[1], - set_touch_ways_0_511_bits[1] - ? state_vec_461[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_461[1], + touch_way_0_bits[1] ? state_vec_461[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_462 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_462[1], - set_touch_ways_0_511_bits[1] - ? state_vec_462[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1CF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_462[1], + touch_way_0_bits[1] ? state_vec_462[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1CF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_463 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_463[1], - set_touch_ways_0_511_bits[1] - ? state_vec_463[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_463[1], + touch_way_0_bits[1] ? state_vec_463[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_464 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_464[1], - set_touch_ways_0_511_bits[1] - ? state_vec_464[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_464[1], + touch_way_0_bits[1] ? state_vec_464[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_465 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_465[1], - set_touch_ways_0_511_bits[1] - ? state_vec_465[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_465[1], + touch_way_0_bits[1] ? state_vec_465[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_466 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_466[1], - set_touch_ways_0_511_bits[1] - ? state_vec_466[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_466[1], + touch_way_0_bits[1] ? state_vec_466[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_467 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_467[1], - set_touch_ways_0_511_bits[1] - ? state_vec_467[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_467[1], + touch_way_0_bits[1] ? state_vec_467[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_468 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_468[1], - set_touch_ways_0_511_bits[1] - ? state_vec_468[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_468[1], + touch_way_0_bits[1] ? state_vec_468[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_469 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_469[1], - set_touch_ways_0_511_bits[1] - ? state_vec_469[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_469[1], + touch_way_0_bits[1] ? state_vec_469[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_470 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_470[1], - set_touch_ways_0_511_bits[1] - ? state_vec_470[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_470[1], + touch_way_0_bits[1] ? state_vec_470[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_471 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_471[1], - set_touch_ways_0_511_bits[1] - ? state_vec_471[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_471[1], + touch_way_0_bits[1] ? state_vec_471[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_472 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_472[1], - set_touch_ways_0_511_bits[1] - ? state_vec_472[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1D9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_472[1], + touch_way_0_bits[1] ? state_vec_472[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1D9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_473 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_473[1], - set_touch_ways_0_511_bits[1] - ? state_vec_473[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_473[1], + touch_way_0_bits[1] ? state_vec_473[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_474 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_474[1], - set_touch_ways_0_511_bits[1] - ? state_vec_474[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_474[1], + touch_way_0_bits[1] ? state_vec_474[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_475 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_475[1], - set_touch_ways_0_511_bits[1] - ? state_vec_475[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_475[1], + touch_way_0_bits[1] ? state_vec_475[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_476 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_476[1], - set_touch_ways_0_511_bits[1] - ? state_vec_476[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_476[1], + touch_way_0_bits[1] ? state_vec_476[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_477 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_477[1], - set_touch_ways_0_511_bits[1] - ? state_vec_477[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_477[1], + touch_way_0_bits[1] ? state_vec_477[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_478 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_478[1], - set_touch_ways_0_511_bits[1] - ? state_vec_478[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1DF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_478[1], + touch_way_0_bits[1] ? state_vec_478[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1DF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_479 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_479[1], - set_touch_ways_0_511_bits[1] - ? state_vec_479[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_479[1], + touch_way_0_bits[1] ? state_vec_479[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_480 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_480[1], - set_touch_ways_0_511_bits[1] - ? state_vec_480[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_480[1], + touch_way_0_bits[1] ? state_vec_480[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_481 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_481[1], - set_touch_ways_0_511_bits[1] - ? state_vec_481[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_481[1], + touch_way_0_bits[1] ? state_vec_481[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_482 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_482[1], - set_touch_ways_0_511_bits[1] - ? state_vec_482[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_482[1], + touch_way_0_bits[1] ? state_vec_482[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_483 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_483[1], - set_touch_ways_0_511_bits[1] - ? state_vec_483[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_483[1], + touch_way_0_bits[1] ? state_vec_483[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_484 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_484[1], - set_touch_ways_0_511_bits[1] - ? state_vec_484[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_484[1], + touch_way_0_bits[1] ? state_vec_484[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_485 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_485[1], - set_touch_ways_0_511_bits[1] - ? state_vec_485[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_485[1], + touch_way_0_bits[1] ? state_vec_485[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_486 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_486[1], - set_touch_ways_0_511_bits[1] - ? state_vec_486[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_486[1], + touch_way_0_bits[1] ? state_vec_486[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_487 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_487[1], - set_touch_ways_0_511_bits[1] - ? state_vec_487[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_487[1], + touch_way_0_bits[1] ? state_vec_487[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_488 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_488[1], - set_touch_ways_0_511_bits[1] - ? state_vec_488[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1E9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_488[1], + touch_way_0_bits[1] ? state_vec_488[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1E9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_489 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_489[1], - set_touch_ways_0_511_bits[1] - ? state_vec_489[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1EA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_489[1], + touch_way_0_bits[1] ? state_vec_489[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1EA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_490 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_490[1], - set_touch_ways_0_511_bits[1] - ? state_vec_490[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1EB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_490[1], + touch_way_0_bits[1] ? state_vec_490[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1EB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_491 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_491[1], - set_touch_ways_0_511_bits[1] - ? state_vec_491[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1EC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_491[1], + touch_way_0_bits[1] ? state_vec_491[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1EC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_492 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_492[1], - set_touch_ways_0_511_bits[1] - ? state_vec_492[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1ED) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_492[1], + touch_way_0_bits[1] ? state_vec_492[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1ED) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_493 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_493[1], - set_touch_ways_0_511_bits[1] - ? state_vec_493[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1EE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_493[1], + touch_way_0_bits[1] ? state_vec_493[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1EE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_494 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_494[1], - set_touch_ways_0_511_bits[1] - ? state_vec_494[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1EF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_494[1], + touch_way_0_bits[1] ? state_vec_494[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1EF) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_495 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_495[1], - set_touch_ways_0_511_bits[1] - ? state_vec_495[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_495[1], + touch_way_0_bits[1] ? state_vec_495[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F0) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_496 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_496[1], - set_touch_ways_0_511_bits[1] - ? state_vec_496[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_496[1], + touch_way_0_bits[1] ? state_vec_496[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F1) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_497 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_497[1], - set_touch_ways_0_511_bits[1] - ? state_vec_497[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_497[1], + touch_way_0_bits[1] ? state_vec_497[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F2) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_498 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_498[1], - set_touch_ways_0_511_bits[1] - ? state_vec_498[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_498[1], + touch_way_0_bits[1] ? state_vec_498[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F3) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_499 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_499[1], - set_touch_ways_0_511_bits[1] - ? state_vec_499[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_499[1], + touch_way_0_bits[1] ? state_vec_499[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F4) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_500 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_500[1], - set_touch_ways_0_511_bits[1] - ? state_vec_500[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_500[1], + touch_way_0_bits[1] ? state_vec_500[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F5) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_501 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_501[1], - set_touch_ways_0_511_bits[1] - ? state_vec_501[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_501[1], + touch_way_0_bits[1] ? state_vec_501[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F6) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_502 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_502[1], - set_touch_ways_0_511_bits[1] - ? state_vec_502[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_502[1], + touch_way_0_bits[1] ? state_vec_502[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F7) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_503 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_503[1], - set_touch_ways_0_511_bits[1] - ? state_vec_503[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_503[1], + touch_way_0_bits[1] ? state_vec_503[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F8) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_504 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_504[1], - set_touch_ways_0_511_bits[1] - ? state_vec_504[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1F9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_504[1], + touch_way_0_bits[1] ? state_vec_504[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1F9) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_505 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_505[1], - set_touch_ways_0_511_bits[1] - ? state_vec_505[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1FA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_505[1], + touch_way_0_bits[1] ? state_vec_505[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1FA) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_506 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_506[1], - set_touch_ways_0_511_bits[1] - ? state_vec_506[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1FB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_506[1], + touch_way_0_bits[1] ? state_vec_506[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1FB) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_507 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_507[1], - set_touch_ways_0_511_bits[1] - ? state_vec_507[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1FC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_507[1], + touch_way_0_bits[1] ? state_vec_507[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1FC) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_508 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_508[1], - set_touch_ways_0_511_bits[1] - ? state_vec_508[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1FD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_508[1], + touch_way_0_bits[1] ? state_vec_508[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1FD) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_509 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_509[1], - set_touch_ways_0_511_bits[1] - ? state_vec_509[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & touch_set_0 == 9'h1FE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_509[1], + touch_way_0_bits[1] ? state_vec_509[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & touch_set_0 == 9'h1FE) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_510 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_510[1], - set_touch_ways_0_511_bits[1] - ? state_vec_510[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 - if (touch_way_0_valid & (&touch_set_0)) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_510[1], + touch_way_0_bits[1] ? state_vec_510[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] + if (touch_way_0_valid & (&touch_set_0)) // @[rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43] state_vec_511 <= - {~(set_touch_ways_0_511_bits[1]), - set_touch_ways_0_511_bits[1] - ? ~(set_touch_ways_0_511_bits[0]) - : state_vec_511[1], - set_touch_ways_0_511_bits[1] - ? state_vec_511[0] - : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_511[1], + touch_way_0_bits[1] ? state_vec_511[0] : ~(touch_way_0_bits[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:60]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - initial begin // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + logic [31:0] _RANDOM[0:60]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + initial begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] for (logic [5:0] i = 6'h0; i < 6'h3D; i += 6'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - end // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - pred_rdata_REG = _RANDOM[6'h0][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62 - pred_rdata_hold_data_0_entry_valid = _RANDOM[6'h0][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_brSlots_0_offset = _RANDOM[6'h0][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_brSlots_0_lower = _RANDOM[6'h0][17:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_brSlots_0_tarStat = _RANDOM[6'h0][19:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_brSlots_0_sharing = _RANDOM[6'h0][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_brSlots_0_valid = _RANDOM[6'h0][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_tailSlot_offset = _RANDOM[6'h0][25:22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + end // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + pred_rdata_REG = _RANDOM[6'h0][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62] + pred_rdata_hold_data_0_entry_valid = _RANDOM[6'h0][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_brSlots_0_offset = _RANDOM[6'h0][5:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_brSlots_0_lower = _RANDOM[6'h0][17:6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_brSlots_0_tarStat = _RANDOM[6'h0][19:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_brSlots_0_sharing = _RANDOM[6'h0][20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_brSlots_0_valid = _RANDOM[6'h0][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_tailSlot_offset = _RANDOM[6'h0][25:22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_0_entry_tailSlot_lower = - {_RANDOM[6'h0][31:26], _RANDOM[6'h1][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_tailSlot_tarStat = _RANDOM[6'h1][15:14]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_tailSlot_sharing = _RANDOM[6'h1][16]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_tailSlot_valid = _RANDOM[6'h1][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_pftAddr = _RANDOM[6'h1][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_carry = _RANDOM[6'h1][22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isCall = _RANDOM[6'h1][23]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isRet = _RANDOM[6'h1][24]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_isJalr = _RANDOM[6'h1][25]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_last_may_be_rvi_call = _RANDOM[6'h1][26]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_always_taken_0 = _RANDOM[6'h1][27]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_entry_always_taken_1 = _RANDOM[6'h1][28]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_0_tag = {_RANDOM[6'h1][31:29], _RANDOM[6'h2][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_valid = _RANDOM[6'h2][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_brSlots_0_offset = _RANDOM[6'h2][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + {_RANDOM[6'h0][31:26], _RANDOM[6'h1][13:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_tailSlot_tarStat = _RANDOM[6'h1][15:14]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_tailSlot_sharing = _RANDOM[6'h1][16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_tailSlot_valid = _RANDOM[6'h1][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_pftAddr = _RANDOM[6'h1][21:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_carry = _RANDOM[6'h1][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isCall = _RANDOM[6'h1][23]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isRet = _RANDOM[6'h1][24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_isJalr = _RANDOM[6'h1][25]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_last_may_be_rvi_call = _RANDOM[6'h1][26]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_always_taken_0 = _RANDOM[6'h1][27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_entry_always_taken_1 = _RANDOM[6'h1][28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_0_tag = {_RANDOM[6'h1][31:29], _RANDOM[6'h2][16:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_valid = _RANDOM[6'h2][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_brSlots_0_offset = _RANDOM[6'h2][21:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_1_entry_brSlots_0_lower = - {_RANDOM[6'h2][31:22], _RANDOM[6'h3][1:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_brSlots_0_tarStat = _RANDOM[6'h3][3:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_brSlots_0_sharing = _RANDOM[6'h3][4]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_brSlots_0_valid = _RANDOM[6'h3][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_tailSlot_offset = _RANDOM[6'h3][9:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_tailSlot_lower = _RANDOM[6'h3][29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_tailSlot_tarStat = _RANDOM[6'h3][31:30]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_tailSlot_sharing = _RANDOM[6'h4][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_tailSlot_valid = _RANDOM[6'h4][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_pftAddr = _RANDOM[6'h4][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_carry = _RANDOM[6'h4][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isCall = _RANDOM[6'h4][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isRet = _RANDOM[6'h4][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_isJalr = _RANDOM[6'h4][9]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_last_may_be_rvi_call = _RANDOM[6'h4][10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_always_taken_0 = _RANDOM[6'h4][11]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_entry_always_taken_1 = _RANDOM[6'h4][12]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_1_tag = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_valid = _RANDOM[6'h5][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_brSlots_0_offset = _RANDOM[6'h5][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_brSlots_0_lower = _RANDOM[6'h5][17:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_brSlots_0_tarStat = _RANDOM[6'h5][19:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_brSlots_0_sharing = _RANDOM[6'h5][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_brSlots_0_valid = _RANDOM[6'h5][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_tailSlot_offset = _RANDOM[6'h5][25:22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + {_RANDOM[6'h2][31:22], _RANDOM[6'h3][1:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_brSlots_0_tarStat = _RANDOM[6'h3][3:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_brSlots_0_sharing = _RANDOM[6'h3][4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_brSlots_0_valid = _RANDOM[6'h3][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_tailSlot_offset = _RANDOM[6'h3][9:6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_tailSlot_lower = _RANDOM[6'h3][29:10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_tailSlot_tarStat = _RANDOM[6'h3][31:30]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_tailSlot_sharing = _RANDOM[6'h4][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_tailSlot_valid = _RANDOM[6'h4][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_pftAddr = _RANDOM[6'h4][5:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_carry = _RANDOM[6'h4][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isCall = _RANDOM[6'h4][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isRet = _RANDOM[6'h4][8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_isJalr = _RANDOM[6'h4][9]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_last_may_be_rvi_call = _RANDOM[6'h4][10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_always_taken_0 = _RANDOM[6'h4][11]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_entry_always_taken_1 = _RANDOM[6'h4][12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_1_tag = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_valid = _RANDOM[6'h5][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_brSlots_0_offset = _RANDOM[6'h5][5:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_brSlots_0_lower = _RANDOM[6'h5][17:6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_brSlots_0_tarStat = _RANDOM[6'h5][19:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_brSlots_0_sharing = _RANDOM[6'h5][20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_brSlots_0_valid = _RANDOM[6'h5][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_tailSlot_offset = _RANDOM[6'h5][25:22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_2_entry_tailSlot_lower = - {_RANDOM[6'h5][31:26], _RANDOM[6'h6][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_tailSlot_tarStat = _RANDOM[6'h6][15:14]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_tailSlot_sharing = _RANDOM[6'h6][16]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_tailSlot_valid = _RANDOM[6'h6][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_pftAddr = _RANDOM[6'h6][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_carry = _RANDOM[6'h6][22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isCall = _RANDOM[6'h6][23]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isRet = _RANDOM[6'h6][24]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_isJalr = _RANDOM[6'h6][25]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_last_may_be_rvi_call = _RANDOM[6'h6][26]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_always_taken_0 = _RANDOM[6'h6][27]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_entry_always_taken_1 = _RANDOM[6'h6][28]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_2_tag = {_RANDOM[6'h6][31:29], _RANDOM[6'h7][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_valid = _RANDOM[6'h7][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_brSlots_0_offset = _RANDOM[6'h7][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + {_RANDOM[6'h5][31:26], _RANDOM[6'h6][13:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_tailSlot_tarStat = _RANDOM[6'h6][15:14]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_tailSlot_sharing = _RANDOM[6'h6][16]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_tailSlot_valid = _RANDOM[6'h6][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_pftAddr = _RANDOM[6'h6][21:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_carry = _RANDOM[6'h6][22]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isCall = _RANDOM[6'h6][23]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isRet = _RANDOM[6'h6][24]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_isJalr = _RANDOM[6'h6][25]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_last_may_be_rvi_call = _RANDOM[6'h6][26]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_always_taken_0 = _RANDOM[6'h6][27]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_entry_always_taken_1 = _RANDOM[6'h6][28]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_2_tag = {_RANDOM[6'h6][31:29], _RANDOM[6'h7][16:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_valid = _RANDOM[6'h7][17]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_brSlots_0_offset = _RANDOM[6'h7][21:18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] pred_rdata_hold_data_3_entry_brSlots_0_lower = - {_RANDOM[6'h7][31:22], _RANDOM[6'h8][1:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_brSlots_0_tarStat = _RANDOM[6'h8][3:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_brSlots_0_sharing = _RANDOM[6'h8][4]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_brSlots_0_valid = _RANDOM[6'h8][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_tailSlot_offset = _RANDOM[6'h8][9:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_tailSlot_lower = _RANDOM[6'h8][29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_tailSlot_tarStat = _RANDOM[6'h8][31:30]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_tailSlot_sharing = _RANDOM[6'h9][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_tailSlot_valid = _RANDOM[6'h9][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_pftAddr = _RANDOM[6'h9][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_carry = _RANDOM[6'h9][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isCall = _RANDOM[6'h9][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isRet = _RANDOM[6'h9][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_isJalr = _RANDOM[6'h9][9]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_last_may_be_rvi_call = _RANDOM[6'h9][10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_always_taken_0 = _RANDOM[6'h9][11]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_entry_always_taken_1 = _RANDOM[6'h9][12]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - pred_rdata_hold_data_3_tag = {_RANDOM[6'h9][31:13], _RANDOM[6'hA][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 - req_tag = _RANDOM[6'hA][20:1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :324:28, utility/src/main/scala/utility/Hold.scala:24:82 - req_idx = _RANDOM[6'hA][29:21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :325:28, utility/src/main/scala/utility/Hold.scala:24:82 - u_req_tag = {_RANDOM[6'hA][31:30], _RANDOM[6'hB][17:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, utility/src/main/scala/utility/Hold.scala:24:82 - u_total_hits_REG = _RANDOM[6'hB][18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 - u_total_hits_REG_1 = _RANDOM[6'hB][19]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 - u_total_hits_REG_2 = _RANDOM[6'hB][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 - u_total_hits_REG_3 = _RANDOM[6'hB][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 - state_vec_0 = _RANDOM[6'hB][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 - state_vec_1 = _RANDOM[6'hB][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 - state_vec_2 = {_RANDOM[6'hB][31], _RANDOM[6'hC][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 - state_vec_3 = _RANDOM[6'hC][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_4 = _RANDOM[6'hC][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_5 = _RANDOM[6'hC][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_6 = _RANDOM[6'hC][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_7 = _RANDOM[6'hC][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_8 = _RANDOM[6'hC][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_9 = _RANDOM[6'hC][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_10 = _RANDOM[6'hC][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_11 = _RANDOM[6'hC][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_12 = _RANDOM[6'hC][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_13 = _RANDOM[6'hD][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_14 = _RANDOM[6'hD][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_15 = _RANDOM[6'hD][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_16 = _RANDOM[6'hD][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_17 = _RANDOM[6'hD][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_18 = _RANDOM[6'hD][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_19 = _RANDOM[6'hD][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_20 = _RANDOM[6'hD][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_21 = _RANDOM[6'hD][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_22 = _RANDOM[6'hD][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_23 = {_RANDOM[6'hD][31:30], _RANDOM[6'hE][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_24 = _RANDOM[6'hE][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_25 = _RANDOM[6'hE][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_26 = _RANDOM[6'hE][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_27 = _RANDOM[6'hE][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_28 = _RANDOM[6'hE][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_29 = _RANDOM[6'hE][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_30 = _RANDOM[6'hE][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_31 = _RANDOM[6'hE][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_32 = _RANDOM[6'hE][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_33 = _RANDOM[6'hE][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_34 = {_RANDOM[6'hE][31], _RANDOM[6'hF][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_35 = _RANDOM[6'hF][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_36 = _RANDOM[6'hF][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_37 = _RANDOM[6'hF][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_38 = _RANDOM[6'hF][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_39 = _RANDOM[6'hF][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_40 = _RANDOM[6'hF][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_41 = _RANDOM[6'hF][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_42 = _RANDOM[6'hF][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_43 = _RANDOM[6'hF][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_44 = _RANDOM[6'hF][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_45 = _RANDOM[6'h10][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_46 = _RANDOM[6'h10][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_47 = _RANDOM[6'h10][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_48 = _RANDOM[6'h10][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_49 = _RANDOM[6'h10][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_50 = _RANDOM[6'h10][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_51 = _RANDOM[6'h10][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_52 = _RANDOM[6'h10][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_53 = _RANDOM[6'h10][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_54 = _RANDOM[6'h10][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_55 = {_RANDOM[6'h10][31:30], _RANDOM[6'h11][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_56 = _RANDOM[6'h11][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_57 = _RANDOM[6'h11][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_58 = _RANDOM[6'h11][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_59 = _RANDOM[6'h11][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_60 = _RANDOM[6'h11][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_61 = _RANDOM[6'h11][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_62 = _RANDOM[6'h11][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_63 = _RANDOM[6'h11][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_64 = _RANDOM[6'h11][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_65 = _RANDOM[6'h11][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_66 = {_RANDOM[6'h11][31], _RANDOM[6'h12][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_67 = _RANDOM[6'h12][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_68 = _RANDOM[6'h12][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_69 = _RANDOM[6'h12][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_70 = _RANDOM[6'h12][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_71 = _RANDOM[6'h12][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_72 = _RANDOM[6'h12][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_73 = _RANDOM[6'h12][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_74 = _RANDOM[6'h12][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_75 = _RANDOM[6'h12][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_76 = _RANDOM[6'h12][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_77 = _RANDOM[6'h13][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_78 = _RANDOM[6'h13][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_79 = _RANDOM[6'h13][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_80 = _RANDOM[6'h13][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_81 = _RANDOM[6'h13][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_82 = _RANDOM[6'h13][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_83 = _RANDOM[6'h13][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_84 = _RANDOM[6'h13][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_85 = _RANDOM[6'h13][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_86 = _RANDOM[6'h13][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_87 = {_RANDOM[6'h13][31:30], _RANDOM[6'h14][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_88 = _RANDOM[6'h14][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_89 = _RANDOM[6'h14][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_90 = _RANDOM[6'h14][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_91 = _RANDOM[6'h14][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_92 = _RANDOM[6'h14][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_93 = _RANDOM[6'h14][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_94 = _RANDOM[6'h14][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_95 = _RANDOM[6'h14][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_96 = _RANDOM[6'h14][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_97 = _RANDOM[6'h14][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_98 = {_RANDOM[6'h14][31], _RANDOM[6'h15][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_99 = _RANDOM[6'h15][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_100 = _RANDOM[6'h15][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_101 = _RANDOM[6'h15][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_102 = _RANDOM[6'h15][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_103 = _RANDOM[6'h15][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_104 = _RANDOM[6'h15][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_105 = _RANDOM[6'h15][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_106 = _RANDOM[6'h15][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_107 = _RANDOM[6'h15][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_108 = _RANDOM[6'h15][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_109 = _RANDOM[6'h16][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_110 = _RANDOM[6'h16][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_111 = _RANDOM[6'h16][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_112 = _RANDOM[6'h16][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_113 = _RANDOM[6'h16][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_114 = _RANDOM[6'h16][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_115 = _RANDOM[6'h16][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_116 = _RANDOM[6'h16][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_117 = _RANDOM[6'h16][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_118 = _RANDOM[6'h16][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_119 = {_RANDOM[6'h16][31:30], _RANDOM[6'h17][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_120 = _RANDOM[6'h17][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_121 = _RANDOM[6'h17][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_122 = _RANDOM[6'h17][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_123 = _RANDOM[6'h17][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_124 = _RANDOM[6'h17][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_125 = _RANDOM[6'h17][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_126 = _RANDOM[6'h17][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_127 = _RANDOM[6'h17][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_128 = _RANDOM[6'h17][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_129 = _RANDOM[6'h17][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_130 = {_RANDOM[6'h17][31], _RANDOM[6'h18][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_131 = _RANDOM[6'h18][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_132 = _RANDOM[6'h18][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_133 = _RANDOM[6'h18][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_134 = _RANDOM[6'h18][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_135 = _RANDOM[6'h18][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_136 = _RANDOM[6'h18][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_137 = _RANDOM[6'h18][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_138 = _RANDOM[6'h18][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_139 = _RANDOM[6'h18][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_140 = _RANDOM[6'h18][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_141 = _RANDOM[6'h19][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_142 = _RANDOM[6'h19][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_143 = _RANDOM[6'h19][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_144 = _RANDOM[6'h19][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_145 = _RANDOM[6'h19][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_146 = _RANDOM[6'h19][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_147 = _RANDOM[6'h19][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_148 = _RANDOM[6'h19][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_149 = _RANDOM[6'h19][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_150 = _RANDOM[6'h19][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_151 = {_RANDOM[6'h19][31:30], _RANDOM[6'h1A][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_152 = _RANDOM[6'h1A][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_153 = _RANDOM[6'h1A][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_154 = _RANDOM[6'h1A][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_155 = _RANDOM[6'h1A][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_156 = _RANDOM[6'h1A][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_157 = _RANDOM[6'h1A][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_158 = _RANDOM[6'h1A][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_159 = _RANDOM[6'h1A][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_160 = _RANDOM[6'h1A][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_161 = _RANDOM[6'h1A][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_162 = {_RANDOM[6'h1A][31], _RANDOM[6'h1B][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_163 = _RANDOM[6'h1B][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_164 = _RANDOM[6'h1B][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_165 = _RANDOM[6'h1B][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_166 = _RANDOM[6'h1B][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_167 = _RANDOM[6'h1B][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_168 = _RANDOM[6'h1B][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_169 = _RANDOM[6'h1B][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_170 = _RANDOM[6'h1B][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_171 = _RANDOM[6'h1B][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_172 = _RANDOM[6'h1B][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_173 = _RANDOM[6'h1C][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_174 = _RANDOM[6'h1C][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_175 = _RANDOM[6'h1C][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_176 = _RANDOM[6'h1C][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_177 = _RANDOM[6'h1C][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_178 = _RANDOM[6'h1C][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_179 = _RANDOM[6'h1C][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_180 = _RANDOM[6'h1C][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_181 = _RANDOM[6'h1C][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_182 = _RANDOM[6'h1C][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_183 = {_RANDOM[6'h1C][31:30], _RANDOM[6'h1D][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_184 = _RANDOM[6'h1D][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_185 = _RANDOM[6'h1D][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_186 = _RANDOM[6'h1D][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_187 = _RANDOM[6'h1D][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_188 = _RANDOM[6'h1D][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_189 = _RANDOM[6'h1D][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_190 = _RANDOM[6'h1D][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_191 = _RANDOM[6'h1D][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_192 = _RANDOM[6'h1D][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_193 = _RANDOM[6'h1D][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_194 = {_RANDOM[6'h1D][31], _RANDOM[6'h1E][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_195 = _RANDOM[6'h1E][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_196 = _RANDOM[6'h1E][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_197 = _RANDOM[6'h1E][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_198 = _RANDOM[6'h1E][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_199 = _RANDOM[6'h1E][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_200 = _RANDOM[6'h1E][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_201 = _RANDOM[6'h1E][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_202 = _RANDOM[6'h1E][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_203 = _RANDOM[6'h1E][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_204 = _RANDOM[6'h1E][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_205 = _RANDOM[6'h1F][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_206 = _RANDOM[6'h1F][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_207 = _RANDOM[6'h1F][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_208 = _RANDOM[6'h1F][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_209 = _RANDOM[6'h1F][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_210 = _RANDOM[6'h1F][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_211 = _RANDOM[6'h1F][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_212 = _RANDOM[6'h1F][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_213 = _RANDOM[6'h1F][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_214 = _RANDOM[6'h1F][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_215 = {_RANDOM[6'h1F][31:30], _RANDOM[6'h20][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_216 = _RANDOM[6'h20][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_217 = _RANDOM[6'h20][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_218 = _RANDOM[6'h20][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_219 = _RANDOM[6'h20][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_220 = _RANDOM[6'h20][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_221 = _RANDOM[6'h20][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_222 = _RANDOM[6'h20][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_223 = _RANDOM[6'h20][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_224 = _RANDOM[6'h20][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_225 = _RANDOM[6'h20][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_226 = {_RANDOM[6'h20][31], _RANDOM[6'h21][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_227 = _RANDOM[6'h21][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_228 = _RANDOM[6'h21][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_229 = _RANDOM[6'h21][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_230 = _RANDOM[6'h21][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_231 = _RANDOM[6'h21][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_232 = _RANDOM[6'h21][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_233 = _RANDOM[6'h21][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_234 = _RANDOM[6'h21][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_235 = _RANDOM[6'h21][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_236 = _RANDOM[6'h21][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_237 = _RANDOM[6'h22][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_238 = _RANDOM[6'h22][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_239 = _RANDOM[6'h22][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_240 = _RANDOM[6'h22][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_241 = _RANDOM[6'h22][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_242 = _RANDOM[6'h22][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_243 = _RANDOM[6'h22][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_244 = _RANDOM[6'h22][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_245 = _RANDOM[6'h22][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_246 = _RANDOM[6'h22][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_247 = {_RANDOM[6'h22][31:30], _RANDOM[6'h23][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_248 = _RANDOM[6'h23][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_249 = _RANDOM[6'h23][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_250 = _RANDOM[6'h23][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_251 = _RANDOM[6'h23][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_252 = _RANDOM[6'h23][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_253 = _RANDOM[6'h23][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_254 = _RANDOM[6'h23][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_255 = _RANDOM[6'h23][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_256 = _RANDOM[6'h23][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_257 = _RANDOM[6'h23][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_258 = {_RANDOM[6'h23][31], _RANDOM[6'h24][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_259 = _RANDOM[6'h24][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_260 = _RANDOM[6'h24][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_261 = _RANDOM[6'h24][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_262 = _RANDOM[6'h24][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_263 = _RANDOM[6'h24][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_264 = _RANDOM[6'h24][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_265 = _RANDOM[6'h24][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_266 = _RANDOM[6'h24][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_267 = _RANDOM[6'h24][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_268 = _RANDOM[6'h24][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_269 = _RANDOM[6'h25][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_270 = _RANDOM[6'h25][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_271 = _RANDOM[6'h25][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_272 = _RANDOM[6'h25][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_273 = _RANDOM[6'h25][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_274 = _RANDOM[6'h25][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_275 = _RANDOM[6'h25][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_276 = _RANDOM[6'h25][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_277 = _RANDOM[6'h25][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_278 = _RANDOM[6'h25][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_279 = {_RANDOM[6'h25][31:30], _RANDOM[6'h26][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_280 = _RANDOM[6'h26][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_281 = _RANDOM[6'h26][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_282 = _RANDOM[6'h26][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_283 = _RANDOM[6'h26][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_284 = _RANDOM[6'h26][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_285 = _RANDOM[6'h26][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_286 = _RANDOM[6'h26][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_287 = _RANDOM[6'h26][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_288 = _RANDOM[6'h26][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_289 = _RANDOM[6'h26][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_290 = {_RANDOM[6'h26][31], _RANDOM[6'h27][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_291 = _RANDOM[6'h27][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_292 = _RANDOM[6'h27][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_293 = _RANDOM[6'h27][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_294 = _RANDOM[6'h27][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_295 = _RANDOM[6'h27][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_296 = _RANDOM[6'h27][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_297 = _RANDOM[6'h27][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_298 = _RANDOM[6'h27][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_299 = _RANDOM[6'h27][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_300 = _RANDOM[6'h27][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_301 = _RANDOM[6'h28][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_302 = _RANDOM[6'h28][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_303 = _RANDOM[6'h28][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_304 = _RANDOM[6'h28][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_305 = _RANDOM[6'h28][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_306 = _RANDOM[6'h28][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_307 = _RANDOM[6'h28][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_308 = _RANDOM[6'h28][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_309 = _RANDOM[6'h28][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_310 = _RANDOM[6'h28][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_311 = {_RANDOM[6'h28][31:30], _RANDOM[6'h29][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_312 = _RANDOM[6'h29][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_313 = _RANDOM[6'h29][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_314 = _RANDOM[6'h29][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_315 = _RANDOM[6'h29][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_316 = _RANDOM[6'h29][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_317 = _RANDOM[6'h29][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_318 = _RANDOM[6'h29][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_319 = _RANDOM[6'h29][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_320 = _RANDOM[6'h29][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_321 = _RANDOM[6'h29][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_322 = {_RANDOM[6'h29][31], _RANDOM[6'h2A][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_323 = _RANDOM[6'h2A][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_324 = _RANDOM[6'h2A][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_325 = _RANDOM[6'h2A][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_326 = _RANDOM[6'h2A][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_327 = _RANDOM[6'h2A][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_328 = _RANDOM[6'h2A][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_329 = _RANDOM[6'h2A][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_330 = _RANDOM[6'h2A][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_331 = _RANDOM[6'h2A][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_332 = _RANDOM[6'h2A][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_333 = _RANDOM[6'h2B][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_334 = _RANDOM[6'h2B][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_335 = _RANDOM[6'h2B][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_336 = _RANDOM[6'h2B][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_337 = _RANDOM[6'h2B][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_338 = _RANDOM[6'h2B][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_339 = _RANDOM[6'h2B][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_340 = _RANDOM[6'h2B][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_341 = _RANDOM[6'h2B][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_342 = _RANDOM[6'h2B][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_343 = {_RANDOM[6'h2B][31:30], _RANDOM[6'h2C][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_344 = _RANDOM[6'h2C][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_345 = _RANDOM[6'h2C][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_346 = _RANDOM[6'h2C][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_347 = _RANDOM[6'h2C][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_348 = _RANDOM[6'h2C][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_349 = _RANDOM[6'h2C][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_350 = _RANDOM[6'h2C][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_351 = _RANDOM[6'h2C][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_352 = _RANDOM[6'h2C][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_353 = _RANDOM[6'h2C][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_354 = {_RANDOM[6'h2C][31], _RANDOM[6'h2D][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_355 = _RANDOM[6'h2D][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_356 = _RANDOM[6'h2D][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_357 = _RANDOM[6'h2D][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_358 = _RANDOM[6'h2D][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_359 = _RANDOM[6'h2D][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_360 = _RANDOM[6'h2D][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_361 = _RANDOM[6'h2D][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_362 = _RANDOM[6'h2D][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_363 = _RANDOM[6'h2D][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_364 = _RANDOM[6'h2D][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_365 = _RANDOM[6'h2E][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_366 = _RANDOM[6'h2E][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_367 = _RANDOM[6'h2E][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_368 = _RANDOM[6'h2E][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_369 = _RANDOM[6'h2E][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_370 = _RANDOM[6'h2E][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_371 = _RANDOM[6'h2E][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_372 = _RANDOM[6'h2E][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_373 = _RANDOM[6'h2E][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_374 = _RANDOM[6'h2E][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_375 = {_RANDOM[6'h2E][31:30], _RANDOM[6'h2F][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_376 = _RANDOM[6'h2F][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_377 = _RANDOM[6'h2F][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_378 = _RANDOM[6'h2F][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_379 = _RANDOM[6'h2F][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_380 = _RANDOM[6'h2F][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_381 = _RANDOM[6'h2F][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_382 = _RANDOM[6'h2F][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_383 = _RANDOM[6'h2F][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_384 = _RANDOM[6'h2F][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_385 = _RANDOM[6'h2F][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_386 = {_RANDOM[6'h2F][31], _RANDOM[6'h30][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_387 = _RANDOM[6'h30][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_388 = _RANDOM[6'h30][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_389 = _RANDOM[6'h30][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_390 = _RANDOM[6'h30][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_391 = _RANDOM[6'h30][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_392 = _RANDOM[6'h30][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_393 = _RANDOM[6'h30][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_394 = _RANDOM[6'h30][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_395 = _RANDOM[6'h30][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_396 = _RANDOM[6'h30][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_397 = _RANDOM[6'h31][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_398 = _RANDOM[6'h31][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_399 = _RANDOM[6'h31][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_400 = _RANDOM[6'h31][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_401 = _RANDOM[6'h31][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_402 = _RANDOM[6'h31][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_403 = _RANDOM[6'h31][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_404 = _RANDOM[6'h31][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_405 = _RANDOM[6'h31][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_406 = _RANDOM[6'h31][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_407 = {_RANDOM[6'h31][31:30], _RANDOM[6'h32][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_408 = _RANDOM[6'h32][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_409 = _RANDOM[6'h32][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_410 = _RANDOM[6'h32][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_411 = _RANDOM[6'h32][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_412 = _RANDOM[6'h32][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_413 = _RANDOM[6'h32][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_414 = _RANDOM[6'h32][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_415 = _RANDOM[6'h32][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_416 = _RANDOM[6'h32][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_417 = _RANDOM[6'h32][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_418 = {_RANDOM[6'h32][31], _RANDOM[6'h33][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_419 = _RANDOM[6'h33][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_420 = _RANDOM[6'h33][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_421 = _RANDOM[6'h33][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_422 = _RANDOM[6'h33][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_423 = _RANDOM[6'h33][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_424 = _RANDOM[6'h33][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_425 = _RANDOM[6'h33][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_426 = _RANDOM[6'h33][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_427 = _RANDOM[6'h33][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_428 = _RANDOM[6'h33][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_429 = _RANDOM[6'h34][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_430 = _RANDOM[6'h34][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_431 = _RANDOM[6'h34][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_432 = _RANDOM[6'h34][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_433 = _RANDOM[6'h34][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_434 = _RANDOM[6'h34][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_435 = _RANDOM[6'h34][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_436 = _RANDOM[6'h34][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_437 = _RANDOM[6'h34][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_438 = _RANDOM[6'h34][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_439 = {_RANDOM[6'h34][31:30], _RANDOM[6'h35][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_440 = _RANDOM[6'h35][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_441 = _RANDOM[6'h35][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_442 = _RANDOM[6'h35][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_443 = _RANDOM[6'h35][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_444 = _RANDOM[6'h35][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_445 = _RANDOM[6'h35][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_446 = _RANDOM[6'h35][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_447 = _RANDOM[6'h35][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_448 = _RANDOM[6'h35][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_449 = _RANDOM[6'h35][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_450 = {_RANDOM[6'h35][31], _RANDOM[6'h36][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_451 = _RANDOM[6'h36][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_452 = _RANDOM[6'h36][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_453 = _RANDOM[6'h36][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_454 = _RANDOM[6'h36][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_455 = _RANDOM[6'h36][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_456 = _RANDOM[6'h36][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_457 = _RANDOM[6'h36][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_458 = _RANDOM[6'h36][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_459 = _RANDOM[6'h36][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_460 = _RANDOM[6'h36][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_461 = _RANDOM[6'h37][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_462 = _RANDOM[6'h37][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_463 = _RANDOM[6'h37][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_464 = _RANDOM[6'h37][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_465 = _RANDOM[6'h37][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_466 = _RANDOM[6'h37][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_467 = _RANDOM[6'h37][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_468 = _RANDOM[6'h37][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_469 = _RANDOM[6'h37][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_470 = _RANDOM[6'h37][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_471 = {_RANDOM[6'h37][31:30], _RANDOM[6'h38][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_472 = _RANDOM[6'h38][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_473 = _RANDOM[6'h38][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_474 = _RANDOM[6'h38][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_475 = _RANDOM[6'h38][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_476 = _RANDOM[6'h38][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_477 = _RANDOM[6'h38][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_478 = _RANDOM[6'h38][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_479 = _RANDOM[6'h38][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_480 = _RANDOM[6'h38][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_481 = _RANDOM[6'h38][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_482 = {_RANDOM[6'h38][31], _RANDOM[6'h39][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_483 = _RANDOM[6'h39][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_484 = _RANDOM[6'h39][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_485 = _RANDOM[6'h39][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_486 = _RANDOM[6'h39][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_487 = _RANDOM[6'h39][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_488 = _RANDOM[6'h39][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_489 = _RANDOM[6'h39][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_490 = _RANDOM[6'h39][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_491 = _RANDOM[6'h39][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_492 = _RANDOM[6'h39][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_493 = _RANDOM[6'h3A][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_494 = _RANDOM[6'h3A][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_495 = _RANDOM[6'h3A][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_496 = _RANDOM[6'h3A][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_497 = _RANDOM[6'h3A][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_498 = _RANDOM[6'h3A][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_499 = _RANDOM[6'h3A][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_500 = _RANDOM[6'h3A][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_501 = _RANDOM[6'h3A][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_502 = _RANDOM[6'h3A][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_503 = {_RANDOM[6'h3A][31:30], _RANDOM[6'h3B][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_504 = _RANDOM[6'h3B][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_505 = _RANDOM[6'h3B][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_506 = _RANDOM[6'h3B][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_507 = _RANDOM[6'h3B][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_508 = _RANDOM[6'h3B][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_509 = _RANDOM[6'h3B][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_510 = _RANDOM[6'h3B][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_511 = _RANDOM[6'h3B][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 - touch_set_0_REG = {_RANDOM[6'h3B][31:25], _RANDOM[6'h3C][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60 - touch_way_0_valid_REG = _RANDOM[6'h3C][2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :369:53 - touch_way_0_bits_REG = _RANDOM[6'h3C][4:3]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :370:70 - allocWriteWay_REG_0 = _RANDOM[6'h3C][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 - allocWriteWay_REG_1 = _RANDOM[6'h3C][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 - allocWriteWay_REG_2 = _RANDOM[6'h3C][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 - allocWriteWay_REG_3 = _RANDOM[6'h3C][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 + {_RANDOM[6'h7][31:22], _RANDOM[6'h8][1:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_brSlots_0_tarStat = _RANDOM[6'h8][3:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_brSlots_0_sharing = _RANDOM[6'h8][4]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_brSlots_0_valid = _RANDOM[6'h8][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_tailSlot_offset = _RANDOM[6'h8][9:6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_tailSlot_lower = _RANDOM[6'h8][29:10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_tailSlot_tarStat = _RANDOM[6'h8][31:30]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_tailSlot_sharing = _RANDOM[6'h9][0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_tailSlot_valid = _RANDOM[6'h9][1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_pftAddr = _RANDOM[6'h9][5:2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_carry = _RANDOM[6'h9][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isCall = _RANDOM[6'h9][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isRet = _RANDOM[6'h9][8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_isJalr = _RANDOM[6'h9][9]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_last_may_be_rvi_call = _RANDOM[6'h9][10]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_always_taken_0 = _RANDOM[6'h9][11]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_entry_always_taken_1 = _RANDOM[6'h9][12]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + pred_rdata_hold_data_3_tag = {_RANDOM[6'h9][31:13], _RANDOM[6'hA][0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82] + req_tag = _RANDOM[6'hA][20:1]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :324:28, utility/src/main/scala/utility/Hold.scala:24:82] + req_idx = _RANDOM[6'hA][29:21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :325:28, utility/src/main/scala/utility/Hold.scala:24:82] + u_req_tag = {_RANDOM[6'hA][31:30], _RANDOM[6'hB][17:0]}; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, utility/src/main/scala/utility/Hold.scala:24:82] + u_total_hits_REG = _RANDOM[6'hB][18]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96] + u_total_hits_REG_1 = _RANDOM[6'hB][19]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96] + u_total_hits_REG_2 = _RANDOM[6'hB][20]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96] + u_total_hits_REG_3 = _RANDOM[6'hB][21]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96] + state_vec_0 = _RANDOM[6'hB][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30] + state_vec_1 = _RANDOM[6'hB][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30] + state_vec_2 = {_RANDOM[6'hB][31], _RANDOM[6'hC][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30] + state_vec_3 = _RANDOM[6'hC][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_4 = _RANDOM[6'hC][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_5 = _RANDOM[6'hC][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_6 = _RANDOM[6'hC][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_7 = _RANDOM[6'hC][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_8 = _RANDOM[6'hC][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_9 = _RANDOM[6'hC][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_10 = _RANDOM[6'hC][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_11 = _RANDOM[6'hC][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_12 = _RANDOM[6'hC][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_13 = _RANDOM[6'hD][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_14 = _RANDOM[6'hD][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_15 = _RANDOM[6'hD][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_16 = _RANDOM[6'hD][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_17 = _RANDOM[6'hD][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_18 = _RANDOM[6'hD][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_19 = _RANDOM[6'hD][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_20 = _RANDOM[6'hD][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_21 = _RANDOM[6'hD][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_22 = _RANDOM[6'hD][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_23 = {_RANDOM[6'hD][31:30], _RANDOM[6'hE][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_24 = _RANDOM[6'hE][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_25 = _RANDOM[6'hE][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_26 = _RANDOM[6'hE][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_27 = _RANDOM[6'hE][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_28 = _RANDOM[6'hE][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_29 = _RANDOM[6'hE][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_30 = _RANDOM[6'hE][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_31 = _RANDOM[6'hE][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_32 = _RANDOM[6'hE][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_33 = _RANDOM[6'hE][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_34 = {_RANDOM[6'hE][31], _RANDOM[6'hF][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_35 = _RANDOM[6'hF][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_36 = _RANDOM[6'hF][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_37 = _RANDOM[6'hF][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_38 = _RANDOM[6'hF][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_39 = _RANDOM[6'hF][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_40 = _RANDOM[6'hF][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_41 = _RANDOM[6'hF][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_42 = _RANDOM[6'hF][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_43 = _RANDOM[6'hF][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_44 = _RANDOM[6'hF][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_45 = _RANDOM[6'h10][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_46 = _RANDOM[6'h10][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_47 = _RANDOM[6'h10][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_48 = _RANDOM[6'h10][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_49 = _RANDOM[6'h10][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_50 = _RANDOM[6'h10][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_51 = _RANDOM[6'h10][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_52 = _RANDOM[6'h10][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_53 = _RANDOM[6'h10][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_54 = _RANDOM[6'h10][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_55 = {_RANDOM[6'h10][31:30], _RANDOM[6'h11][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_56 = _RANDOM[6'h11][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_57 = _RANDOM[6'h11][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_58 = _RANDOM[6'h11][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_59 = _RANDOM[6'h11][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_60 = _RANDOM[6'h11][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_61 = _RANDOM[6'h11][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_62 = _RANDOM[6'h11][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_63 = _RANDOM[6'h11][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_64 = _RANDOM[6'h11][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_65 = _RANDOM[6'h11][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_66 = {_RANDOM[6'h11][31], _RANDOM[6'h12][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_67 = _RANDOM[6'h12][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_68 = _RANDOM[6'h12][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_69 = _RANDOM[6'h12][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_70 = _RANDOM[6'h12][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_71 = _RANDOM[6'h12][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_72 = _RANDOM[6'h12][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_73 = _RANDOM[6'h12][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_74 = _RANDOM[6'h12][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_75 = _RANDOM[6'h12][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_76 = _RANDOM[6'h12][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_77 = _RANDOM[6'h13][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_78 = _RANDOM[6'h13][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_79 = _RANDOM[6'h13][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_80 = _RANDOM[6'h13][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_81 = _RANDOM[6'h13][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_82 = _RANDOM[6'h13][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_83 = _RANDOM[6'h13][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_84 = _RANDOM[6'h13][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_85 = _RANDOM[6'h13][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_86 = _RANDOM[6'h13][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_87 = {_RANDOM[6'h13][31:30], _RANDOM[6'h14][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_88 = _RANDOM[6'h14][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_89 = _RANDOM[6'h14][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_90 = _RANDOM[6'h14][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_91 = _RANDOM[6'h14][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_92 = _RANDOM[6'h14][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_93 = _RANDOM[6'h14][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_94 = _RANDOM[6'h14][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_95 = _RANDOM[6'h14][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_96 = _RANDOM[6'h14][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_97 = _RANDOM[6'h14][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_98 = {_RANDOM[6'h14][31], _RANDOM[6'h15][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_99 = _RANDOM[6'h15][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_100 = _RANDOM[6'h15][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_101 = _RANDOM[6'h15][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_102 = _RANDOM[6'h15][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_103 = _RANDOM[6'h15][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_104 = _RANDOM[6'h15][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_105 = _RANDOM[6'h15][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_106 = _RANDOM[6'h15][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_107 = _RANDOM[6'h15][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_108 = _RANDOM[6'h15][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_109 = _RANDOM[6'h16][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_110 = _RANDOM[6'h16][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_111 = _RANDOM[6'h16][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_112 = _RANDOM[6'h16][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_113 = _RANDOM[6'h16][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_114 = _RANDOM[6'h16][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_115 = _RANDOM[6'h16][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_116 = _RANDOM[6'h16][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_117 = _RANDOM[6'h16][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_118 = _RANDOM[6'h16][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_119 = {_RANDOM[6'h16][31:30], _RANDOM[6'h17][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_120 = _RANDOM[6'h17][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_121 = _RANDOM[6'h17][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_122 = _RANDOM[6'h17][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_123 = _RANDOM[6'h17][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_124 = _RANDOM[6'h17][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_125 = _RANDOM[6'h17][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_126 = _RANDOM[6'h17][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_127 = _RANDOM[6'h17][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_128 = _RANDOM[6'h17][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_129 = _RANDOM[6'h17][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_130 = {_RANDOM[6'h17][31], _RANDOM[6'h18][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_131 = _RANDOM[6'h18][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_132 = _RANDOM[6'h18][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_133 = _RANDOM[6'h18][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_134 = _RANDOM[6'h18][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_135 = _RANDOM[6'h18][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_136 = _RANDOM[6'h18][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_137 = _RANDOM[6'h18][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_138 = _RANDOM[6'h18][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_139 = _RANDOM[6'h18][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_140 = _RANDOM[6'h18][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_141 = _RANDOM[6'h19][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_142 = _RANDOM[6'h19][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_143 = _RANDOM[6'h19][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_144 = _RANDOM[6'h19][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_145 = _RANDOM[6'h19][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_146 = _RANDOM[6'h19][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_147 = _RANDOM[6'h19][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_148 = _RANDOM[6'h19][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_149 = _RANDOM[6'h19][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_150 = _RANDOM[6'h19][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_151 = {_RANDOM[6'h19][31:30], _RANDOM[6'h1A][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_152 = _RANDOM[6'h1A][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_153 = _RANDOM[6'h1A][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_154 = _RANDOM[6'h1A][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_155 = _RANDOM[6'h1A][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_156 = _RANDOM[6'h1A][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_157 = _RANDOM[6'h1A][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_158 = _RANDOM[6'h1A][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_159 = _RANDOM[6'h1A][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_160 = _RANDOM[6'h1A][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_161 = _RANDOM[6'h1A][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_162 = {_RANDOM[6'h1A][31], _RANDOM[6'h1B][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_163 = _RANDOM[6'h1B][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_164 = _RANDOM[6'h1B][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_165 = _RANDOM[6'h1B][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_166 = _RANDOM[6'h1B][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_167 = _RANDOM[6'h1B][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_168 = _RANDOM[6'h1B][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_169 = _RANDOM[6'h1B][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_170 = _RANDOM[6'h1B][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_171 = _RANDOM[6'h1B][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_172 = _RANDOM[6'h1B][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_173 = _RANDOM[6'h1C][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_174 = _RANDOM[6'h1C][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_175 = _RANDOM[6'h1C][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_176 = _RANDOM[6'h1C][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_177 = _RANDOM[6'h1C][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_178 = _RANDOM[6'h1C][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_179 = _RANDOM[6'h1C][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_180 = _RANDOM[6'h1C][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_181 = _RANDOM[6'h1C][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_182 = _RANDOM[6'h1C][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_183 = {_RANDOM[6'h1C][31:30], _RANDOM[6'h1D][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_184 = _RANDOM[6'h1D][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_185 = _RANDOM[6'h1D][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_186 = _RANDOM[6'h1D][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_187 = _RANDOM[6'h1D][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_188 = _RANDOM[6'h1D][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_189 = _RANDOM[6'h1D][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_190 = _RANDOM[6'h1D][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_191 = _RANDOM[6'h1D][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_192 = _RANDOM[6'h1D][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_193 = _RANDOM[6'h1D][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_194 = {_RANDOM[6'h1D][31], _RANDOM[6'h1E][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_195 = _RANDOM[6'h1E][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_196 = _RANDOM[6'h1E][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_197 = _RANDOM[6'h1E][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_198 = _RANDOM[6'h1E][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_199 = _RANDOM[6'h1E][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_200 = _RANDOM[6'h1E][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_201 = _RANDOM[6'h1E][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_202 = _RANDOM[6'h1E][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_203 = _RANDOM[6'h1E][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_204 = _RANDOM[6'h1E][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_205 = _RANDOM[6'h1F][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_206 = _RANDOM[6'h1F][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_207 = _RANDOM[6'h1F][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_208 = _RANDOM[6'h1F][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_209 = _RANDOM[6'h1F][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_210 = _RANDOM[6'h1F][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_211 = _RANDOM[6'h1F][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_212 = _RANDOM[6'h1F][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_213 = _RANDOM[6'h1F][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_214 = _RANDOM[6'h1F][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_215 = {_RANDOM[6'h1F][31:30], _RANDOM[6'h20][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_216 = _RANDOM[6'h20][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_217 = _RANDOM[6'h20][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_218 = _RANDOM[6'h20][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_219 = _RANDOM[6'h20][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_220 = _RANDOM[6'h20][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_221 = _RANDOM[6'h20][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_222 = _RANDOM[6'h20][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_223 = _RANDOM[6'h20][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_224 = _RANDOM[6'h20][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_225 = _RANDOM[6'h20][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_226 = {_RANDOM[6'h20][31], _RANDOM[6'h21][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_227 = _RANDOM[6'h21][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_228 = _RANDOM[6'h21][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_229 = _RANDOM[6'h21][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_230 = _RANDOM[6'h21][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_231 = _RANDOM[6'h21][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_232 = _RANDOM[6'h21][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_233 = _RANDOM[6'h21][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_234 = _RANDOM[6'h21][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_235 = _RANDOM[6'h21][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_236 = _RANDOM[6'h21][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_237 = _RANDOM[6'h22][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_238 = _RANDOM[6'h22][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_239 = _RANDOM[6'h22][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_240 = _RANDOM[6'h22][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_241 = _RANDOM[6'h22][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_242 = _RANDOM[6'h22][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_243 = _RANDOM[6'h22][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_244 = _RANDOM[6'h22][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_245 = _RANDOM[6'h22][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_246 = _RANDOM[6'h22][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_247 = {_RANDOM[6'h22][31:30], _RANDOM[6'h23][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_248 = _RANDOM[6'h23][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_249 = _RANDOM[6'h23][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_250 = _RANDOM[6'h23][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_251 = _RANDOM[6'h23][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_252 = _RANDOM[6'h23][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_253 = _RANDOM[6'h23][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_254 = _RANDOM[6'h23][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_255 = _RANDOM[6'h23][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_256 = _RANDOM[6'h23][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_257 = _RANDOM[6'h23][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_258 = {_RANDOM[6'h23][31], _RANDOM[6'h24][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_259 = _RANDOM[6'h24][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_260 = _RANDOM[6'h24][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_261 = _RANDOM[6'h24][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_262 = _RANDOM[6'h24][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_263 = _RANDOM[6'h24][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_264 = _RANDOM[6'h24][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_265 = _RANDOM[6'h24][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_266 = _RANDOM[6'h24][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_267 = _RANDOM[6'h24][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_268 = _RANDOM[6'h24][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_269 = _RANDOM[6'h25][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_270 = _RANDOM[6'h25][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_271 = _RANDOM[6'h25][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_272 = _RANDOM[6'h25][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_273 = _RANDOM[6'h25][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_274 = _RANDOM[6'h25][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_275 = _RANDOM[6'h25][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_276 = _RANDOM[6'h25][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_277 = _RANDOM[6'h25][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_278 = _RANDOM[6'h25][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_279 = {_RANDOM[6'h25][31:30], _RANDOM[6'h26][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_280 = _RANDOM[6'h26][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_281 = _RANDOM[6'h26][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_282 = _RANDOM[6'h26][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_283 = _RANDOM[6'h26][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_284 = _RANDOM[6'h26][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_285 = _RANDOM[6'h26][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_286 = _RANDOM[6'h26][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_287 = _RANDOM[6'h26][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_288 = _RANDOM[6'h26][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_289 = _RANDOM[6'h26][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_290 = {_RANDOM[6'h26][31], _RANDOM[6'h27][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_291 = _RANDOM[6'h27][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_292 = _RANDOM[6'h27][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_293 = _RANDOM[6'h27][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_294 = _RANDOM[6'h27][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_295 = _RANDOM[6'h27][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_296 = _RANDOM[6'h27][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_297 = _RANDOM[6'h27][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_298 = _RANDOM[6'h27][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_299 = _RANDOM[6'h27][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_300 = _RANDOM[6'h27][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_301 = _RANDOM[6'h28][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_302 = _RANDOM[6'h28][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_303 = _RANDOM[6'h28][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_304 = _RANDOM[6'h28][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_305 = _RANDOM[6'h28][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_306 = _RANDOM[6'h28][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_307 = _RANDOM[6'h28][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_308 = _RANDOM[6'h28][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_309 = _RANDOM[6'h28][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_310 = _RANDOM[6'h28][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_311 = {_RANDOM[6'h28][31:30], _RANDOM[6'h29][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_312 = _RANDOM[6'h29][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_313 = _RANDOM[6'h29][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_314 = _RANDOM[6'h29][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_315 = _RANDOM[6'h29][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_316 = _RANDOM[6'h29][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_317 = _RANDOM[6'h29][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_318 = _RANDOM[6'h29][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_319 = _RANDOM[6'h29][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_320 = _RANDOM[6'h29][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_321 = _RANDOM[6'h29][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_322 = {_RANDOM[6'h29][31], _RANDOM[6'h2A][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_323 = _RANDOM[6'h2A][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_324 = _RANDOM[6'h2A][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_325 = _RANDOM[6'h2A][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_326 = _RANDOM[6'h2A][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_327 = _RANDOM[6'h2A][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_328 = _RANDOM[6'h2A][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_329 = _RANDOM[6'h2A][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_330 = _RANDOM[6'h2A][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_331 = _RANDOM[6'h2A][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_332 = _RANDOM[6'h2A][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_333 = _RANDOM[6'h2B][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_334 = _RANDOM[6'h2B][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_335 = _RANDOM[6'h2B][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_336 = _RANDOM[6'h2B][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_337 = _RANDOM[6'h2B][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_338 = _RANDOM[6'h2B][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_339 = _RANDOM[6'h2B][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_340 = _RANDOM[6'h2B][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_341 = _RANDOM[6'h2B][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_342 = _RANDOM[6'h2B][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_343 = {_RANDOM[6'h2B][31:30], _RANDOM[6'h2C][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_344 = _RANDOM[6'h2C][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_345 = _RANDOM[6'h2C][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_346 = _RANDOM[6'h2C][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_347 = _RANDOM[6'h2C][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_348 = _RANDOM[6'h2C][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_349 = _RANDOM[6'h2C][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_350 = _RANDOM[6'h2C][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_351 = _RANDOM[6'h2C][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_352 = _RANDOM[6'h2C][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_353 = _RANDOM[6'h2C][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_354 = {_RANDOM[6'h2C][31], _RANDOM[6'h2D][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_355 = _RANDOM[6'h2D][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_356 = _RANDOM[6'h2D][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_357 = _RANDOM[6'h2D][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_358 = _RANDOM[6'h2D][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_359 = _RANDOM[6'h2D][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_360 = _RANDOM[6'h2D][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_361 = _RANDOM[6'h2D][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_362 = _RANDOM[6'h2D][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_363 = _RANDOM[6'h2D][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_364 = _RANDOM[6'h2D][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_365 = _RANDOM[6'h2E][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_366 = _RANDOM[6'h2E][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_367 = _RANDOM[6'h2E][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_368 = _RANDOM[6'h2E][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_369 = _RANDOM[6'h2E][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_370 = _RANDOM[6'h2E][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_371 = _RANDOM[6'h2E][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_372 = _RANDOM[6'h2E][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_373 = _RANDOM[6'h2E][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_374 = _RANDOM[6'h2E][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_375 = {_RANDOM[6'h2E][31:30], _RANDOM[6'h2F][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_376 = _RANDOM[6'h2F][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_377 = _RANDOM[6'h2F][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_378 = _RANDOM[6'h2F][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_379 = _RANDOM[6'h2F][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_380 = _RANDOM[6'h2F][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_381 = _RANDOM[6'h2F][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_382 = _RANDOM[6'h2F][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_383 = _RANDOM[6'h2F][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_384 = _RANDOM[6'h2F][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_385 = _RANDOM[6'h2F][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_386 = {_RANDOM[6'h2F][31], _RANDOM[6'h30][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_387 = _RANDOM[6'h30][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_388 = _RANDOM[6'h30][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_389 = _RANDOM[6'h30][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_390 = _RANDOM[6'h30][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_391 = _RANDOM[6'h30][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_392 = _RANDOM[6'h30][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_393 = _RANDOM[6'h30][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_394 = _RANDOM[6'h30][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_395 = _RANDOM[6'h30][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_396 = _RANDOM[6'h30][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_397 = _RANDOM[6'h31][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_398 = _RANDOM[6'h31][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_399 = _RANDOM[6'h31][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_400 = _RANDOM[6'h31][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_401 = _RANDOM[6'h31][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_402 = _RANDOM[6'h31][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_403 = _RANDOM[6'h31][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_404 = _RANDOM[6'h31][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_405 = _RANDOM[6'h31][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_406 = _RANDOM[6'h31][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_407 = {_RANDOM[6'h31][31:30], _RANDOM[6'h32][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_408 = _RANDOM[6'h32][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_409 = _RANDOM[6'h32][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_410 = _RANDOM[6'h32][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_411 = _RANDOM[6'h32][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_412 = _RANDOM[6'h32][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_413 = _RANDOM[6'h32][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_414 = _RANDOM[6'h32][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_415 = _RANDOM[6'h32][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_416 = _RANDOM[6'h32][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_417 = _RANDOM[6'h32][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_418 = {_RANDOM[6'h32][31], _RANDOM[6'h33][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_419 = _RANDOM[6'h33][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_420 = _RANDOM[6'h33][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_421 = _RANDOM[6'h33][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_422 = _RANDOM[6'h33][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_423 = _RANDOM[6'h33][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_424 = _RANDOM[6'h33][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_425 = _RANDOM[6'h33][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_426 = _RANDOM[6'h33][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_427 = _RANDOM[6'h33][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_428 = _RANDOM[6'h33][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_429 = _RANDOM[6'h34][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_430 = _RANDOM[6'h34][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_431 = _RANDOM[6'h34][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_432 = _RANDOM[6'h34][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_433 = _RANDOM[6'h34][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_434 = _RANDOM[6'h34][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_435 = _RANDOM[6'h34][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_436 = _RANDOM[6'h34][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_437 = _RANDOM[6'h34][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_438 = _RANDOM[6'h34][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_439 = {_RANDOM[6'h34][31:30], _RANDOM[6'h35][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_440 = _RANDOM[6'h35][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_441 = _RANDOM[6'h35][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_442 = _RANDOM[6'h35][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_443 = _RANDOM[6'h35][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_444 = _RANDOM[6'h35][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_445 = _RANDOM[6'h35][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_446 = _RANDOM[6'h35][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_447 = _RANDOM[6'h35][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_448 = _RANDOM[6'h35][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_449 = _RANDOM[6'h35][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_450 = {_RANDOM[6'h35][31], _RANDOM[6'h36][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_451 = _RANDOM[6'h36][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_452 = _RANDOM[6'h36][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_453 = _RANDOM[6'h36][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_454 = _RANDOM[6'h36][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_455 = _RANDOM[6'h36][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_456 = _RANDOM[6'h36][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_457 = _RANDOM[6'h36][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_458 = _RANDOM[6'h36][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_459 = _RANDOM[6'h36][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_460 = _RANDOM[6'h36][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_461 = _RANDOM[6'h37][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_462 = _RANDOM[6'h37][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_463 = _RANDOM[6'h37][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_464 = _RANDOM[6'h37][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_465 = _RANDOM[6'h37][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_466 = _RANDOM[6'h37][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_467 = _RANDOM[6'h37][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_468 = _RANDOM[6'h37][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_469 = _RANDOM[6'h37][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_470 = _RANDOM[6'h37][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_471 = {_RANDOM[6'h37][31:30], _RANDOM[6'h38][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_472 = _RANDOM[6'h38][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_473 = _RANDOM[6'h38][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_474 = _RANDOM[6'h38][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_475 = _RANDOM[6'h38][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_476 = _RANDOM[6'h38][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_477 = _RANDOM[6'h38][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_478 = _RANDOM[6'h38][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_479 = _RANDOM[6'h38][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_480 = _RANDOM[6'h38][27:25]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_481 = _RANDOM[6'h38][30:28]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_482 = {_RANDOM[6'h38][31], _RANDOM[6'h39][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_483 = _RANDOM[6'h39][4:2]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_484 = _RANDOM[6'h39][7:5]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_485 = _RANDOM[6'h39][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_486 = _RANDOM[6'h39][13:11]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_487 = _RANDOM[6'h39][16:14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_488 = _RANDOM[6'h39][19:17]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_489 = _RANDOM[6'h39][22:20]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_490 = _RANDOM[6'h39][25:23]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_491 = _RANDOM[6'h39][28:26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_492 = _RANDOM[6'h39][31:29]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_493 = _RANDOM[6'h3A][2:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_494 = _RANDOM[6'h3A][5:3]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_495 = _RANDOM[6'h3A][8:6]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_496 = _RANDOM[6'h3A][11:9]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_497 = _RANDOM[6'h3A][14:12]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_498 = _RANDOM[6'h3A][17:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_499 = _RANDOM[6'h3A][20:18]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_500 = _RANDOM[6'h3A][23:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_501 = _RANDOM[6'h3A][26:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_502 = _RANDOM[6'h3A][29:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_503 = {_RANDOM[6'h3A][31:30], _RANDOM[6'h3B][0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_504 = _RANDOM[6'h3B][3:1]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_505 = _RANDOM[6'h3B][6:4]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_506 = _RANDOM[6'h3B][9:7]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_507 = _RANDOM[6'h3B][12:10]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_508 = _RANDOM[6'h3B][15:13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_509 = _RANDOM[6'h3B][18:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_510 = _RANDOM[6'h3B][21:19]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_511 = _RANDOM[6'h3B][24:22]; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9] + touch_set_0_REG = {_RANDOM[6'h3B][31:25], _RANDOM[6'h3C][1:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60] + touch_way_0_valid_REG = _RANDOM[6'h3C][2]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :369:53] + touch_way_0_bits_REG = _RANDOM[6'h3C][4:3]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :370:70] + allocWriteWay_REG_0 = _RANDOM[6'h3C][5]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41] + allocWriteWay_REG_1 = _RANDOM[6'h3C][6]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41] + allocWriteWay_REG_2 = _RANDOM[6'h3C][7]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41] + allocWriteWay_REG_3 = _RANDOM[6'h3C][8]; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - state_vec_0 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_1 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_2 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_3 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_4 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_5 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_6 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_7 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_8 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_9 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_10 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_11 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_12 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_13 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_14 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_15 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_16 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_17 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_18 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_19 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_20 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_21 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_22 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_23 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_24 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_25 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_26 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_27 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_28 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_29 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_30 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_31 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_32 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_33 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_34 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_35 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_36 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_37 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_38 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_39 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_40 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_41 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_42 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_43 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_44 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_45 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_46 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_47 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_48 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_49 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_50 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_51 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_52 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_53 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_54 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_55 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_56 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_57 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_58 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_59 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_60 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_61 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_62 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_63 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_64 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_65 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_66 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_67 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_68 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_69 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_70 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_71 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_72 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_73 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_74 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_75 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_76 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_77 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_78 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_79 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_80 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_81 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_82 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_83 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_84 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_85 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_86 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_87 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_88 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_89 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_90 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_91 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_92 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_93 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_94 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_95 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_96 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_97 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_98 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_99 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_100 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_101 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_102 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_103 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_104 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_105 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_106 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_107 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_108 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_109 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_110 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_111 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_112 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_113 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_114 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_115 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_116 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_117 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_118 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_119 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_120 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_121 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_122 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_123 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_124 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_125 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_126 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_127 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_128 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_129 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_130 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_131 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_132 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_133 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_134 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_135 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_136 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_137 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_138 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_139 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_140 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_141 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_142 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_143 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_144 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_145 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_146 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_147 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_148 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_149 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_150 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_151 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_152 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_153 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_154 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_155 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_156 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_157 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_158 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_159 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_160 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_161 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_162 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_163 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_164 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_165 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_166 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_167 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_168 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_169 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_170 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_171 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_172 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_173 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_174 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_175 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_176 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_177 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_178 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_179 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_180 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_181 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_182 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_183 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_184 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_185 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_186 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_187 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_188 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_189 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_190 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_191 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_192 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_193 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_194 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_195 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_196 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_197 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_198 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_199 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_200 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_201 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_202 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_203 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_204 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_205 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_206 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_207 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_208 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_209 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_210 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_211 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_212 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_213 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_214 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_215 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_216 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_217 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_218 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_219 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_220 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_221 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_222 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_223 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_224 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_225 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_226 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_227 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_228 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_229 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_230 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_231 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_232 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_233 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_234 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_235 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_236 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_237 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_238 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_239 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_240 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_241 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_242 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_243 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_244 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_245 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_246 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_247 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_248 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_249 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_250 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_251 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_252 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_253 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_254 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_255 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_256 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_257 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_258 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_259 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_260 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_261 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_262 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_263 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_264 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_265 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_266 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_267 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_268 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_269 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_270 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_271 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_272 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_273 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_274 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_275 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_276 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_277 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_278 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_279 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_280 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_281 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_282 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_283 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_284 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_285 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_286 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_287 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_288 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_289 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_290 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_291 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_292 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_293 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_294 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_295 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_296 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_297 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_298 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_299 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_300 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_301 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_302 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_303 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_304 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_305 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_306 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_307 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_308 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_309 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_310 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_311 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_312 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_313 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_314 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_315 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_316 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_317 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_318 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_319 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_320 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_321 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_322 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_323 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_324 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_325 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_326 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_327 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_328 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_329 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_330 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_331 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_332 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_333 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_334 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_335 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_336 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_337 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_338 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_339 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_340 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_341 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_342 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_343 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_344 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_345 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_346 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_347 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_348 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_349 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_350 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_351 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_352 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_353 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_354 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_355 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_356 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_357 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_358 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_359 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_360 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_361 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_362 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_363 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_364 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_365 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_366 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_367 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_368 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_369 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_370 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_371 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_372 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_373 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_374 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_375 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_376 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_377 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_378 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_379 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_380 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_381 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_382 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_383 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_384 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_385 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_386 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_387 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_388 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_389 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_390 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_391 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_392 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_393 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_394 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_395 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_396 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_397 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_398 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_399 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_400 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_401 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_402 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_403 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_404 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_405 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_406 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_407 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_408 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_409 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_410 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_411 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_412 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_413 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_414 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_415 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_416 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_417 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_418 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_419 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_420 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_421 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_422 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_423 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_424 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_425 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_426 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_427 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_428 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_429 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_430 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_431 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_432 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_433 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_434 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_435 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_436 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_437 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_438 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_439 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_440 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_441 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_442 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_443 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_444 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_445 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_446 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_447 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_448 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_449 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_450 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_451 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_452 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_453 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_454 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_455 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_456 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_457 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_458 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_459 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_460 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_461 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_462 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_463 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_464 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_465 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_466 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_467 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_468 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_469 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_470 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_471 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_472 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_473 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_474 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_475 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_476 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_477 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_478 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_479 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_480 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_481 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_482 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_483 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_484 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_485 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_486 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_487 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_488 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_489 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_490 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_491 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_492 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_493 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_494 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_495 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_496 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_497 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_498 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_499 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_500 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_501 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_502 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_503 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_504 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_505 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_506 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_507 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_508 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_509 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_510 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 - state_vec_511 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + if (reset) begin // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + state_vec_0 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_1 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_2 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_3 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_4 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_5 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_6 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_7 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_8 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_9 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_10 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_11 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_12 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_13 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_14 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_15 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_16 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_17 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_18 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_19 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_20 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_21 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_22 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_23 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_24 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_25 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_26 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_27 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_28 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_29 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_30 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_31 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_32 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_33 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_34 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_35 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_36 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_37 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_38 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_39 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_40 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_41 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_42 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_43 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_44 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_45 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_46 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_47 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_48 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_49 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_50 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_51 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_52 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_53 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_54 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_55 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_56 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_57 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_58 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_59 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_60 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_61 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_62 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_63 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_64 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_65 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_66 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_67 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_68 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_69 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_70 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_71 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_72 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_73 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_74 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_75 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_76 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_77 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_78 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_79 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_80 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_81 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_82 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_83 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_84 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_85 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_86 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_87 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_88 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_89 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_90 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_91 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_92 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_93 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_94 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_95 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_96 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_97 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_98 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_99 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_100 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_101 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_102 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_103 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_104 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_105 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_106 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_107 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_108 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_109 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_110 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_111 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_112 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_113 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_114 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_115 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_116 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_117 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_118 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_119 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_120 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_121 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_122 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_123 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_124 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_125 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_126 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_127 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_128 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_129 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_130 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_131 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_132 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_133 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_134 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_135 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_136 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_137 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_138 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_139 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_140 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_141 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_142 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_143 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_144 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_145 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_146 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_147 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_148 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_149 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_150 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_151 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_152 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_153 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_154 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_155 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_156 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_157 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_158 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_159 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_160 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_161 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_162 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_163 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_164 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_165 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_166 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_167 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_168 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_169 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_170 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_171 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_172 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_173 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_174 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_175 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_176 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_177 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_178 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_179 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_180 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_181 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_182 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_183 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_184 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_185 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_186 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_187 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_188 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_189 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_190 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_191 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_192 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_193 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_194 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_195 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_196 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_197 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_198 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_199 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_200 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_201 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_202 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_203 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_204 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_205 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_206 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_207 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_208 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_209 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_210 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_211 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_212 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_213 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_214 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_215 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_216 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_217 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_218 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_219 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_220 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_221 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_222 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_223 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_224 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_225 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_226 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_227 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_228 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_229 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_230 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_231 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_232 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_233 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_234 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_235 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_236 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_237 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_238 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_239 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_240 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_241 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_242 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_243 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_244 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_245 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_246 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_247 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_248 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_249 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_250 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_251 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_252 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_253 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_254 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_255 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_256 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_257 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_258 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_259 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_260 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_261 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_262 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_263 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_264 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_265 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_266 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_267 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_268 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_269 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_270 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_271 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_272 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_273 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_274 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_275 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_276 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_277 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_278 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_279 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_280 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_281 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_282 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_283 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_284 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_285 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_286 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_287 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_288 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_289 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_290 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_291 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_292 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_293 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_294 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_295 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_296 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_297 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_298 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_299 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_300 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_301 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_302 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_303 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_304 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_305 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_306 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_307 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_308 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_309 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_310 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_311 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_312 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_313 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_314 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_315 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_316 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_317 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_318 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_319 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_320 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_321 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_322 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_323 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_324 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_325 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_326 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_327 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_328 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_329 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_330 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_331 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_332 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_333 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_334 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_335 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_336 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_337 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_338 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_339 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_340 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_341 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_342 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_343 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_344 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_345 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_346 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_347 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_348 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_349 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_350 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_351 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_352 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_353 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_354 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_355 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_356 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_357 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_358 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_359 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_360 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_361 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_362 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_363 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_364 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_365 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_366 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_367 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_368 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_369 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_370 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_371 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_372 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_373 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_374 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_375 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_376 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_377 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_378 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_379 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_380 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_381 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_382 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_383 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_384 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_385 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_386 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_387 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_388 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_389 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_390 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_391 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_392 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_393 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_394 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_395 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_396 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_397 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_398 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_399 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_400 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_401 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_402 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_403 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_404 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_405 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_406 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_407 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_408 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_409 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_410 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_411 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_412 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_413 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_414 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_415 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_416 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_417 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_418 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_419 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_420 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_421 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_422 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_423 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_424 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_425 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_426 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_427 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_428 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_429 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_430 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_431 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_432 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_433 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_434 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_435 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_436 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_437 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_438 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_439 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_440 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_441 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_442 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_443 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_444 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_445 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_446 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_447 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_448 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_449 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_450 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_451 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_452 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_453 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_454 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_455 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_456 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_457 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_458 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_459 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_460 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_461 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_462 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_463 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_464 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_465 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_466 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_467 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_468 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_469 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_470 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_471 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_472 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_473 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_474 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_475 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_476 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_477 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_478 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_479 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_480 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_481 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_482 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_483 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_484 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_485 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_486 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_487 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_488 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_489 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_490 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_491 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_492 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_493 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_494 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_495 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_496 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_497 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_498 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_499 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_500 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_501 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_502 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_503 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_504 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_505 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_506 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_507 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_508 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_509 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_510 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] + state_vec_511 = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_9 ftb ( // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + SRAMTemplate_13 ftb ( // @[src/main/scala/xiangshan/frontend/FTB.scala:312:21] .clock (clock), .reset (reset), .io_r_req_ready (io_req_pc_ready), .io_r_req_valid - (io_req_pc_valid | io_u_req_pc_valid), // src/main/scala/xiangshan/frontend/FTB.scala:316:43 + (io_req_pc_valid | io_u_req_pc_valid), // @[src/main/scala/xiangshan/frontend/FTB.scala:316:43] .io_r_req_bits_setIdx - (io_u_req_pc_valid ? io_u_req_pc_bits[9:1] : io_req_pc_bits[9:1]), // src/main/scala/xiangshan/frontend/FTB.scala:317:36, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + (io_u_req_pc_valid ? io_u_req_pc_bits[9:1] : io_req_pc_bits[9:1]), // @[src/main/scala/xiangshan/frontend/FTB.scala:317:36, src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] .io_r_resp_data_0_entry_valid (_ftb_io_r_resp_data_0_entry_valid), .io_r_resp_data_0_entry_brSlots_0_offset (_ftb_io_r_resp_data_0_entry_brSlots_0_offset), @@ -7944,7 +5895,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 (_ftb_io_r_resp_data_3_entry_always_taken_1), .io_r_resp_data_3_tag (_ftb_io_r_resp_data_3_tag), .io_w_req_valid (io_update_write_data_valid), - .io_w_req_bits_setIdx (io_update_pc[9:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_w_req_bits_setIdx (io_update_pc[9:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] .io_w_req_bits_data_0_entry_valid (io_update_write_data_bits_entry_valid), .io_w_req_bits_data_0_entry_brSlots_0_offset @@ -8101,11 +6052,11 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 .io_w_req_bits_data_3_entry_always_taken_1 (io_update_write_data_bits_entry_always_taken_1), .io_w_req_bits_data_3_tag (io_update_write_data_bits_tag), - .io_w_req_bits_waymask (4'h1 << write_way_bits) // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FTB.scala:402:20 + .io_w_req_bits_waymask (4'h1 << u_way) // @[src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FTB.scala:402:20] ); assign io_read_resp_valid = total_hits_0 & pred_rdata_0_entry_valid | total_hits_1 & pred_rdata_1_entry_valid - | total_hits_2 & pred_rdata_2_entry_valid | total_hits_3 & pred_rdata_3_entry_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :332:107, utility/src/main/scala/utility/Hold.scala:25:8 + | total_hits_2 & pred_rdata_2_entry_valid | total_hits_3 & pred_rdata_3_entry_valid; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :332:107, utility/src/main/scala/utility/Hold.scala:25:8] assign io_read_resp_brSlots_0_offset = (total_hits_0 ? (pred_rdata_REG @@ -8126,7 +6077,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_brSlots_0_offset : pred_rdata_hold_data_3_entry_brSlots_0_offset) - : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_brSlots_0_lower = (total_hits_0 ? (pred_rdata_REG @@ -8147,7 +6098,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_brSlots_0_lower : pred_rdata_hold_data_3_entry_brSlots_0_lower) - : 12'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 12'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_brSlots_0_tarStat = (total_hits_0 ? (pred_rdata_REG @@ -8168,7 +6119,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat : pred_rdata_hold_data_3_entry_brSlots_0_tarStat) - : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_brSlots_0_sharing = total_hits_0 & (pred_rdata_REG @@ -8182,7 +6133,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_brSlots_0_sharing) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_brSlots_0_sharing - : pred_rdata_hold_data_3_entry_brSlots_0_sharing); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_brSlots_0_sharing); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_brSlots_0_valid = total_hits_0 & (pred_rdata_REG @@ -8196,7 +6147,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_brSlots_0_valid) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_brSlots_0_valid - : pred_rdata_hold_data_3_entry_brSlots_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_brSlots_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_tailSlot_offset = (total_hits_0 ? (pred_rdata_REG @@ -8217,7 +6168,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_tailSlot_offset : pred_rdata_hold_data_3_entry_tailSlot_offset) - : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_tailSlot_lower = (total_hits_0 ? (pred_rdata_REG @@ -8238,7 +6189,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_tailSlot_lower : pred_rdata_hold_data_3_entry_tailSlot_lower) - : 20'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 20'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_tailSlot_tarStat = (total_hits_0 ? (pred_rdata_REG @@ -8259,7 +6210,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_tailSlot_tarStat : pred_rdata_hold_data_3_entry_tailSlot_tarStat) - : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_tailSlot_sharing = total_hits_0 & (pred_rdata_REG @@ -8273,7 +6224,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_tailSlot_sharing) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_tailSlot_sharing - : pred_rdata_hold_data_3_entry_tailSlot_sharing); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_tailSlot_sharing); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_tailSlot_valid = total_hits_0 & (pred_rdata_REG @@ -8287,7 +6238,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_tailSlot_valid) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_tailSlot_valid - : pred_rdata_hold_data_3_entry_tailSlot_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_tailSlot_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_pftAddr = (total_hits_0 ? (pred_rdata_REG @@ -8308,7 +6259,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 ? (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_pftAddr : pred_rdata_hold_data_3_entry_pftAddr) - : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_carry = total_hits_0 & (pred_rdata_REG @@ -8322,7 +6273,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_carry) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_carry - : pred_rdata_hold_data_3_entry_carry); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_carry); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_isCall = total_hits_0 & (pred_rdata_REG @@ -8336,7 +6287,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_isCall) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_isCall - : pred_rdata_hold_data_3_entry_isCall); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_isCall); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_isRet = total_hits_0 & (pred_rdata_REG @@ -8350,7 +6301,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_isRet) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_isRet - : pred_rdata_hold_data_3_entry_isRet); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_isRet); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_isJalr = total_hits_0 & (pred_rdata_REG @@ -8364,7 +6315,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_isJalr) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_isJalr - : pred_rdata_hold_data_3_entry_isJalr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_isJalr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_last_may_be_rvi_call = total_hits_0 & (pred_rdata_REG @@ -8378,7 +6329,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_last_may_be_rvi_call) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call - : pred_rdata_hold_data_3_entry_last_may_be_rvi_call); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_last_may_be_rvi_call); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_always_taken_0 = total_hits_0 & (pred_rdata_REG @@ -8392,7 +6343,7 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_always_taken_0) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_always_taken_0 - : pred_rdata_hold_data_3_entry_always_taken_0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + : pred_rdata_hold_data_3_entry_always_taken_0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] assign io_read_resp_always_taken_1 = total_hits_0 & (pred_rdata_REG @@ -8406,13 +6357,13 @@ module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 : pred_rdata_hold_data_2_entry_always_taken_1) | total_hits_3 & (pred_rdata_REG ? _ftb_io_r_resp_data_3_entry_always_taken_1 - : pred_rdata_hold_data_3_entry_always_taken_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 - assign io_read_hits_valid = read_way_valid; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :333:34 - assign io_read_hits_bits = read_way_bits; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + : pred_rdata_hold_data_3_entry_always_taken_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8] + assign io_read_hits_valid = hit; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :333:34] + assign io_read_hits_bits = hit_way; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:290:9] assign io_update_hits_valid = _ftb_io_r_resp_data_0_tag == u_req_tag & _ftb_io_r_resp_data_0_entry_valid - & u_total_hits_REG | u_total_hits_1 | u_total_hits_2 | u_total_hits_3; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :327:30, :338:{35,86,96}, :339:38 + & u_total_hits_REG | u_total_hits_1 | u_total_hits_2 | u_total_hits_3; // @[src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :327:30, :338:{35,86,96}, :339:38] assign io_update_hits_bits = - {|{u_total_hits_3, u_total_hits_2}, u_total_hits_3 | u_total_hits_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :338:86 + {|{u_total_hits_3, u_total_hits_2}, u_total_hits_3 | u_total_hits_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :338:86] endmodule diff --git a/rtl/FTB/FTBEntryGen.sv b/rtl/FTB/FTBEntryGen.sv index 616bf32..055a12d 100644 --- a/rtl/FTB/FTBEntryGen.sv +++ b/rtl/FTB/FTBEntryGen.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,111 +55,111 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 - input [38:0] io_start_addr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [3:0] io_old_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [11:0] io_old_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [1:0] io_old_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [3:0] io_old_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [19:0] io_old_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [1:0] io_old_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [3:0] io_old_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_old_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_brMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_jmpInfo_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_jmpInfo_bits_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_jmpInfo_bits_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_jmpInfo_bits_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [3:0] io_pd_jmpOffset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [38:0] io_pd_jalTarget, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_pd_rvcMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_cfiIndex_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [3:0] io_cfiIndex_bits, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input [38:0] io_target, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_hit, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - input io_mispredict_vec_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [3:0] io_new_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [11:0] io_new_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [1:0] io_new_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [3:0] io_new_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [19:0] io_new_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [1:0] io_new_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output [3:0] io_new_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_new_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_taken_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_taken_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_jmp_taken, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_mispred_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_mispred_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_mispred_mask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 - output io_is_old_entry // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 +module FTBEntryGen( // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7] + input [40:0] io_start_addr, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [3:0] io_old_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [11:0] io_old_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [1:0] io_old_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [3:0] io_old_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [19:0] io_old_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [1:0] io_old_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [3:0] io_old_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_carry, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_isCall, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_isRet, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_isJalr, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_old_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_2, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_3, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_4, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_5, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_6, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_7, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_8, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_9, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_10, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_11, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_12, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_13, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_14, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_brMask_15, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_jmpInfo_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_jmpInfo_bits_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_jmpInfo_bits_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_jmpInfo_bits_2, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [3:0] io_pd_jmpOffset, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [40:0] io_pd_jalTarget, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_2, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_3, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_4, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_5, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_6, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_7, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_8, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_9, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_10, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_11, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_12, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_13, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_14, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_pd_rvcMask_15, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_cfiIndex_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [3:0] io_cfiIndex_bits, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input [40:0] io_target, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_hit, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_2, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_3, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_4, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_5, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_6, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_7, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_8, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_9, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_10, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_11, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_12, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_13, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_14, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + input io_mispredict_vec_15, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [3:0] io_new_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [11:0] io_new_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [1:0] io_new_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [3:0] io_new_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [19:0] io_new_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [1:0] io_new_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output [3:0] io_new_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_carry, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_isCall, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_isRet, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_isJalr, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_new_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_taken_mask_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_taken_mask_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_jmp_taken, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_mispred_mask_0, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_mispred_mask_1, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_mispred_mask_2, // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] + output io_is_old_entry // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14] ); wire [15:0] _GEN = @@ -178,14 +178,14 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 {io_pd_brMask_3}, {io_pd_brMask_2}, {io_pd_brMask_1}, - {io_pd_brMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47 - wire init_entry_always_taken_0 = _GEN[io_cfiIndex_bits] & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47 + {io_pd_brMask_0}}; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:256:47] + wire cfi_is_br = _GEN[io_cfiIndex_bits] & io_cfiIndex_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:256:47] wire init_entry_isJalr = - io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_0 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62 - wire last_jmp_rvi = io_pd_jmpInfo_valid & (&io_pd_jmpOffset) & ~io_pd_rvcMask_15; // src/main/scala/xiangshan/frontend/NewFtq.scala:259:{52,75,78} - wire cfi_is_jalr = io_cfiIndex_bits == io_pd_jmpOffset & init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62, :262:37, :263:55 - wire [37:0] _GEN_0 = cfi_is_jalr ? io_target[38:1] : io_pd_jalTarget[38:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14, :263:55, :284:64 - wire [4:0] _GEN_1 = {1'h0, io_start_addr[4:1]}; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :266:30, :287:40 + io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_0 & io_cfiIndex_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:259:62] + wire last_jmp_rvi = io_pd_jmpInfo_valid & (&io_pd_jmpOffset) & ~io_pd_rvcMask_15; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:262:{52,75,78}] + wire cfi_is_jalr = io_cfiIndex_bits == io_pd_jmpOffset & init_entry_isJalr; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:259:62, :265:37, :266:55] + wire [39:0] _GEN_0 = cfi_is_jalr ? io_target[40:1] : io_pd_jalTarget[40:1]; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:225:14, :266:55, :287:64] + wire [4:0] _GEN_1 = {1'h0, io_start_addr[4:1]}; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :269:30, :290:40] wire [15:0] _GEN_2 = {{io_pd_rvcMask_15}, {io_pd_rvcMask_14}, @@ -202,77 +202,77 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 {io_pd_rvcMask_3}, {io_pd_rvcMask_2}, {io_pd_rvcMask_1}, - {io_pd_rvcMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:287:62 + {io_pd_rvcMask_0}}; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:290:62] wire [4:0] jmpPft = 5'(_GEN_1 - + 5'({1'h0, io_pd_jmpOffset} + {3'h0, _GEN_2[io_pd_jmpOffset] ? 2'h1 : 2'h2})); // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :61:12, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:{40,56,62} + + 5'({1'h0, io_pd_jmpOffset} + {3'h0, _GEN_2[io_pd_jmpOffset] ? 2'h1 : 2'h2})); // @[src/main/scala/xiangshan/frontend/FTB.scala:60:10, :61:12, src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :290:{40,56,62}] wire is_new_br = - init_entry_always_taken_0 + cfi_is_br & {io_old_entry_tailSlot_valid & io_old_entry_tailSlot_offset == io_cfiIndex_bits & io_old_entry_tailSlot_sharing, io_old_entry_brSlots_0_valid - & io_old_entry_brSlots_0_offset == io_cfiIndex_bits} == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:194:{32,44}, :195:{42,53}, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :253:47, :299:{37,44}, :300:29 + & io_old_entry_brSlots_0_offset == io_cfiIndex_bits} == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:194:{32,44}, :195:{42,53}, src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :256:47, :302:{37,44}, :303:29] wire new_br_insert_onehot_0 = - ~io_old_entry_brSlots_0_valid | io_cfiIndex_bits < io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:307:{9,33,50} + ~io_old_entry_brSlots_0_valid | io_cfiIndex_bits < io_old_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:310:{9,33,50}] wire _new_br_insert_onehot_T_3 = - io_cfiIndex_bits > io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:309:53 + io_cfiIndex_bits > io_old_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:312:53] wire new_br_insert_onehot_1 = io_old_entry_brSlots_0_valid & _new_br_insert_onehot_T_3 - & (~io_old_entry_tailSlot_valid | io_cfiIndex_bits < io_old_entry_tailSlot_offset); // src/main/scala/xiangshan/frontend/NewFtq.scala:309:{53,83}, :310:{10,36,53} - wire _GEN_3 = io_cfiIndex_bits > io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:322:31 - wire _GEN_4 = _GEN_3 | ~io_old_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:314:36, :322:{31,61}, :329:44 + & (~io_old_entry_tailSlot_valid | io_cfiIndex_bits < io_old_entry_tailSlot_offset); // @[src/main/scala/xiangshan/frontend/NewFtq.scala:312:{53,83}, :313:{10,36,53}] + wire _GEN_3 = io_cfiIndex_bits > io_old_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:325:31] + wire _GEN_4 = _GEN_3 | ~io_old_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:317:36, :325:{31,61}, :332:44] wire pft_need_to_change = - is_new_br & io_old_entry_brSlots_0_valid & io_old_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38 + is_new_br & io_old_entry_brSlots_0_valid & io_old_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:303:29, :345:38] wire [3:0] new_pft_offset = {new_br_insert_onehot_1, new_br_insert_onehot_0} == 2'h0 ? io_cfiIndex_bits - : io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :307:33, :309:83, :346:{10,33,40} - wire [4:0] _old_entry_modified_carry_T_1 = 5'(_GEN_1 + {1'h0, new_pft_offset}); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:40, :346:10, :350:59, :351:58 - wire _old_target_target_T_9 = io_old_entry_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :98:19 - wire _old_target_target_T_10 = io_old_entry_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:61:12, :99:19 - wire _old_target_target_T_11 = io_old_entry_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41 + : io_old_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :310:33, :312:83, :349:{10,33,40}] + wire [4:0] _old_entry_modified_carry_T_1 = 5'(_GEN_1 + {1'h0, new_pft_offset}); // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :290:40, :349:10, :353:59, :354:58] + wire _old_target_target_T_9 = io_old_entry_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:60:10, :98:19] + wire _old_target_target_T_10 = io_old_entry_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:61:12, :99:19] + wire _old_target_target_T_11 = io_old_entry_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/NewFtq.scala:253:41] wire jalr_target_modified = cfi_is_jalr & {io_old_entry_tailSlot_sharing - ? {(_old_target_target_T_9 ? 26'(io_start_addr[38:13] + 26'h1) : 26'h0) - | (_old_target_target_T_10 ? 26'(io_start_addr[38:13] - 26'h1) : 26'h0) - | (_old_target_target_T_11 ? io_start_addr[38:13] : 26'h0), + ? {(_old_target_target_T_9 ? 28'(io_start_addr[40:13] + 28'h1) : 28'h0) + | (_old_target_target_T_10 ? 28'(io_start_addr[40:13] - 28'h1) : 28'h0) + | (_old_target_target_T_11 ? io_start_addr[40:13] : 28'h0), io_old_entry_tailSlot_lower[11:0]} - : {(_old_target_target_T_9 ? 18'(io_start_addr[38:21] + 18'h1) : 18'h0) - | (_old_target_target_T_10 ? 18'(io_start_addr[38:21] - 18'h1) : 18'h0) - | (_old_target_target_T_11 ? io_start_addr[38:21] : 18'h0), + : {(_old_target_target_T_9 ? 20'(io_start_addr[40:21] + 20'h1) : 20'h0) + | (_old_target_target_T_10 ? 20'(io_start_addr[40:21] - 20'h1) : 20'h0) + | (_old_target_target_T_11 ? io_start_addr[40:21] : 20'h0), io_old_entry_tailSlot_lower}, - 1'h0} != io_target & ~io_old_entry_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :263:55, :360:25, :361:{57,72} + 1'h0} != io_target & ~io_old_entry_tailSlot_sharing; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/NewFtq.scala:253:41, :266:55, :363:25, :364:{57,72}] wire old_entry_always_taken_always_taken_0 = io_old_entry_always_taken_0 & io_cfiIndex_valid & io_old_entry_brSlots_0_valid - & io_cfiIndex_bits == io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85} + & io_cfiIndex_bits == io_old_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:374:{65,85}] wire old_entry_always_taken_always_taken_1 = io_old_entry_always_taken_1 & io_cfiIndex_valid & io_old_entry_tailSlot_valid - & io_old_entry_tailSlot_sharing & io_cfiIndex_bits == io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85} - wire _GEN_5 = is_new_br & new_br_insert_onehot_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :307:33, :379:8 - wire _GEN_6 = is_new_br & pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38, :379:8 - wire _GEN_7 = ~is_new_br | ~pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :314:36, :342:38, :344:29, :352:45, :379:8 - wire [3:0] _io_new_entry_brSlots_0_offset_output = + & io_old_entry_tailSlot_sharing & io_cfiIndex_bits == io_old_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:374:{65,85}] + wire _GEN_5 = is_new_br & new_br_insert_onehot_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:303:29, :310:33, :382:8] + wire _GEN_6 = is_new_br & pft_need_to_change; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:303:29, :345:38, :382:8] + wire _GEN_7 = ~is_new_br | ~pft_need_to_change; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:303:29, :317:36, :345:38, :347:29, :355:45, :382:8] + wire [3:0] io_new_entry_brSlots_0_offset_0 = io_hit ? (_GEN_5 ? io_cfiIndex_bits : io_old_entry_brSlots_0_offset) - : init_entry_always_taken_0 ? io_cfiIndex_bits : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :253:47, :273:20, :275:25, :379:8, :383:22 - wire _io_new_entry_brSlots_0_valid_output = - io_hit ? _GEN_5 | io_old_entry_brSlots_0_valid : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47, :379:8, :383:22 - wire [3:0] _io_new_entry_tailSlot_offset_output = + : cfi_is_br ? io_cfiIndex_bits : 4'h0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:{28,41}, :256:47, :276:20, :278:25, :382:8, :386:22] + wire io_new_entry_brSlots_0_valid_0 = + io_hit ? _GEN_5 | io_old_entry_brSlots_0_valid : cfi_is_br; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:256:47, :382:8, :386:22] + wire [3:0] io_new_entry_tailSlot_offset_0 = io_hit ? (is_new_br ? (new_br_insert_onehot_1 ? io_cfiIndex_bits : _GEN_4 ? io_old_entry_tailSlot_offset : io_old_entry_brSlots_0_offset) : io_old_entry_tailSlot_offset) - : io_pd_jmpInfo_valid ? io_pd_jmpOffset : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :281:24, :282:32, :300:29, :309:83, :314:36, :317:36, :319:19, :322:61, :329:44, :379:8, :383:22 - wire _io_new_entry_tailSlot_sharing_output = + : io_pd_jmpInfo_valid ? io_pd_jmpOffset : 4'h0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:{28,41}, :284:24, :285:32, :303:29, :312:83, :317:36, :320:36, :322:19, :325:61, :332:44, :382:8, :386:22] + wire io_new_entry_tailSlot_sharing_0 = io_hit & (is_new_br ? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_brSlots_0_valid | io_old_entry_tailSlot_sharing - : ~jalr_target_modified & io_old_entry_tailSlot_sharing); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :309:83, :314:36, :317:36, :322:{31,61}, :329:44, :358:47, :361:72, :362:31, :379:8, :380:10, :383:22 - wire _io_new_entry_tailSlot_valid_output = + : ~jalr_target_modified & io_old_entry_tailSlot_sharing); // @[src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:303:29, :312:83, :317:36, :320:36, :325:{31,61}, :332:44, :361:47, :364:72, :365:31, :382:8, :383:10, :386:22] + wire io_new_entry_tailSlot_valid_0 = io_hit ? (is_new_br ? new_br_insert_onehot_1 @@ -280,9 +280,9 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 : io_old_entry_tailSlot_valid) : io_pd_jmpInfo_valid & (io_pd_jmpInfo_valid & ~io_pd_jmpInfo_bits_0 & io_cfiIndex_valid - | init_entry_isJalr); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:28, :255:{42,62}, :256:62, :281:24, :283:{31,49}, :300:29, :309:83, :314:36, :317:36, :318:18, :322:61, :329:44, :379:8, :383:22 - wire _io_mispred_mask_1_WIRE_1 = - _io_new_entry_tailSlot_valid_output & _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:383:22 + | init_entry_isJalr); // @[src/main/scala/xiangshan/frontend/NewFtq.scala:253:28, :258:{42,62}, :259:62, :284:24, :286:{31,49}, :303:29, :312:83, :317:36, :320:36, :321:18, :325:61, :332:44, :382:8, :386:22] + wire _io_mispred_mask_1_T = + io_new_entry_tailSlot_valid_0 & io_new_entry_tailSlot_sharing_0; // @[src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:386:22] wire [15:0] _GEN_8 = {{io_mispredict_vec_15}, {io_mispredict_vec_14}, @@ -299,29 +299,29 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 {io_mispredict_vec_3}, {io_mispredict_vec_2}, {io_mispredict_vec_1}, - {io_mispredict_vec_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:391:52 - assign io_new_entry_valid = ~io_hit | io_old_entry_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:{22,23} - assign io_new_entry_brSlots_0_offset = _io_new_entry_brSlots_0_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + {io_mispredict_vec_0}}; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:394:52] + assign io_new_entry_valid = ~io_hit | io_old_entry_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:{22,23}] + assign io_new_entry_brSlots_0_offset = io_new_entry_brSlots_0_offset_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22] assign io_new_entry_brSlots_0_lower = io_hit ? (_GEN_5 ? io_target[12:1] : io_old_entry_brSlots_0_lower) - : init_entry_always_taken_0 ? io_target[12:1] : 12'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22 + : cfi_is_br ? io_target[12:1] : 12'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :253:{28,41}, :256:47, :276:20, :382:8, :386:22] assign io_new_entry_brSlots_0_tarStat = io_hit ? (_GEN_5 - ? (io_target[38:13] > io_start_addr[38:13] + ? (io_target[40:13] > io_start_addr[40:13] ? 2'h1 - : {io_target[38:13] < io_start_addr[38:13], 1'h0}) + : {io_target[40:13] < io_start_addr[40:13], 1'h0}) : io_old_entry_brSlots_0_tarStat) - : init_entry_always_taken_0 - ? (io_target[38:13] > io_start_addr[38:13] + : cfi_is_br + ? (io_target[40:13] > io_start_addr[40:13] ? 2'h1 - : {io_target[38:13] < io_start_addr[38:13], 1'h0}) - : 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22 + : {io_target[40:13] < io_start_addr[40:13], 1'h0}) + : 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :253:{28,41}, :256:47, :276:20, :382:8, :386:22] assign io_new_entry_brSlots_0_sharing = - io_hit & (~is_new_br | ~new_br_insert_onehot_0) & io_old_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :307:33, :314:36, :317:36, :379:8, :383:22 - assign io_new_entry_brSlots_0_valid = _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 - assign io_new_entry_tailSlot_offset = _io_new_entry_tailSlot_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + io_hit & (~is_new_br | ~new_br_insert_onehot_0) & io_old_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :303:29, :310:33, :317:36, :320:36, :382:8, :386:22] + assign io_new_entry_brSlots_0_valid = io_new_entry_brSlots_0_valid_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22] + assign io_new_entry_tailSlot_offset = io_new_entry_tailSlot_offset_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22] assign io_new_entry_tailSlot_lower = io_hit ? (is_new_br @@ -331,48 +331,48 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 ? io_old_entry_tailSlot_lower : {8'h0, io_old_entry_brSlots_0_lower}) : jalr_target_modified ? io_target[20:1] : io_old_entry_tailSlot_lower) - : io_pd_jmpInfo_valid ? _GEN_0[19:0] : 20'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22, utility/src/main/scala/utility/BitUtils.scala:88:41 + : io_pd_jmpInfo_valid ? _GEN_0[19:0] : 20'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :253:{28,41}, :284:24, :287:64, :303:29, :312:83, :317:36, :320:36, :325:61, :332:44, :364:72, :382:8, :383:10, :386:22, utility/src/main/scala/utility/BitUtils.scala:88:41] assign io_new_entry_tailSlot_tarStat = io_hit ? (is_new_br ? (new_br_insert_onehot_1 - ? (io_target[38:13] > io_start_addr[38:13] + ? (io_target[40:13] > io_start_addr[40:13] ? 2'h1 - : {io_target[38:13] < io_start_addr[38:13], 1'h0}) + : {io_target[40:13] < io_start_addr[40:13], 1'h0}) : _GEN_4 ? io_old_entry_tailSlot_tarStat : io_old_entry_brSlots_0_tarStat) : jalr_target_modified - ? (io_target[38:21] > io_start_addr[38:21] + ? (io_target[40:21] > io_start_addr[40:21] ? 2'h1 - : {io_target[38:21] < io_start_addr[38:21], 1'h0}) + : {io_target[40:21] < io_start_addr[40:21], 1'h0}) : io_old_entry_tailSlot_tarStat) : io_pd_jmpInfo_valid - ? (_GEN_0[37:20] > io_start_addr[38:21] + ? (_GEN_0[39:20] > io_start_addr[40:21] ? 2'h1 - : {_GEN_0[37:20] < io_start_addr[38:21], 1'h0}) - : 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, :76:32, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22 - assign io_new_entry_tailSlot_sharing = _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 - assign io_new_entry_tailSlot_valid = _io_new_entry_tailSlot_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + : {_GEN_0[39:20] < io_start_addr[40:21], 1'h0}) + : 2'h0; // @[src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, :76:32, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :253:{28,41}, :284:24, :287:64, :303:29, :312:83, :317:36, :320:36, :325:61, :332:44, :364:72, :382:8, :383:10, :386:22] + assign io_new_entry_tailSlot_sharing = io_new_entry_tailSlot_sharing_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22] + assign io_new_entry_tailSlot_valid = io_new_entry_tailSlot_valid_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22] assign io_new_entry_pftAddr = io_hit ? (_GEN_6 ? 4'(io_start_addr[4:1] + new_pft_offset) : io_old_entry_pftAddr) - : io_pd_jmpInfo_valid & ~last_jmp_rvi ? jmpPft[3:0] : io_start_addr[4:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :266:30, :287:56, :288:{28,43,46}, :346:10, :350:59, :379:8, :383:22 + : io_pd_jmpInfo_valid & ~last_jmp_rvi ? jmpPft[3:0] : io_start_addr[4:1]; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :262:75, :269:30, :290:56, :291:{28,43,46}, :349:10, :353:59, :382:8, :386:22] assign io_new_entry_carry = io_hit ? (_GEN_6 ? _old_entry_modified_carry_T_1[4] : io_old_entry_carry) - : ~(io_pd_jmpInfo_valid & ~last_jmp_rvi) | jmpPft[4]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :287:56, :288:46, :289:{28,43,67}, :351:{58,81}, :379:8, :383:22 + : ~(io_pd_jmpInfo_valid & ~last_jmp_rvi) | jmpPft[4]; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :262:75, :290:56, :291:46, :292:{28,43,67}, :354:{58,81}, :382:8, :386:22] assign io_new_entry_isCall = io_hit ? _GEN_7 & io_old_entry_isCall - : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_1 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :257:62, :379:8, :383:22 + : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_1 & io_cfiIndex_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :260:62, :382:8, :386:22] assign io_new_entry_isRet = io_hit ? _GEN_7 & io_old_entry_isRet - : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_2 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :258:62, :379:8, :383:22 - assign io_new_entry_isJalr = io_hit ? _GEN_7 & io_old_entry_isJalr : init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :256:62, :379:8, :383:22 + : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_2 & io_cfiIndex_valid; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :261:62, :382:8, :386:22] + assign io_new_entry_isJalr = io_hit ? _GEN_7 & io_old_entry_isJalr : init_entry_isJalr; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :259:62, :382:8, :386:22] assign io_new_entry_last_may_be_rvi_call = io_hit ? _GEN_7 & io_old_entry_last_may_be_rvi_call - : (&io_pd_jmpOffset) & ~_GEN_2[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:52, :287:62, :294:{74,77}, :379:8, :383:22 + : (&io_pd_jmpOffset) & ~_GEN_2[io_pd_jmpOffset]; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :262:52, :290:62, :297:{74,77}, :382:8, :386:22] assign io_new_entry_always_taken_0 = io_hit ? (is_new_br @@ -381,33 +381,33 @@ module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 : jalr_target_modified ? ~jalr_target_modified & io_old_entry_always_taken_0 : old_entry_always_taken_always_taken_0) - : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :253:47, :300:29, :307:33, :309:53, :314:36, :317:36, :321:42, :322:61, :323:42, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22 + : cfi_is_br; // @[src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :256:47, :303:29, :310:33, :312:53, :317:36, :320:36, :324:42, :325:61, :326:42, :361:47, :364:72, :365:31, :367:48, :374:65, :382:8, :383:10, :386:22] assign io_new_entry_always_taken_1 = io_hit & (is_new_br ? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_always_taken_1 : jalr_target_modified ? ~jalr_target_modified & io_old_entry_always_taken_1 - : old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :309:83, :314:36, :317:36, :321:42, :322:{31,61}, :323:42, :329:44, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22 + : old_entry_always_taken_always_taken_1); // @[src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :303:29, :312:83, :317:36, :320:36, :324:42, :325:{31,61}, :326:42, :332:44, :361:47, :364:72, :365:31, :367:48, :374:65, :382:8, :383:10, :386:22] assign io_taken_mask_0 = - io_cfiIndex_bits == _io_new_entry_brSlots_0_offset_output & io_cfiIndex_valid - & _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68} + io_cfiIndex_bits == io_new_entry_brSlots_0_offset_0 & io_cfiIndex_valid + & io_new_entry_brSlots_0_valid_0; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :390:{39,68}] assign io_taken_mask_1 = - io_cfiIndex_bits == _io_new_entry_tailSlot_offset_output & io_cfiIndex_valid - & _io_mispred_mask_1_WIRE_1; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68} + io_cfiIndex_bits == io_new_entry_tailSlot_offset_0 & io_cfiIndex_valid + & _io_mispred_mask_1_T; // @[src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :390:{39,68}] assign io_jmp_taken = - _io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output - & _io_new_entry_tailSlot_offset_output == io_cfiIndex_bits; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :389:{41,73} + io_new_entry_tailSlot_valid_0 & ~io_new_entry_tailSlot_sharing_0 + & io_new_entry_tailSlot_offset_0 == io_cfiIndex_bits; // @[src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :392:{41,73}] assign io_mispred_mask_0 = - _io_new_entry_brSlots_0_valid_output & _GEN_8[_io_new_entry_brSlots_0_offset_output]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52 + io_new_entry_brSlots_0_valid_0 & _GEN_8[io_new_entry_brSlots_0_offset_0]; // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :394:52] assign io_mispred_mask_1 = - _io_mispred_mask_1_WIRE_1 & _GEN_8[_io_new_entry_tailSlot_offset_output]; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52 + _io_mispred_mask_1_T & _GEN_8[io_new_entry_tailSlot_offset_0]; // @[src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :394:52] assign io_mispred_mask_2 = - _io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output - & _GEN_8[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52, :393:49 + io_new_entry_tailSlot_valid_0 & ~io_new_entry_tailSlot_sharing_0 + & _GEN_8[io_pd_jmpOffset]; // @[src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :386:22, :394:52, :396:49] assign io_is_old_entry = io_hit & ~is_new_br & ~jalr_target_modified & ~(io_old_entry_always_taken_0 & ~old_entry_always_taken_always_taken_0 - | io_old_entry_always_taken_1 & ~old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :361:72, :371:65, :372:{56,59}, :374:65, :397:{29,43,65,68} + | io_old_entry_always_taken_1 & ~old_entry_always_taken_always_taken_1); // @[src/main/scala/xiangshan/frontend/NewFtq.scala:224:7, :303:29, :364:72, :374:65, :375:{56,59}, :377:65, :400:{29,43,65,68}] endmodule diff --git a/rtl/FTB/SRAMTemplate_13.sv b/rtl/FTB/SRAMTemplate_13.sv new file mode 100644 index 0000000..fadd882 --- /dev/null +++ b/rtl/FTB/SRAMTemplate_13.sv @@ -0,0 +1,443 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_13( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_0_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_0_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_0_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_1_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_1_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_1_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_2_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_2_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_2_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_2_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_3_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_3_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [3:0] io_r_resp_data_3_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [19:0] io_r_resp_data_3_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_0_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_1_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_2_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_2_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_data_3_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [19:0] io_w_req_bits_data_3_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] +); + + wire [8:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19] + wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + wire [319:0] _array_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [8:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}] + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet <= 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 9'(_resetSet + 9'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_3 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19] + .RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38] + .RW0_clk (clock), + .RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + .RW0_wdata + ({~_resetState & io_w_req_bits_data_3_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr, + ~_resetState & io_w_req_bits_data_3_entry_carry, + ~_resetState & io_w_req_bits_data_3_entry_isCall, + ~_resetState & io_w_req_bits_data_3_entry_isRet, + ~_resetState & io_w_req_bits_data_3_entry_isJalr, + ~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_3_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_3_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_3_tag, + ~_resetState & io_w_req_bits_data_2_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr, + ~_resetState & io_w_req_bits_data_2_entry_carry, + ~_resetState & io_w_req_bits_data_2_entry_isCall, + ~_resetState & io_w_req_bits_data_2_entry_isRet, + ~_resetState & io_w_req_bits_data_2_entry_isJalr, + ~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_2_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_2_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_2_tag, + ~_resetState & io_w_req_bits_data_1_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr, + ~_resetState & io_w_req_bits_data_1_entry_carry, + ~_resetState & io_w_req_bits_data_1_entry_isCall, + ~_resetState & io_w_req_bits_data_1_entry_isRet, + ~_resetState & io_w_req_bits_data_1_entry_isJalr, + ~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_1_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_1_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_1_tag, + ~_resetState & io_w_req_bits_data_0_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr, + ~_resetState & io_w_req_bits_data_0_entry_carry, + ~_resetState & io_w_req_bits_data_0_entry_isCall, + ~_resetState & io_w_req_bits_data_0_entry_isRet, + ~_resetState & io_w_req_bits_data_0_entry_isJalr, + ~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_0_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_0_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_0_tag}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :175:{18,43}, :176:13] + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}] + ); + assign io_r_req_ready = ~_resetState & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :171:52, :172:41, :222:{21,33}] + assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] + assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45] +endmodule + diff --git a/rtl/FTB/SRAMTemplate_9.sv b/rtl/FTB/SRAMTemplate_9.sv deleted file mode 100644 index 9cc03e1..0000000 --- a/rtl/FTB/SRAMTemplate_9.sv +++ /dev/null @@ -1,659 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_9( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [3:0] io_r_resp_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [19:0] io_r_resp_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [19:0] io_w_req_bits_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 -); - - wire [19:0] _wdata_T_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [11:0] _wdata_T_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [11:0] _wdata_T_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [11:0] _wdata_T_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [19:0] _wdata_T_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [11:0] _wdata_T_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [3:0] _wdata_T_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 - wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 - wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - wire [319:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} - assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - assign _wdata_T_0_entry_valid = ~_resetState & io_w_req_bits_data_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_brSlots_0_offset = - _resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_brSlots_0_lower = - _resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_brSlots_0_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_brSlots_0_sharing = - ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_brSlots_0_valid = - ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_tailSlot_offset = - _resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_tailSlot_lower = - _resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_tailSlot_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_tailSlot_sharing = - ~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_tailSlot_valid = - ~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_pftAddr = - _resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_entry_carry = ~_resetState & io_w_req_bits_data_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_isCall = ~_resetState & io_w_req_bits_data_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_isRet = ~_resetState & io_w_req_bits_data_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_isJalr = ~_resetState & io_w_req_bits_data_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_last_may_be_rvi_call = - ~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_always_taken_0 = - ~_resetState & io_w_req_bits_data_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_entry_always_taken_1 = - ~_resetState & io_w_req_bits_data_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_0_tag = _resetState ? 20'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_valid = ~_resetState & io_w_req_bits_data_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_brSlots_0_offset = - _resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_brSlots_0_lower = - _resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_brSlots_0_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_brSlots_0_sharing = - ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_brSlots_0_valid = - ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_tailSlot_offset = - _resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_tailSlot_lower = - _resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_tailSlot_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_tailSlot_sharing = - ~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_tailSlot_valid = - ~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_pftAddr = - _resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_entry_carry = ~_resetState & io_w_req_bits_data_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_isCall = ~_resetState & io_w_req_bits_data_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_isRet = ~_resetState & io_w_req_bits_data_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_isJalr = ~_resetState & io_w_req_bits_data_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_last_may_be_rvi_call = - ~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_always_taken_0 = - ~_resetState & io_w_req_bits_data_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_entry_always_taken_1 = - ~_resetState & io_w_req_bits_data_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_1_tag = _resetState ? 20'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_valid = ~_resetState & io_w_req_bits_data_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_brSlots_0_offset = - _resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_brSlots_0_lower = - _resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_brSlots_0_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_brSlots_0_sharing = - ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_brSlots_0_valid = - ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_tailSlot_offset = - _resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_tailSlot_lower = - _resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_tailSlot_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_tailSlot_sharing = - ~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_tailSlot_valid = - ~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_pftAddr = - _resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_2_entry_carry = ~_resetState & io_w_req_bits_data_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_isCall = ~_resetState & io_w_req_bits_data_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_isRet = ~_resetState & io_w_req_bits_data_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_isJalr = ~_resetState & io_w_req_bits_data_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_last_may_be_rvi_call = - ~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_always_taken_0 = - ~_resetState & io_w_req_bits_data_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_entry_always_taken_1 = - ~_resetState & io_w_req_bits_data_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_2_tag = _resetState ? 20'h0 : io_w_req_bits_data_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_valid = ~_resetState & io_w_req_bits_data_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_brSlots_0_offset = - _resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_brSlots_0_lower = - _resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_brSlots_0_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_brSlots_0_sharing = - ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_brSlots_0_valid = - ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_tailSlot_offset = - _resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_tailSlot_lower = - _resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_tailSlot_tarStat = - _resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_tailSlot_sharing = - ~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_tailSlot_valid = - ~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_pftAddr = - _resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_3_entry_carry = ~_resetState & io_w_req_bits_data_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_isCall = ~_resetState & io_w_req_bits_data_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_isRet = ~_resetState & io_w_req_bits_data_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_isJalr = ~_resetState & io_w_req_bits_data_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_last_may_be_rvi_call = - ~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_always_taken_0 = - ~_resetState & io_w_req_bits_data_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_entry_always_taken_1 = - ~_resetState & io_w_req_bits_data_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign _wdata_T_3_tag = _resetState ? 20'h0 : io_w_req_bits_data_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - else begin - _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_3 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 - .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 - .RW0_clk (clock), - .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - .RW0_wdata - ({_wdata_T_3_entry_valid, - _wdata_T_3_entry_brSlots_0_offset, - _wdata_T_3_entry_brSlots_0_lower, - _wdata_T_3_entry_brSlots_0_tarStat, - _wdata_T_3_entry_brSlots_0_sharing, - _wdata_T_3_entry_brSlots_0_valid, - _wdata_T_3_entry_tailSlot_offset, - _wdata_T_3_entry_tailSlot_lower, - _wdata_T_3_entry_tailSlot_tarStat, - _wdata_T_3_entry_tailSlot_sharing, - _wdata_T_3_entry_tailSlot_valid, - _wdata_T_3_entry_pftAddr, - _wdata_T_3_entry_carry, - _wdata_T_3_entry_isCall, - _wdata_T_3_entry_isRet, - _wdata_T_3_entry_isJalr, - _wdata_T_3_entry_last_may_be_rvi_call, - _wdata_T_3_entry_always_taken_1, - _wdata_T_3_entry_always_taken_0, - _wdata_T_3_tag, - _wdata_T_2_entry_valid, - _wdata_T_2_entry_brSlots_0_offset, - _wdata_T_2_entry_brSlots_0_lower, - _wdata_T_2_entry_brSlots_0_tarStat, - _wdata_T_2_entry_brSlots_0_sharing, - _wdata_T_2_entry_brSlots_0_valid, - _wdata_T_2_entry_tailSlot_offset, - _wdata_T_2_entry_tailSlot_lower, - _wdata_T_2_entry_tailSlot_tarStat, - _wdata_T_2_entry_tailSlot_sharing, - _wdata_T_2_entry_tailSlot_valid, - _wdata_T_2_entry_pftAddr, - _wdata_T_2_entry_carry, - _wdata_T_2_entry_isCall, - _wdata_T_2_entry_isRet, - _wdata_T_2_entry_isJalr, - _wdata_T_2_entry_last_may_be_rvi_call, - _wdata_T_2_entry_always_taken_1, - _wdata_T_2_entry_always_taken_0, - _wdata_T_2_tag, - _wdata_T_1_entry_valid, - _wdata_T_1_entry_brSlots_0_offset, - _wdata_T_1_entry_brSlots_0_lower, - _wdata_T_1_entry_brSlots_0_tarStat, - _wdata_T_1_entry_brSlots_0_sharing, - _wdata_T_1_entry_brSlots_0_valid, - _wdata_T_1_entry_tailSlot_offset, - _wdata_T_1_entry_tailSlot_lower, - _wdata_T_1_entry_tailSlot_tarStat, - _wdata_T_1_entry_tailSlot_sharing, - _wdata_T_1_entry_tailSlot_valid, - _wdata_T_1_entry_pftAddr, - _wdata_T_1_entry_carry, - _wdata_T_1_entry_isCall, - _wdata_T_1_entry_isRet, - _wdata_T_1_entry_isJalr, - _wdata_T_1_entry_last_may_be_rvi_call, - _wdata_T_1_entry_always_taken_1, - _wdata_T_1_entry_always_taken_0, - _wdata_T_1_tag, - _wdata_T_0_entry_valid, - _wdata_T_0_entry_brSlots_0_offset, - _wdata_T_0_entry_brSlots_0_lower, - _wdata_T_0_entry_brSlots_0_tarStat, - _wdata_T_0_entry_brSlots_0_sharing, - _wdata_T_0_entry_brSlots_0_valid, - _wdata_T_0_entry_tailSlot_offset, - _wdata_T_0_entry_tailSlot_lower, - _wdata_T_0_entry_tailSlot_tarStat, - _wdata_T_0_entry_tailSlot_sharing, - _wdata_T_0_entry_tailSlot_valid, - _wdata_T_0_entry_pftAddr, - _wdata_T_0_entry_carry, - _wdata_T_0_entry_isCall, - _wdata_T_0_entry_isRet, - _wdata_T_0_entry_isJalr, - _wdata_T_0_entry_last_may_be_rvi_call, - _wdata_T_0_entry_always_taken_1, - _wdata_T_0_entry_always_taken_0, - _wdata_T_0_tag}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 - .RW0_rdata (_array_RW0_rdata), - .RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} - ); - assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} - assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 - assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 -endmodule - diff --git a/rtl/FTB/array_3.sv b/rtl/FTB/array_3.sv index 32493ee..e509dfe 100644 --- a/rtl/FTB/array_3.sv +++ b/rtl/FTB/array_3.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,7 +55,7 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_3( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_3( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [8:0] RW0_addr, input RW0_en, input RW0_clk, @@ -65,7 +65,7 @@ module array_3( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 input [3:0] RW0_wmask ); - array_3_ext array_3_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_3_ext array_3_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), diff --git a/rtl/ITTAGE.txt b/rtl/ITTAGE.txt index dc92507..0f599f2 100644 --- a/rtl/ITTAGE.txt +++ b/rtl/ITTAGE.txt @@ -10,8 +10,8 @@ ./rtl/ITTAGE/ITTageTable_2.sv ./rtl/ITTAGE/ITTageTable_3.sv ./rtl/ITTAGE/ITTageTable_4.sv -./rtl/ITTAGE/SRAMTemplate_35.sv ./rtl/ITTAGE/SRAMTemplate_39.sv +./rtl/ITTAGE/SRAMTemplate_43.sv ./rtl/ITTAGE/WrBypass_41.sv ./rtl/ITTAGE/WrBypass_43.sv ./rtl/ITTAGE/array_0_0.sv diff --git a/rtl/ITTAGE/CAMTemplate_41.sv b/rtl/ITTAGE/CAMTemplate_41.sv index 3d138e1..7e5cc58 100644 --- a/rtl/ITTAGE/CAMTemplate_41.sv +++ b/rtl/ITTAGE/CAMTemplate_41.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,56 +55,56 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module CAMTemplate_41( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - input clock, - input [7:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [7:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [1:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +module CAMTemplate_41( // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input clock, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input [7:0] io_r_req_0_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_0, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_1, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_2, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_3, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input io_w_valid, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [7:0] io_w_bits_data_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [1:0] io_w_bits_index // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] ); - reg [7:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - always @(posedge clock) begin - if (io_w_valid & io_w_bits_index == 2'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 2'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 2'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + always @(posedge clock) begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + if (io_w_valid & io_w_bits_index == 2'h0) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_0 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 2'h1) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_1 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 2'h2) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_2 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & (&io_w_bits_index)) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_3 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + initial begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] endmodule diff --git a/rtl/ITTAGE/CAMTemplate_43.sv b/rtl/ITTAGE/CAMTemplate_43.sv index 6bfa2c5..7480ccd 100644 --- a/rtl/ITTAGE/CAMTemplate_43.sv +++ b/rtl/ITTAGE/CAMTemplate_43.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,58 +55,58 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module CAMTemplate_43( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - input clock, - input [8:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [8:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [1:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +module CAMTemplate_43( // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input clock, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input [8:0] io_r_req_0_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_0, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_1, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_2, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_3, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input io_w_valid, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [8:0] io_w_bits_data_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [1:0] io_w_bits_index // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] ); - reg [8:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - always @(posedge clock) begin - if (io_w_valid & io_w_bits_index == 2'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28 - array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 2'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28 - array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 2'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28 - array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + always @(posedge clock) begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + if (io_w_valid & io_w_bits_index == 2'h0) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :170:21, :171:28] + array_0 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 2'h1) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :170:21, :171:28] + array_1 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 2'h2) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :170:21, :171:28] + array_2 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & (&io_w_bits_index)) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_3 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + initial begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - array_0 = _RANDOM[1'h0][8:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_1 = _RANDOM[1'h0][17:9]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_2 = _RANDOM[1'h0][26:18]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + end // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + array_0 = _RANDOM[1'h0][8:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_1 = _RANDOM[1'h0][17:9]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_2 = _RANDOM[1'h0][26:18]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]}; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] endmodule diff --git a/rtl/ITTAGE/Folded1WDataModuleTemplate.sv b/rtl/ITTAGE/Folded1WDataModuleTemplate.sv index 1c7617f..e7e3a79 100644 --- a/rtl/ITTAGE/Folded1WDataModuleTemplate.sv +++ b/rtl/ITTAGE/Folded1WDataModuleTemplate.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,21 +55,22 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module Folded1WDataModuleTemplate( // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - input clock, - input reset, - input [7:0] io_raddr_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - output io_rdata_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_wen, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input [7:0] io_waddr, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_wdata, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_resetEn // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 +module Folded1WDataModuleTemplate( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input clock, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input reset, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input io_ren_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input [7:0] io_raddr_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + output io_rdata_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_wen, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input [7:0] io_waddr, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_wdata, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_resetEn // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] ); - wire [15:0] _data_ext_R0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - reg doing_reset; // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28 - reg [3:0] resetRow; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 - reg [7:0] raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34 + wire [15:0] _data_ext_R0_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + reg doing_reset; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] + reg [3:0] resetRow; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] + reg [7:0] raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69] wire [15:0] _GEN = {{_data_ext_R0_data[15]}, {_data_ext_R0_data[14]}, @@ -86,57 +87,60 @@ module Folded1WDataModuleTemplate( // utility/src/main/scala/utility/DataModuleT {_data_ext_R0_data[3]}, {_data_ext_R0_data[2]}, {_data_ext_R0_data[1]}, - {_data_ext_R0_data[0]}}; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :226:23 - always @(posedge clock or posedge reset) begin - if (reset) begin - doing_reset <= 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow <= 4'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 + {_data_ext_R0_data[0]}}; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :243:23] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset <= 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow <= 4'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] end - else begin - doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :215:{36,50}, :217:25, :219:{18,35,49} - resetRow <= 4'(resetRow + {3'h0, doing_reset}); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :217:25, :218:24 + else begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28, :228:{36,50}, :230:25, :232:{18,35,49}] + if (doing_reset) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] + resetRow <= 4'(resetRow + 4'h1); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25, :231:45] end end // always @(posedge, posedge) - always @(posedge clock) - raddr_0 <= io_raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34 - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + always @(posedge clock) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + if (io_ren_0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + raddr_0 <= io_raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69] + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + initial begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :217:25 - raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :230:25] + raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69] `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - doing_reset = 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow = 4'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 + if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset = 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow = 4'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - data_16x16 data_ext ( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - .R0_addr (raddr_0[7:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34, :224:25 - .R0_en (1'h1), // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + data_16x16 data_ext ( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + .R0_addr (raddr_0[7:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69, :241:25] + .R0_en (1'h1), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] .R0_clk (clock), .R0_data (_data_ext_R0_data), - .W0_addr (io_waddr[7:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:229:24 - .W0_en (~doing_reset & io_wen), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :213:28, :226:23, :233:21, :235:22 + .W0_addr (io_waddr[7:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:246:24] + .W0_en (~doing_reset & io_wen), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :226:28, :243:23, :250:21, :252:22] .W0_clk (clock), - .W0_data ({16{io_wdata}}), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - .W1_addr (resetRow), // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 - .W1_en (doing_reset), // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28 + .W0_data ({16{io_wdata}}), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + .W1_addr (resetRow), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] + .W1_en (doing_reset), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] .W1_clk (clock), - .W1_data (16'h0) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + .W1_data (16'h0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] ); - assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34, :225:23, :226:23 + assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69, :242:23, :243:23] endmodule diff --git a/rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv b/rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv index 5bca41b..fef9b37 100644 --- a/rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv +++ b/rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,21 +55,22 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module Folded1WDataModuleTemplate_2( // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - input clock, - input reset, - input [8:0] io_raddr_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - output io_rdata_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_wen, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input [8:0] io_waddr, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_wdata, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 - input io_resetEn // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14 +module Folded1WDataModuleTemplate_2( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input clock, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input reset, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + input io_ren_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input [8:0] io_raddr_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + output io_rdata_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_wen, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input [8:0] io_waddr, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_wdata, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + input io_resetEn // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] ); - wire [15:0] _data_ext_R0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - reg doing_reset; // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28 - reg [4:0] resetRow; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 - reg [8:0] raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34 + wire [15:0] _data_ext_R0_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + reg doing_reset; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] + reg [4:0] resetRow; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] + reg [8:0] raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69] wire [15:0] _GEN = {{_data_ext_R0_data[15]}, {_data_ext_R0_data[14]}, @@ -86,57 +87,60 @@ module Folded1WDataModuleTemplate_2( // utility/src/main/scala/utility/DataModul {_data_ext_R0_data[3]}, {_data_ext_R0_data[2]}, {_data_ext_R0_data[1]}, - {_data_ext_R0_data[0]}}; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :226:23 - always @(posedge clock or posedge reset) begin - if (reset) begin - doing_reset <= 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow <= 5'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 + {_data_ext_R0_data[0]}}; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :243:23] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset <= 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow <= 5'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] end - else begin - doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :215:{36,50}, :217:25, :219:{18,35,49} - resetRow <= 5'(resetRow + {4'h0, doing_reset}); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :217:25, :218:24 + else begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28, :228:{36,50}, :230:25, :232:{18,35,49}] + if (doing_reset) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] + resetRow <= 5'(resetRow + 5'h1); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25, :231:45] end end // always @(posedge, posedge) - always @(posedge clock) - raddr_0 <= io_raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34 - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + always @(posedge clock) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + if (io_ren_0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14] + raddr_0 <= io_raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69] + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + initial begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :217:25 - raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :230:25] + raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69] `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - doing_reset = 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28 - resetRow = 5'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 + if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + doing_reset = 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28] + resetRow = 5'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - data_32x16 data_ext ( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - .R0_addr (raddr_0[8:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34, :224:25 - .R0_en (1'h1), // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7 + data_32x16 data_ext ( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + .R0_addr (raddr_0[8:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69, :241:25] + .R0_en (1'h1), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7] .R0_clk (clock), .R0_data (_data_ext_R0_data), - .W0_addr (io_waddr[8:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:229:24 - .W0_en (~doing_reset & io_wen), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :213:28, :226:23, :233:21, :235:22 + .W0_addr (io_waddr[8:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:246:24] + .W0_en (~doing_reset & io_wen), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :226:28, :243:23, :250:21, :252:22] .W0_clk (clock), - .W0_data ({16{io_wdata}}), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - .W1_addr (resetRow), // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25 - .W1_en (doing_reset), // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28 + .W0_data ({16{io_wdata}}), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + .W1_addr (resetRow), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25] + .W1_en (doing_reset), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28] .W1_clk (clock), - .W1_data (16'h0) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + .W1_data (16'h0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] ); - assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34, :225:23, :226:23 + assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69, :242:23, :243:23] endmodule diff --git a/rtl/ITTAGE/FoldedSRAMTemplate_21.sv b/rtl/ITTAGE/FoldedSRAMTemplate_21.sv index c780e0f..13f4b71 100644 --- a/rtl/ITTAGE/FoldedSRAMTemplate_21.sv +++ b/rtl/ITTAGE/FoldedSRAMTemplate_21.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,26 +55,28 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FoldedSRAMTemplate_21( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - input clock, - input reset, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +module FoldedSRAMTemplate_21( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [6:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [8:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [1:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [40:0] io_r_resp_data_0_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [6:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [8:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [40:0] io_w_req_bits_data_0_target // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] ); - SRAMTemplate_35 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + SRAMTemplate_39 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] .clock (clock), .reset (reset), .io_r_req_valid (io_r_req_valid), .io_r_req_bits_setIdx (io_r_req_bits_setIdx), + .io_r_resp_data_0_valid (io_r_resp_data_0_valid), .io_r_resp_data_0_tag (io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (io_r_resp_data_0_ctr), .io_r_resp_data_0_target (io_r_resp_data_0_target), diff --git a/rtl/ITTAGE/FoldedSRAMTemplate_25.sv b/rtl/ITTAGE/FoldedSRAMTemplate_25.sv index 9939f3f..41267c4 100644 --- a/rtl/ITTAGE/FoldedSRAMTemplate_25.sv +++ b/rtl/ITTAGE/FoldedSRAMTemplate_25.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,86 +55,101 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FoldedSRAMTemplate_25( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - input clock, - input reset, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +module FoldedSRAMTemplate_25( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [7:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [8:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [1:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [40:0] io_r_resp_data_0_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [7:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [8:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [40:0] io_w_req_bits_data_0_target // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] ); - wire [8:0] _array_io_r_resp_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [38:0] _array_io_r_resp_data_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [8:0] _array_io_r_resp_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [38:0] _array_io_r_resp_data_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - reg ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21 - reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - reg holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82 - wire holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 - always @(posedge clock) begin - ridx <= io_r_req_bits_setIdx[0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58} - holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + wire _array_io_r_resp_data_0_valid; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [8:0] _array_io_r_resp_data_0_tag; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_0_ctr; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [40:0] _array_io_r_resp_data_0_target; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_1_valid; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [8:0] _array_io_r_resp_data_1_tag; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_1_ctr; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [40:0] _array_io_r_resp_data_1_target; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + reg ridx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + reg holdRidx_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg holdRidx_hold_data; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (io_r_req_valid) // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + ridx <= io_r_req_bits_setIdx[0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:{23,60}] + if (holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + holdRidx_hold_data <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (reset) // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + else if (io_r_req_valid | holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + holdRidx_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - ridx = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 - holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][1]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 - holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + ridx = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][1]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] `endif // RANDOMIZE_REG_INIT + if (reset) // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_39 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + SRAMTemplate_43 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] .clock (clock), .reset (reset), .io_r_req_valid (io_r_req_valid), - .io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36 + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:257:36] + .io_r_resp_data_0_valid (_array_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_array_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_array_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_array_io_r_resp_data_0_target), + .io_r_resp_data_1_valid (_array_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_array_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_array_io_r_resp_data_1_ctr), .io_r_resp_data_1_target (_array_io_r_resp_data_1_target), .io_w_req_valid (io_w_req_valid), - .io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36 + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:274:36] .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag), .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr), .io_w_req_bits_data_0_target (io_w_req_bits_data_0_target), .io_w_req_bits_data_1_tag (io_w_req_bits_data_0_tag), .io_w_req_bits_data_1_ctr (io_w_req_bits_data_0_ctr), .io_w_req_bits_data_1_target (io_w_req_bits_data_0_target), - .io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0]) // src/main/scala/chisel3/util/OneHot.scala:58:35, :65:12, utility/src/main/scala/utility/SRAMTemplate.scala:206:54 + .io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0]) // @[src/main/scala/chisel3/util/OneHot.scala:58:35, :65:12, utility/src/main/scala/utility/SRAMTemplate.scala:275:54] ); + assign io_r_resp_data_0_valid = + ~holdRidx & _array_io_r_resp_data_0_valid | holdRidx & _array_io_r_resp_data_1_valid; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21] assign io_r_resp_data_0_tag = (holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag) - | (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21 + | (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21] assign io_r_resp_data_0_ctr = (holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr) - | (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21 + | (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21] assign io_r_resp_data_0_target = - (holdRidx ? 39'h0 : _array_io_r_resp_data_0_target) - | (holdRidx ? _array_io_r_resp_data_1_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21 + (holdRidx ? 41'h0 : _array_io_r_resp_data_0_target) + | (holdRidx ? _array_io_r_resp_data_1_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21] endmodule diff --git a/rtl/ITTAGE/ITTage.sv b/rtl/ITTAGE/ITTage.sv index 5820041..ae4dbb5 100644 --- a/rtl/ITTAGE/ITTage.sv +++ b/rtl/ITTAGE/ITTage.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,528 +55,539 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - input clock, - input reset, - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_full_target // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module ITTage( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_cfi_idx_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_cfi_idx_bits, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_jmp_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_full_target // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] ); - reg [2:0] resp_meta_allocate_bits_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:516:40 - reg resp_meta_allocate_valid_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:515:40 - wire resp_meta_altDiffers; // src/main/scala/xiangshan/frontend/ITTAGE.scala:498:50 - wire _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [38:0] _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [38:0] _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [38:0] _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [38:0] _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [1:0] _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - wire [38:0] _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 - reg [7:0] tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - reg s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_0_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [38:0] s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg s2_resps_1_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_1_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [38:0] s2_resps_1_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg s2_resps_2_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_2_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_2_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [38:0] s2_resps_2_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_3_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_3_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [38:0] s2_resps_3_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg s2_resps_4_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_4_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [1:0] s2_resps_4_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg [38:0] s2_resps_4_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 - reg s3_tageTaken_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - reg s3_tageTaken_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - reg s3_tageTaken_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - reg s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - reg [38:0] s3_tageTarget_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 - reg [38:0] s3_tageTarget_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 - reg [38:0] s3_tageTarget_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 - reg [38:0] s3_tageTarget_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 - reg [38:0] s3_providerTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39 - reg [38:0] s3_altProviderTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39 - reg s3_provided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39 - reg [2:0] s3_provider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39 - reg s3_altProvided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39 - reg [2:0] s3_altProvider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:401:39 - reg s3_finalAltPred; // src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39 - reg s3_providerU; // src/main/scala/xiangshan/frontend/ITTAGE.scala:403:39 - reg [1:0] s3_providerCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39 - reg [1:0] s3_altProviderCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39 + reg [2:0] resp_meta_allocate_bits_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:510:40] + reg resp_meta_allocate_valid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:509:40] + wire resp_meta_altDiffers; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:492:50] + wire _tables_4_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_4_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_4_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [40:0] _tables_4_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire _tables_3_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_3_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_3_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [40:0] _tables_3_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire _tables_2_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_2_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_2_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [40:0] _tables_2_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire _tables_1_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_1_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_1_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [40:0] _tables_1_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire _tables_0_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_0_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [1:0] _tables_0_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + wire [40:0] _tables_0_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] + reg [7:0] tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + reg s2_resps_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [40:0] s2_resps_0_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg s2_resps_1_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [40:0] s2_resps_1_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg s2_resps_2_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_2_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_2_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [40:0] s2_resps_2_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_3_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_3_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [40:0] s2_resps_3_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg s2_resps_4_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_4_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [1:0] s2_resps_4_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg [40:0] s2_resps_4_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27] + reg s3_tageTaken_dup_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + reg s3_tageTaken_dup_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + reg s3_tageTaken_dup_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + reg s3_tageTaken_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + reg [40:0] s3_tageTarget_dup_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] + reg [40:0] s3_tageTarget_dup_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] + reg [40:0] s3_tageTarget_dup_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] + reg [40:0] s3_tageTarget_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] + reg [40:0] s3_providerTarget; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:390:39] + reg [40:0] s3_altProviderTarget; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:391:39] + reg s3_provided; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:392:39] + reg [2:0] s3_provider; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:393:39] + reg s3_altProvided; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:394:39] + reg [2:0] s3_altProvider; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:395:39] + reg s3_finalAltPred; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39] + reg s3_providerU; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39] + reg [1:0] s3_providerCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39] + reg [1:0] s3_altProviderCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39] wire updateValid = io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isJalr & ~(io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet) & io_update_valid & ~io_update_bits_ftb_entry_tailSlot_sharing & io_update_bits_jmp_taken & io_update_bits_cfi_idx_valid - & io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/FrontendBundle.scala:655:41, src/main/scala/xiangshan/frontend/ITTAGE.scala:416:23, :417:{46,69} - assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59, :402:39, :498:50 - reg [63:0] s2_allocLFSR_lfsr; // utility/src/main/scala/utility/LFSR64.scala:27:33 + & io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/FrontendBundle.scala:656:41, src/main/scala/xiangshan/frontend/ITTAGE.scala:410:23, :411:{46,69}] + assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59, :396:39, :492:50] + reg [63:0] s2_allocLFSR_lfsr; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] wire _GEN = updateValid & io_update_bits_mispred_mask_2 - & ~(io_update_bits_meta[96] & io_update_bits_meta[77:39] == io_update_bits_full_target - & io_update_bits_meta[86:85] == 2'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :417:46, :421:40, :553:80, :554:47, :555:{38,41,59} - reg tables_0_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - reg tables_0_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - reg [38:0] tables_0_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - reg [38:0] tables_0_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 - reg tables_0_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - reg [1:0] tables_0_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - reg tables_0_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - reg tables_0_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - reg tables_0_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - reg [38:0] tables_0_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - reg [3:0] tables_0_io_update_folded_hist_REG_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg tables_1_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - reg tables_1_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - reg [38:0] tables_1_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - reg [38:0] tables_1_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 - reg tables_1_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - reg [1:0] tables_1_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - reg tables_1_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - reg tables_1_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - reg tables_1_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - reg [38:0] tables_1_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - reg [7:0] tables_1_io_update_folded_hist_REG_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg tables_2_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - reg tables_2_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - reg [38:0] tables_2_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - reg [38:0] tables_2_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 - reg tables_2_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - reg [1:0] tables_2_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - reg tables_2_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - reg tables_2_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - reg tables_2_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - reg [38:0] tables_2_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - reg [8:0] tables_2_io_update_folded_hist_REG_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg [7:0] tables_2_io_update_folded_hist_REG_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg tables_3_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - reg tables_3_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - reg [38:0] tables_3_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - reg [38:0] tables_3_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 - reg tables_3_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - reg [1:0] tables_3_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - reg tables_3_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - reg tables_3_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - reg tables_3_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - reg [38:0] tables_3_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - reg [8:0] tables_3_io_update_folded_hist_REG_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg [7:0] tables_3_io_update_folded_hist_REG_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg tables_4_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - reg tables_4_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - reg [38:0] tables_4_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - reg [38:0] tables_4_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 - reg tables_4_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - reg [1:0] tables_4_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - reg tables_4_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - reg tables_4_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - reg tables_4_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - reg [38:0] tables_4_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - reg [8:0] tables_4_io_update_folded_hist_REG_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - reg [7:0] tables_4_io_update_folded_hist_REG_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - always @(posedge clock or posedge reset) begin - if (reset) begin - tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - s2_allocLFSR_lfsr <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + & ~(io_update_bits_meta[100] + & io_update_bits_meta[81:41] == io_update_bits_full_target + & io_update_bits_meta[90:89] == 2'h0); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :411:46, :415:40, :550:80, :551:47, :552:{38,41,59}] + reg tables_0_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + reg tables_0_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + reg tables_0_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + reg [40:0] tables_0_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + reg [40:0] tables_0_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] + reg tables_0_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + reg [1:0] tables_0_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + reg tables_0_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + reg tables_0_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + reg [40:0] tables_0_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + reg [3:0] tables_0_io_update_folded_hist_r_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg tables_1_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + reg tables_1_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + reg tables_1_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + reg [40:0] tables_1_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + reg [40:0] tables_1_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] + reg tables_1_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + reg [1:0] tables_1_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + reg tables_1_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + reg tables_1_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + reg [40:0] tables_1_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + reg [7:0] tables_1_io_update_folded_hist_r_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg tables_2_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + reg tables_2_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + reg tables_2_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + reg [40:0] tables_2_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + reg [40:0] tables_2_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] + reg tables_2_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + reg [1:0] tables_2_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + reg tables_2_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + reg tables_2_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + reg [40:0] tables_2_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + reg [8:0] tables_2_io_update_folded_hist_r_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg [7:0] tables_2_io_update_folded_hist_r_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg tables_3_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + reg tables_3_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + reg tables_3_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + reg [40:0] tables_3_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + reg [40:0] tables_3_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] + reg tables_3_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + reg [1:0] tables_3_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + reg tables_3_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + reg tables_3_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + reg [40:0] tables_3_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + reg [8:0] tables_3_io_update_folded_hist_r_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg [7:0] tables_3_io_update_folded_hist_r_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg tables_4_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + reg tables_4_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + reg tables_4_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + reg [40:0] tables_4_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + reg [40:0] tables_4_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] + reg tables_4_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + reg [1:0] tables_4_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + reg tables_4_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + reg tables_4_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + reg [40:0] tables_4_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + reg [8:0] tables_4_io_update_folded_hist_r_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + reg [7:0] tables_4_io_update_folded_hist_r_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + s2_allocLFSR_lfsr <= 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] end - else begin - if (&tickCtr) // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17 - tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - else if (_GEN) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:555:38 - if ((&tickCtr) & ~(io_update_bits_meta[82])) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40, :557:46 - tickCtr <= 8'hFF; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - else if (tickCtr == 8'h0 & io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:26, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40 - tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - else if (io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40 - tickCtr <= 8'(tickCtr - 8'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - else // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40 - tickCtr <= 8'(tickCtr + 8'h1); // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + else begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + if (&tickCtr) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17] + tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + else if (_GEN) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:552:38] + if ((&tickCtr) & ~(io_update_bits_meta[86])) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :415:40, :554:46] + tickCtr <= 8'hFF; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + else if (tickCtr == 8'h0 & io_update_bits_meta[86]) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:26, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :415:40] + tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + else if (io_update_bits_meta[86]) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40] + tickCtr <= 8'(tickCtr - 8'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + else // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40] + tickCtr <= 8'(tickCtr + 8'h1); // @[src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] end - if (s2_allocLFSR_lfsr == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 - s2_allocLFSR_lfsr <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 - else // utility/src/main/scala/utility/LFSR64.scala:31:24 + if (s2_allocLFSR_lfsr == 64'h0) // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24] + s2_allocLFSR_lfsr <= 64'h1; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18] + else // @[utility/src/main/scala/utility/LFSR64.scala:31:24] s2_allocLFSR_lfsr <= {s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3] ^ s2_allocLFSR_lfsr[4], - s2_allocLFSR_lfsr[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} + s2_allocLFSR_lfsr[63:1]}; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51}] end end // always @(posedge, posedge) - wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10] wire [2:0] selectedInfo_res_2_first_tableIdx = - s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 - wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:146:40 - wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 + s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :444:24, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16] + wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:146:40] + wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16] wire [1:0] selectedInfo_res_1_first_ctr = - s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire [38:0] selectedInfo_res_1_first_target = - s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 + s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire [40:0] selectedInfo_res_1_first_target = + s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16] wire [1:0] selectedInfo_res_2_first_ctr = - s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire [38:0] selectedInfo_res_2_first_target = - s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; // utility/src/main/scala/utility/ParallelMux.scala:145:16 + s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire [40:0] selectedInfo_res_2_first_target = + s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; // @[utility/src/main/scala/utility/ParallelMux.scala:145:16] wire selectedInfo_hasTwo = selectedInfo_res_hasTwo | s2_resps_1_valid & s2_resps_0_valid | s2_resps_2_valid - & selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:{28,40} + & selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:{28,40}] wire [1:0] selectedInfo_first_ctr = selectedInfo_res_hasOne ? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr) - : selectedInfo_res_2_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 - wire [38:0] selectedInfo_first_target = + : selectedInfo_res_2_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10] + wire [40:0] selectedInfo_first_target = selectedInfo_res_hasOne ? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target) - : selectedInfo_res_2_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 - wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; // utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :150:{19,22} - wire [38:0] selectedInfo_second_target = + : selectedInfo_res_2_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10] + wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; // @[utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :150:{19,22}] + wire [40:0] selectedInfo_second_target = (selectedInfo_res_hasOne - ? 39'h0 + ? 41'h0 : (s2_resps_2_valid - ? 39'h0 - : (s2_resps_1_valid ? 39'h0 : s2_resps_0_bits_target) - | (s2_resps_1_valid ? s2_resps_0_bits_target : 39'h0)) - | (s2_resps_2_valid ? selectedInfo_res_1_first_target : 39'h0)) - | (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 39'h0) + ? 41'h0 + : (s2_resps_1_valid ? 41'h0 : s2_resps_0_bits_target) + | (s2_resps_1_valid ? s2_resps_0_bits_target : 41'h0)) + | (s2_resps_2_valid ? selectedInfo_res_1_first_target : 41'h0)) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 41'h0) | (selectedInfo_res_hasTwo - ? (s2_resps_4_valid ? 39'h0 : s2_resps_3_bits_target) - | (s2_resps_4_valid ? s2_resps_3_bits_target : 39'h0) - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 - wire providerNull = selectedInfo_first_ctr == 2'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :465:33, utility/src/main/scala/utility/ParallelMux.scala:146:28 - wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :466:18, utility/src/main/scala/utility/ParallelMux.scala:146:28 - wire _s2_tageTaken_WIRE = - selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:465:{15,18,33}, :466:18, :467:6, utility/src/main/scala/utility/ParallelMux.scala:145:16 - wire [38:0] _s2_tageTarget_WIRE = - (selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 39'h0) - | (_s2_tageTarget_T_3 ? selectedInfo_second_target : 39'h0) + ? (s2_resps_4_valid ? 41'h0 : s2_resps_3_bits_target) + | (s2_resps_4_valid ? s2_resps_3_bits_target : 41'h0) + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19] + wire providerNull = selectedInfo_first_ctr == 2'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :453:39, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:453:39, :459:33, utility/src/main/scala/utility/ParallelMux.scala:146:28] + wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:453:39, :460:18, utility/src/main/scala/utility/ParallelMux.scala:146:28] + wire _s2_tageTaken_T_9 = + selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:459:{15,18,33}, :460:18, :461:6, utility/src/main/scala/utility/ParallelMux.scala:145:16] + wire [40:0] _s2_tageTarget_T_12 = + (selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 41'h0) + | (_s2_tageTarget_T_3 ? selectedInfo_second_target : 41'h0) | (~selectedInfo_hasOne | providerNull & ~selectedInfo_hasTwo ? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, :465:33, :466:18, :467:6, :470:{15,18}, :472:{16,32,35}, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:28, :147:10 + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :453:39, :459:33, :460:18, :461:6, :464:{15,18}, :466:{16,32,35}, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:28, :147:10] wire _GEN_0 = - io_update_bits_meta[92] & io_update_bits_meta[86:85] == 2'h0 - & io_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :525:80, :526:25 - wire _GEN_1 = io_update_bits_meta[95:93] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :539:30 - wire _GEN_2 = updateValid & io_update_bits_meta[96]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:417:46, :421:40, :423:33, :520:22, :521:38, :539:30 - wire _GEN_3 = io_update_bits_meta[95:93] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 - wire _GEN_4 = io_update_bits_meta[95:93] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 - wire _GEN_5 = io_update_bits_meta[95:93] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 - wire _GEN_6 = io_update_bits_meta[95:93] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 + io_update_bits_meta[96] & io_update_bits_meta[90:89] == 2'h0 + & io_update_bits_mispred_mask_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :519:80, :520:25] + wire _GEN_1 = io_update_bits_meta[99:97] == 3'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :533:30] + wire _GEN_2 = updateValid & io_update_bits_meta[100]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:411:46, :415:40, :417:33, :514:22, :515:38, :533:30] + wire _GEN_3 = io_update_bits_meta[99:97] == 3'h1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30] + wire _GEN_4 = io_update_bits_meta[99:97] == 3'h2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30] + wire _GEN_5 = io_update_bits_meta[99:97] == 3'h3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30] + wire _GEN_6 = io_update_bits_meta[99:97] == 3'h4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30] wire _updateU_T_2 = - io_update_bits_meta[88] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[87]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :542:{31,78} - wire _updateCorrect_T = io_update_bits_meta[77:39] == io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :543:61 - wire _GEN_7 = io_update_bits_meta[81:79] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :560:34 - wire _GEN_8 = _GEN & io_update_bits_meta[82] & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 - wire _GEN_9 = io_update_bits_meta[81:79] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 - wire _GEN_10 = _GEN & io_update_bits_meta[82] & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 - wire _GEN_11 = io_update_bits_meta[81:79] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 - wire _GEN_12 = _GEN & io_update_bits_meta[82] & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 - wire _GEN_13 = io_update_bits_meta[81:79] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 - wire _GEN_14 = _GEN & io_update_bits_meta[82] & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 - wire _GEN_15 = io_update_bits_meta[81:79] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 - wire _GEN_16 = _GEN & io_update_bits_meta[82] & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 - wire _GEN_17 = _GEN & io_update_bits_meta[82]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :563:34 + io_update_bits_meta[92] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[91]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :539:{31,78}] + wire _updateCorrect_T = io_update_bits_meta[81:41] == io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :540:61] + wire _GEN_7 = io_update_bits_meta[85:83] == 3'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :557:34] + wire _GEN_8 = _GEN & io_update_bits_meta[86] & _GEN_7; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34] + wire updateMask_0 = + _GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[95:93] == 3'h0); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :417:33, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34] + wire _GEN_9 = io_update_bits_meta[85:83] == 3'h1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34] + wire _GEN_10 = _GEN & io_update_bits_meta[86] & _GEN_9; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34] + wire updateMask_1 = + _GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[95:93] == 3'h1); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34] + wire _GEN_11 = io_update_bits_meta[85:83] == 3'h2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34] + wire _GEN_12 = _GEN & io_update_bits_meta[86] & _GEN_11; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34] + wire updateMask_2 = + _GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[95:93] == 3'h2); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34] + wire _GEN_13 = io_update_bits_meta[85:83] == 3'h3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34] + wire _GEN_14 = _GEN & io_update_bits_meta[86] & _GEN_13; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34] + wire updateMask_3 = + _GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[95:93] == 3'h3); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34] + wire _GEN_15 = io_update_bits_meta[85:83] == 3'h4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34] + wire _GEN_16 = _GEN & io_update_bits_meta[86] & _GEN_15; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34] + wire updateMask_4 = + _GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[95:93] == 3'h4); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34] + wire _GEN_17 = _GEN & io_update_bits_meta[86]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :560:34] wire [2:0] selectedInfo_first_tableIdx = selectedInfo_res_hasOne ? (s2_resps_4_valid ? 3'h4 : 3'h3) - : selectedInfo_res_2_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 + : selectedInfo_res_2_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :444:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10] wire [1:0] selectedInfo_second_ctr = (selectedInfo_res_hasOne ? 2'h0 @@ -589,9 +600,9 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 | (selectedInfo_res_hasTwo ? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr) | (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0) - : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 - wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:147:10 - wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19] + wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:147:10] + wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire [4:0] _GEN_19 = ~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&selectedInfo_first_tableIdx), _GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3] @@ -600,58 +611,58 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 ~s2_resps_3_valid & s2_resps_3_bits_u == 2'h0, ~s2_resps_2_valid & s2_resps_2_bits_u == 2'h0, ~s2_resps_1_valid & s2_resps_1_bits_u == 2'h0, - ~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :509:{55,64,67,79,86}, :510:{5,55,61}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :145:16, :147:10 - wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :511:32, :513:60, utility/src/main/scala/utility/LFSR64.scala:27:33 + ~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, :503:{55,64,67,79,86}, :504:{5,55,61}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :145:16, :147:10] + wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:503:86, :505:32, :507:60, utility/src/main/scala/utility/LFSR64.scala:27:33] wire [2:0] s2_maskedEntry = _GEN_20[0] ? 3'h0 : _GEN_20[1] ? 3'h1 - : _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :513:60 - wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :509:86, :514:47 - always @(posedge clock) begin - if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_resps_0_valid <= _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_1_valid <= _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_2_valid <= _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_3_valid <= _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_4_valid <= _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 - s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + : _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :444:24, :507:60] + wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :503:86, :508:47] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + if (io_s1_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_resps_0_valid <= _tables_0_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_1_valid <= _tables_1_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_2_valid <= _tables_2_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_3_valid <= _tables_3_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_4_valid <= _tables_4_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] + s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27] end - if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_tageTaken_dup_0 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - s3_tageTarget_dup_0 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + if (io_s2_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_tageTaken_dup_0 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + s3_tageTarget_dup_0 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] end - if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_tageTaken_dup_1 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - s3_tageTarget_dup_1 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + if (io_s2_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_tageTaken_dup_1 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + s3_tageTarget_dup_1 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] end - if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_tageTaken_dup_2 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - s3_tageTarget_dup_2 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + if (io_s2_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_tageTaken_dup_2 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + s3_tageTarget_dup_2 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] end - if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_tageTaken_dup_3 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 - s3_tageTarget_dup_3 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 - s3_providerTarget <= selectedInfo_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 - s3_altProviderTarget <= selectedInfo_second_target; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39 - s3_provided <= selectedInfo_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39, utility/src/main/scala/utility/ParallelMux.scala:145:16 - s3_provider <= selectedInfo_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 - s3_altProvided <= selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39, utility/src/main/scala/utility/ParallelMux.scala:146:28 + if (io_s2_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_tageTaken_dup_3 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59] + s3_tageTarget_dup_3 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59] + s3_providerTarget <= selectedInfo_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:390:39, utility/src/main/scala/utility/ParallelMux.scala:147:10] + s3_altProviderTarget <= selectedInfo_second_target; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:391:39] + s3_provided <= selectedInfo_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:392:39, utility/src/main/scala/utility/ParallelMux.scala:145:16] + s3_provider <= selectedInfo_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:393:39, utility/src/main/scala/utility/ParallelMux.scala:147:10] + s3_altProvided <= selectedInfo_hasTwo; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:394:39, utility/src/main/scala/utility/ParallelMux.scala:146:28] s3_altProvider <= (selectedInfo_res_hasOne | ~s2_resps_2_valid ? 3'h0 @@ -659,17 +670,17 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 | (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0) | (selectedInfo_res_hasTwo ? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0) - : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :401:39, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 - s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39, :474:{25,58}, utility/src/main/scala/utility/ParallelMux.scala:146:28 + : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, :395:39, :444:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19] + s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39, :468:{25,58}, utility/src/main/scala/utility/ParallelMux.scala:146:28] s3_providerU <= selectedInfo_res_hasOne ? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0]) : s2_resps_2_valid ? s2_resps_2_bits_u[0] - : s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :403:39, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 - s3_providerCtr <= selectedInfo_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 - s3_altProviderCtr <= selectedInfo_second_ctr; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39 - resp_meta_allocate_valid_r <= |_GEN_19; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :515:{40,61} + : s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :397:39, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10] + s3_providerCtr <= selectedInfo_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39, utility/src/main/scala/utility/ParallelMux.scala:147:10] + s3_altProviderCtr <= selectedInfo_second_ctr; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39] + resp_meta_allocate_valid_r <= |_GEN_19; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:503:86, :509:{40,61}] resp_meta_allocate_bits_r <= _s2_allocEntry_T[0] ? s2_maskedEntry @@ -677,225 +688,227 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 ? 3'h0 : _GEN_19[1] ? 3'h1 - : _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :509:86, :514:{27,47}, :516:40 + : _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :444:24, :503:86, :508:{27,47}, :510:40] + end + tables_0_io_update_valid_REG <= updateMask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41] + tables_0_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43] + if (updateMask_0) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34] + tables_0_io_update_correct_r <= _GEN_8 | _GEN_1 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45] + tables_0_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + tables_0_io_update_old_target_r <= + _GEN_1 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48] + tables_0_io_update_alloc_r <= _GEN_17 & _GEN_7; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43] + tables_0_io_update_oldCtr_r <= + _GEN_1 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44] + tables_0_io_update_uValid_r <= _GEN_8 | _GEN_2 & _GEN_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44] + tables_0_io_update_u_r <= ~_GEN_8 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39] + tables_0_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + tables_0_io_update_folded_hist_r_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + end + tables_1_io_update_valid_REG <= updateMask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41] + tables_1_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43] + if (updateMask_1) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34] + tables_1_io_update_correct_r <= _GEN_10 | _GEN_3 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45] + tables_1_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + tables_1_io_update_old_target_r <= + _GEN_3 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48] + tables_1_io_update_alloc_r <= _GEN_17 & _GEN_9; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43] + tables_1_io_update_oldCtr_r <= + _GEN_3 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44] + tables_1_io_update_uValid_r <= _GEN_10 | _GEN_2 & _GEN_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44] + tables_1_io_update_u_r <= ~_GEN_10 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39] + tables_1_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + tables_1_io_update_folded_hist_r_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + end + tables_2_io_update_valid_REG <= updateMask_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41] + tables_2_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43] + if (updateMask_2) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34] + tables_2_io_update_correct_r <= _GEN_12 | _GEN_4 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45] + tables_2_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + tables_2_io_update_old_target_r <= + _GEN_4 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48] + tables_2_io_update_alloc_r <= _GEN_17 & _GEN_11; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43] + tables_2_io_update_oldCtr_r <= + _GEN_4 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44] + tables_2_io_update_uValid_r <= _GEN_12 | _GEN_2 & _GEN_4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44] + tables_2_io_update_u_r <= ~_GEN_12 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39] + tables_2_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + tables_2_io_update_folded_hist_r_hist_13_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + tables_2_io_update_folded_hist_r_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + end + tables_3_io_update_valid_REG <= updateMask_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41] + tables_3_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43] + if (updateMask_3) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34] + tables_3_io_update_correct_r <= _GEN_14 | _GEN_5 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45] + tables_3_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + tables_3_io_update_old_target_r <= + _GEN_5 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48] + tables_3_io_update_alloc_r <= _GEN_17 & _GEN_13; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43] + tables_3_io_update_oldCtr_r <= + _GEN_5 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44] + tables_3_io_update_uValid_r <= _GEN_14 | _GEN_2 & _GEN_5; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44] + tables_3_io_update_u_r <= ~_GEN_14 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39] + tables_3_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + tables_3_io_update_folded_hist_r_hist_6_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + tables_3_io_update_folded_hist_r_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + end + tables_4_io_update_valid_REG <= updateMask_4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41] + tables_4_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43] + if (updateMask_4) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34] + tables_4_io_update_correct_r <= _GEN_16 | _GEN_6 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45] + tables_4_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + tables_4_io_update_old_target_r <= + _GEN_6 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48] + tables_4_io_update_alloc_r <= _GEN_17 & _GEN_15; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43] + tables_4_io_update_oldCtr_r <= + _GEN_6 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44] + tables_4_io_update_uValid_r <= _GEN_16 | _GEN_2 & _GEN_6; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44] + tables_4_io_update_u_r <= ~_GEN_16 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39] + tables_4_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] + tables_4_io_update_folded_hist_r_hist_10_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + tables_4_io_update_folded_hist_r_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] end - tables_0_io_update_valid_REG <= - _GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[91:89] == 3'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :423:33, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 - tables_0_io_update_correct_REG <= _GEN_8 | _GEN_1 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 - tables_0_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - tables_0_io_update_old_target_REG <= - _GEN_1 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 - tables_0_io_update_alloc_REG <= _GEN_17 & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 - tables_0_io_update_oldCtr_REG <= - _GEN_1 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 - tables_0_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 - tables_0_io_update_uValid_REG <= _GEN_8 | _GEN_2 & _GEN_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 - tables_0_io_update_u_REG <= ~_GEN_8 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 - tables_0_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - tables_0_io_update_folded_hist_REG_hist_12_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_1_io_update_valid_REG <= - _GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[91:89] == 3'h1); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 - tables_1_io_update_correct_REG <= _GEN_10 | _GEN_3 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 - tables_1_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - tables_1_io_update_old_target_REG <= - _GEN_3 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 - tables_1_io_update_alloc_REG <= _GEN_17 & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 - tables_1_io_update_oldCtr_REG <= - _GEN_3 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 - tables_1_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 - tables_1_io_update_uValid_REG <= _GEN_10 | _GEN_2 & _GEN_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 - tables_1_io_update_u_REG <= ~_GEN_10 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 - tables_1_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - tables_1_io_update_folded_hist_REG_hist_14_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_2_io_update_valid_REG <= - _GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[91:89] == 3'h2); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 - tables_2_io_update_correct_REG <= _GEN_12 | _GEN_4 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 - tables_2_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - tables_2_io_update_old_target_REG <= - _GEN_4 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 - tables_2_io_update_alloc_REG <= _GEN_17 & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 - tables_2_io_update_oldCtr_REG <= - _GEN_4 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 - tables_2_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 - tables_2_io_update_uValid_REG <= _GEN_12 | _GEN_2 & _GEN_4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 - tables_2_io_update_u_REG <= ~_GEN_12 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 - tables_2_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - tables_2_io_update_folded_hist_REG_hist_13_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_2_io_update_folded_hist_REG_hist_4_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_3_io_update_valid_REG <= - _GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[91:89] == 3'h3); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 - tables_3_io_update_correct_REG <= _GEN_14 | _GEN_5 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 - tables_3_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - tables_3_io_update_old_target_REG <= - _GEN_5 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 - tables_3_io_update_alloc_REG <= _GEN_17 & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 - tables_3_io_update_oldCtr_REG <= - _GEN_5 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 - tables_3_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 - tables_3_io_update_uValid_REG <= _GEN_14 | _GEN_2 & _GEN_5; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 - tables_3_io_update_u_REG <= ~_GEN_14 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 - tables_3_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - tables_3_io_update_folded_hist_REG_hist_6_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_3_io_update_folded_hist_REG_hist_2_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_4_io_update_valid_REG <= - _GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[91:89] == 3'h4); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 - tables_4_io_update_correct_REG <= _GEN_16 | _GEN_6 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 - tables_4_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - tables_4_io_update_old_target_REG <= - _GEN_6 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 - tables_4_io_update_alloc_REG <= _GEN_17 & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 - tables_4_io_update_oldCtr_REG <= - _GEN_6 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 - tables_4_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 - tables_4_io_update_uValid_REG <= _GEN_16 | _GEN_2 & _GEN_6; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 - tables_4_io_update_u_REG <= ~_GEN_16 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 - tables_4_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 - tables_4_io_update_folded_hist_REG_hist_10_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - tables_4_io_update_folded_hist_REG_hist_3_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:77]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + logic [31:0] _RANDOM[0:79]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - for (logic [6:0] i = 7'h0; i < 7'h4E; i += 7'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - tickCtr = {_RANDOM[7'hE][31:26], _RANDOM[7'hF][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24 - s2_resps_0_valid = _RANDOM[7'hF][2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 - s2_resps_0_bits_ctr = _RANDOM[7'hF][4:3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 - s2_resps_0_bits_u = _RANDOM[7'hF][6:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 - s2_resps_0_bits_target = {_RANDOM[7'hF][31:7], _RANDOM[7'h10][13:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 - s2_resps_1_valid = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_1_bits_ctr = _RANDOM[7'h10][16:15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_1_bits_u = _RANDOM[7'h10][18:17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_1_bits_target = {_RANDOM[7'h10][31:19], _RANDOM[7'h11][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_2_valid = _RANDOM[7'h11][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_2_bits_ctr = _RANDOM[7'h11][28:27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_2_bits_u = _RANDOM[7'h11][30:29]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + for (logic [6:0] i = 7'h0; i < 7'h50; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + end // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + tickCtr = _RANDOM[7'hF][25:18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24] + s2_resps_0_valid = _RANDOM[7'hF][26]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27] + s2_resps_0_bits_ctr = _RANDOM[7'hF][28:27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27] + s2_resps_0_bits_u = _RANDOM[7'hF][30:29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27] + s2_resps_0_bits_target = {_RANDOM[7'hF][31], _RANDOM[7'h10], _RANDOM[7'h11][7:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27] + s2_resps_1_valid = _RANDOM[7'h11][8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_1_bits_ctr = _RANDOM[7'h11][10:9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_1_bits_u = _RANDOM[7'h11][12:11]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_1_bits_target = {_RANDOM[7'h11][31:13], _RANDOM[7'h12][21:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_2_valid = _RANDOM[7'h12][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_2_bits_ctr = _RANDOM[7'h12][24:23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_2_bits_u = _RANDOM[7'h12][26:25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] s2_resps_2_bits_target = - {_RANDOM[7'h11][31], _RANDOM[7'h12], _RANDOM[7'h13][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_3_valid = _RANDOM[7'h13][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_3_bits_ctr = _RANDOM[7'h13][8:7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_3_bits_u = _RANDOM[7'h13][10:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_3_bits_target = {_RANDOM[7'h13][31:11], _RANDOM[7'h14][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_4_valid = _RANDOM[7'h14][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_4_bits_ctr = _RANDOM[7'h14][20:19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_4_bits_u = _RANDOM[7'h14][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s2_resps_4_bits_target = {_RANDOM[7'h14][31:23], _RANDOM[7'h15][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 - s3_tageTaken_dup_0 = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 - s3_tageTaken_dup_1 = _RANDOM[7'h19][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 - s3_tageTaken_dup_2 = _RANDOM[7'h19][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 - s3_tageTaken_dup_3 = _RANDOM[7'h19][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 - s3_tageTarget_dup_0 = {_RANDOM[7'h19][31:23], _RANDOM[7'h1A][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59 - s3_tageTarget_dup_1 = - {_RANDOM[7'h1A][31:30], _RANDOM[7'h1B], _RANDOM[7'h1C][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 - s3_tageTarget_dup_2 = {_RANDOM[7'h1C][31:5], _RANDOM[7'h1D][11:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 - s3_tageTarget_dup_3 = {_RANDOM[7'h1D][31:12], _RANDOM[7'h1E][18:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 - s3_providerTarget = {_RANDOM[7'h1E][31:19], _RANDOM[7'h1F][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59, :396:39 - s3_altProviderTarget = {_RANDOM[7'h1F][31:26], _RANDOM[7'h20], _RANDOM[7'h21][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :396:39, :397:39 - s3_provided = _RANDOM[7'h21][1]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :398:39 - s3_provider = _RANDOM[7'h21][4:2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :399:39 - s3_altProvided = _RANDOM[7'h21][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :400:39 - s3_altProvider = _RANDOM[7'h21][8:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :401:39 - s3_finalAltPred = _RANDOM[7'h21][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :402:39 - s3_providerU = _RANDOM[7'h21][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :403:39 - s3_providerCtr = _RANDOM[7'h21][12:11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :404:39 - s3_altProviderCtr = _RANDOM[7'h21][14:13]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :405:39 - s2_allocLFSR_lfsr = {_RANDOM[7'h21][31:15], _RANDOM[7'h22], _RANDOM[7'h23][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_allocate_valid_r = _RANDOM[7'h23][15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :515:40, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_allocate_bits_r = _RANDOM[7'h23][18:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :516:40, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_valid_REG = _RANDOM[7'h23][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_correct_REG = _RANDOM[7'h23][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_target_REG = {_RANDOM[7'h23][31:21], _RANDOM[7'h24][27:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_old_target_REG = - {_RANDOM[7'h24][31:28], _RANDOM[7'h25], _RANDOM[7'h26][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 - tables_0_io_update_alloc_REG = _RANDOM[7'h26][3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 - tables_0_io_update_oldCtr_REG = _RANDOM[7'h26][5:4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 - tables_0_io_update_reset_u_REG = _RANDOM[7'h26][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 - tables_0_io_update_uValid_REG = _RANDOM[7'h26][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 - tables_0_io_update_u_REG = _RANDOM[7'h26][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 - tables_0_io_update_pc_REG = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][15:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 - tables_0_io_update_folded_hist_REG_hist_12_folded_hist = - {_RANDOM[7'h28][31:30], _RANDOM[7'h29][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_1_io_update_valid_REG = _RANDOM[7'h2C][4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 - tables_1_io_update_correct_REG = _RANDOM[7'h2C][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 - tables_1_io_update_target_REG = {_RANDOM[7'h2C][31:6], _RANDOM[7'h2D][12:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 - tables_1_io_update_old_target_REG = {_RANDOM[7'h2D][31:13], _RANDOM[7'h2E][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 - tables_1_io_update_alloc_REG = _RANDOM[7'h2E][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 - tables_1_io_update_oldCtr_REG = _RANDOM[7'h2E][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 - tables_1_io_update_reset_u_REG = _RANDOM[7'h2E][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 - tables_1_io_update_uValid_REG = _RANDOM[7'h2E][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 - tables_1_io_update_u_REG = _RANDOM[7'h2E][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 - tables_1_io_update_pc_REG = - {_RANDOM[7'h2E][31:26], _RANDOM[7'h2F], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 - tables_1_io_update_folded_hist_REG_hist_14_folded_hist = - {_RANDOM[7'h30][31:30], _RANDOM[7'h31][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :589:38, :591:47 - tables_2_io_update_valid_REG = _RANDOM[7'h34][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 - tables_2_io_update_correct_REG = _RANDOM[7'h34][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 - tables_2_io_update_target_REG = {_RANDOM[7'h34][31:23], _RANDOM[7'h35][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 - tables_2_io_update_old_target_REG = - {_RANDOM[7'h35][31:30], _RANDOM[7'h36], _RANDOM[7'h37][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 - tables_2_io_update_alloc_REG = _RANDOM[7'h37][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 - tables_2_io_update_oldCtr_REG = _RANDOM[7'h37][7:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 - tables_2_io_update_reset_u_REG = _RANDOM[7'h37][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 - tables_2_io_update_uValid_REG = _RANDOM[7'h37][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 - tables_2_io_update_u_REG = _RANDOM[7'h37][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 - tables_2_io_update_pc_REG = {_RANDOM[7'h37][31:11], _RANDOM[7'h38][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 - tables_2_io_update_folded_hist_REG_hist_13_folded_hist = _RANDOM[7'h39][31:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_2_io_update_folded_hist_REG_hist_4_folded_hist = - {_RANDOM[7'h3B][31:27], _RANDOM[7'h3C][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_3_io_update_valid_REG = _RANDOM[7'h3D][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 - tables_3_io_update_correct_REG = _RANDOM[7'h3D][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 - tables_3_io_update_target_REG = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 - tables_3_io_update_old_target_REG = {_RANDOM[7'h3E][31:15], _RANDOM[7'h3F][21:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 - tables_3_io_update_alloc_REG = _RANDOM[7'h3F][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 - tables_3_io_update_oldCtr_REG = _RANDOM[7'h3F][24:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 - tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 - tables_3_io_update_uValid_REG = _RANDOM[7'h3F][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 - tables_3_io_update_u_REG = _RANDOM[7'h3F][27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 - tables_3_io_update_pc_REG = - {_RANDOM[7'h3F][31:28], _RANDOM[7'h40], _RANDOM[7'h41][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 - tables_3_io_update_folded_hist_REG_hist_6_folded_hist = - {_RANDOM[7'h43][31:28], _RANDOM[7'h44][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_3_io_update_folded_hist_REG_hist_2_folded_hist = - {_RANDOM[7'h44][31:28], _RANDOM[7'h45][3:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_4_io_update_valid_REG = _RANDOM[7'h45][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :591:47 - tables_4_io_update_correct_REG = _RANDOM[7'h45][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, :591:47 - tables_4_io_update_target_REG = {_RANDOM[7'h45][31:25], _RANDOM[7'h46]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :591:47 - tables_4_io_update_old_target_REG = {_RANDOM[7'h47], _RANDOM[7'h48][6:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46 - tables_4_io_update_alloc_REG = _RANDOM[7'h48][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 - tables_4_io_update_oldCtr_REG = _RANDOM[7'h48][9:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 - tables_4_io_update_reset_u_REG = _RANDOM[7'h48][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 - tables_4_io_update_uValid_REG = _RANDOM[7'h48][11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 - tables_4_io_update_u_REG = _RANDOM[7'h48][12]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 - tables_4_io_update_pc_REG = {_RANDOM[7'h48][31:13], _RANDOM[7'h49][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 - tables_4_io_update_folded_hist_REG_hist_10_folded_hist = _RANDOM[7'h4B][22:14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 - tables_4_io_update_folded_hist_REG_hist_3_folded_hist = _RANDOM[7'h4D][12:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + {_RANDOM[7'h12][31:27], _RANDOM[7'h13], _RANDOM[7'h14][3:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_3_valid = _RANDOM[7'h14][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_3_bits_ctr = _RANDOM[7'h14][6:5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_3_bits_u = _RANDOM[7'h14][8:7]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_3_bits_target = {_RANDOM[7'h14][31:9], _RANDOM[7'h15][17:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_4_valid = _RANDOM[7'h15][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_4_bits_ctr = _RANDOM[7'h15][20:19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_4_bits_u = _RANDOM[7'h15][22:21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s2_resps_4_bits_target = {_RANDOM[7'h15][31:23], _RANDOM[7'h16]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27] + s3_tageTaken_dup_0 = _RANDOM[7'h1A][27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59] + s3_tageTaken_dup_1 = _RANDOM[7'h1A][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59] + s3_tageTaken_dup_2 = _RANDOM[7'h1A][29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59] + s3_tageTaken_dup_3 = _RANDOM[7'h1A][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59] + s3_tageTarget_dup_0 = {_RANDOM[7'h1A][31], _RANDOM[7'h1B], _RANDOM[7'h1C][7:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59] + s3_tageTarget_dup_1 = {_RANDOM[7'h1C][31:8], _RANDOM[7'h1D][16:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59] + s3_tageTarget_dup_2 = {_RANDOM[7'h1D][31:17], _RANDOM[7'h1E][25:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59] + s3_tageTarget_dup_3 = + {_RANDOM[7'h1E][31:26], _RANDOM[7'h1F], _RANDOM[7'h20][2:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59] + s3_providerTarget = {_RANDOM[7'h20][31:3], _RANDOM[7'h21][11:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59, :390:39] + s3_altProviderTarget = {_RANDOM[7'h21][31:12], _RANDOM[7'h22][20:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :390:39, :391:39] + s3_provided = _RANDOM[7'h22][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :392:39] + s3_provider = _RANDOM[7'h22][24:22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :393:39] + s3_altProvided = _RANDOM[7'h22][25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :394:39] + s3_altProvider = _RANDOM[7'h22][28:26]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :395:39] + s3_finalAltPred = _RANDOM[7'h22][29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :396:39] + s3_providerU = _RANDOM[7'h22][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :397:39] + s3_providerCtr = {_RANDOM[7'h22][31], _RANDOM[7'h23][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :398:39] + s3_altProviderCtr = _RANDOM[7'h23][2:1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :398:39, :399:39] + s2_allocLFSR_lfsr = {_RANDOM[7'h23][31:3], _RANDOM[7'h24], _RANDOM[7'h25][2:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :398:39, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_allocate_valid_r = _RANDOM[7'h25][3]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :509:40, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_allocate_bits_r = _RANDOM[7'h25][6:4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :510:40, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_valid_REG = _RANDOM[7'h25][7]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_reset_u_REG = _RANDOM[7'h25][8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :577:43, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_correct_r = _RANDOM[7'h25][9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_target_r = {_RANDOM[7'h25][31:10], _RANDOM[7'h26][18:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_old_target_r = {_RANDOM[7'h26][31:19], _RANDOM[7'h27][27:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48] + tables_0_io_update_alloc_r = _RANDOM[7'h27][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43] + tables_0_io_update_oldCtr_r = _RANDOM[7'h27][30:29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44] + tables_0_io_update_uValid_r = _RANDOM[7'h27][31]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44] + tables_0_io_update_u_r = _RANDOM[7'h28][0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :585:39] + tables_0_io_update_pc_r = {_RANDOM[7'h28][31:1], _RANDOM[7'h29][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :585:39, :586:40] + tables_0_io_update_folded_hist_r_hist_12_folded_hist = _RANDOM[7'h2A][27:24]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_1_io_update_valid_REG = _RANDOM[7'h2D][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41] + tables_1_io_update_reset_u_REG = _RANDOM[7'h2D][31]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43] + tables_1_io_update_correct_r = _RANDOM[7'h2E][0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45] + tables_1_io_update_target_r = {_RANDOM[7'h2E][31:1], _RANDOM[7'h2F][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45, :579:44] + tables_1_io_update_old_target_r = {_RANDOM[7'h2F][31:10], _RANDOM[7'h30][18:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48] + tables_1_io_update_alloc_r = _RANDOM[7'h30][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43] + tables_1_io_update_oldCtr_r = _RANDOM[7'h30][21:20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44] + tables_1_io_update_uValid_r = _RANDOM[7'h30][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44] + tables_1_io_update_u_r = _RANDOM[7'h30][23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39] + tables_1_io_update_pc_r = + {_RANDOM[7'h30][31:24], _RANDOM[7'h31], _RANDOM[7'h32][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40] + tables_1_io_update_folded_hist_r_hist_14_folded_hist = + {_RANDOM[7'h32][31:30], _RANDOM[7'h33][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :586:40, :588:49] + tables_2_io_update_valid_REG = _RANDOM[7'h36][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41] + tables_2_io_update_reset_u_REG = _RANDOM[7'h36][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43] + tables_2_io_update_correct_r = _RANDOM[7'h36][23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45] + tables_2_io_update_target_r = + {_RANDOM[7'h36][31:24], _RANDOM[7'h37], _RANDOM[7'h38][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44] + tables_2_io_update_old_target_r = {_RANDOM[7'h38][31:1], _RANDOM[7'h39][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48] + tables_2_io_update_alloc_r = _RANDOM[7'h39][10]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43] + tables_2_io_update_oldCtr_r = _RANDOM[7'h39][12:11]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44] + tables_2_io_update_uValid_r = _RANDOM[7'h39][13]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44] + tables_2_io_update_u_r = _RANDOM[7'h39][14]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39] + tables_2_io_update_pc_r = {_RANDOM[7'h39][31:15], _RANDOM[7'h3A][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40] + tables_2_io_update_folded_hist_r_hist_13_folded_hist = + {_RANDOM[7'h3B][31:29], _RANDOM[7'h3C][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_2_io_update_folded_hist_r_hist_4_folded_hist = _RANDOM[7'h3E][8:1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_3_io_update_valid_REG = _RANDOM[7'h3F][12]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41] + tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][13]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43] + tables_3_io_update_correct_r = _RANDOM[7'h3F][14]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45] + tables_3_io_update_target_r = {_RANDOM[7'h3F][31:15], _RANDOM[7'h40][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44] + tables_3_io_update_old_target_r = + {_RANDOM[7'h40][31:24], _RANDOM[7'h41], _RANDOM[7'h42][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48] + tables_3_io_update_alloc_r = _RANDOM[7'h42][1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43] + tables_3_io_update_oldCtr_r = _RANDOM[7'h42][3:2]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44] + tables_3_io_update_uValid_r = _RANDOM[7'h42][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44] + tables_3_io_update_u_r = _RANDOM[7'h42][5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39] + tables_3_io_update_pc_r = {_RANDOM[7'h42][31:6], _RANDOM[7'h43][14:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40] + tables_3_io_update_folded_hist_r_hist_6_folded_hist = _RANDOM[7'h46][16:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_3_io_update_folded_hist_r_hist_2_folded_hist = _RANDOM[7'h47][15:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_4_io_update_valid_REG = _RANDOM[7'h48][3]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41] + tables_4_io_update_reset_u_REG = _RANDOM[7'h48][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43] + tables_4_io_update_correct_r = _RANDOM[7'h48][5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45] + tables_4_io_update_target_r = {_RANDOM[7'h48][31:6], _RANDOM[7'h49][14:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44] + tables_4_io_update_old_target_r = {_RANDOM[7'h49][31:15], _RANDOM[7'h4A][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48] + tables_4_io_update_alloc_r = _RANDOM[7'h4A][24]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43] + tables_4_io_update_oldCtr_r = _RANDOM[7'h4A][26:25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44] + tables_4_io_update_uValid_r = _RANDOM[7'h4A][27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44] + tables_4_io_update_u_r = _RANDOM[7'h4A][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39] + tables_4_io_update_pc_r = + {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B], _RANDOM[7'h4C][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40] + tables_4_io_update_folded_hist_r_hist_10_folded_hist = _RANDOM[7'h4E][8:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] + tables_4_io_update_folded_hist_r_hist_3_folded_hist = _RANDOM[7'h4F][30:23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - tickCtr = 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 - s2_allocLFSR_lfsr = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + if (reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + tickCtr = 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24] + s2_allocLFSR_lfsr = 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - ITTageTable tables_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + ITTageTable tables_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -906,20 +919,20 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 .io_resp_bits_ctr (_tables_0_io_resp_bits_ctr), .io_resp_bits_u (_tables_0_io_resp_bits_u), .io_resp_bits_target (_tables_0_io_resp_bits_target), - .io_update_pc (tables_0_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_pc (tables_0_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] .io_update_folded_hist_hist_12_folded_hist - (tables_0_io_update_folded_hist_REG_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - .io_update_valid (tables_0_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - .io_update_correct (tables_0_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - .io_update_alloc (tables_0_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - .io_update_oldCtr (tables_0_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - .io_update_uValid (tables_0_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - .io_update_u (tables_0_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - .io_update_reset_u (tables_0_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - .io_update_target (tables_0_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - .io_update_old_target (tables_0_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + (tables_0_io_update_folded_hist_r_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + .io_update_valid (tables_0_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + .io_update_correct (tables_0_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + .io_update_alloc (tables_0_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + .io_update_oldCtr (tables_0_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + .io_update_uValid (tables_0_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + .io_update_u (tables_0_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + .io_update_reset_u (tables_0_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + .io_update_target (tables_0_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + .io_update_old_target (tables_0_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] ); - ITTageTable_1 tables_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + ITTageTable_1 tables_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -930,20 +943,20 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 .io_resp_bits_ctr (_tables_1_io_resp_bits_ctr), .io_resp_bits_u (_tables_1_io_resp_bits_u), .io_resp_bits_target (_tables_1_io_resp_bits_target), - .io_update_pc (tables_1_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_pc (tables_1_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] .io_update_folded_hist_hist_14_folded_hist - (tables_1_io_update_folded_hist_REG_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - .io_update_valid (tables_1_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - .io_update_correct (tables_1_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - .io_update_alloc (tables_1_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - .io_update_oldCtr (tables_1_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - .io_update_uValid (tables_1_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - .io_update_u (tables_1_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - .io_update_reset_u (tables_1_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - .io_update_target (tables_1_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - .io_update_old_target (tables_1_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + (tables_1_io_update_folded_hist_r_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + .io_update_valid (tables_1_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + .io_update_correct (tables_1_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + .io_update_alloc (tables_1_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + .io_update_oldCtr (tables_1_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + .io_update_uValid (tables_1_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + .io_update_u (tables_1_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + .io_update_reset_u (tables_1_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + .io_update_target (tables_1_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + .io_update_old_target (tables_1_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] ); - ITTageTable_2 tables_2 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + ITTageTable_2 tables_2 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -956,22 +969,22 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 .io_resp_bits_ctr (_tables_2_io_resp_bits_ctr), .io_resp_bits_u (_tables_2_io_resp_bits_u), .io_resp_bits_target (_tables_2_io_resp_bits_target), - .io_update_pc (tables_2_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_pc (tables_2_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] .io_update_folded_hist_hist_13_folded_hist - (tables_2_io_update_folded_hist_REG_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + (tables_2_io_update_folded_hist_r_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] .io_update_folded_hist_hist_4_folded_hist - (tables_2_io_update_folded_hist_REG_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - .io_update_valid (tables_2_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - .io_update_correct (tables_2_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - .io_update_alloc (tables_2_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - .io_update_oldCtr (tables_2_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - .io_update_uValid (tables_2_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - .io_update_u (tables_2_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - .io_update_reset_u (tables_2_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - .io_update_target (tables_2_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - .io_update_old_target (tables_2_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + (tables_2_io_update_folded_hist_r_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + .io_update_valid (tables_2_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + .io_update_correct (tables_2_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + .io_update_alloc (tables_2_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + .io_update_oldCtr (tables_2_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + .io_update_uValid (tables_2_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + .io_update_u (tables_2_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + .io_update_reset_u (tables_2_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + .io_update_target (tables_2_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + .io_update_old_target (tables_2_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] ); - ITTageTable_3 tables_3 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + ITTageTable_3 tables_3 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -984,22 +997,22 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 .io_resp_bits_ctr (_tables_3_io_resp_bits_ctr), .io_resp_bits_u (_tables_3_io_resp_bits_u), .io_resp_bits_target (_tables_3_io_resp_bits_target), - .io_update_pc (tables_3_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_pc (tables_3_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] .io_update_folded_hist_hist_6_folded_hist - (tables_3_io_update_folded_hist_REG_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + (tables_3_io_update_folded_hist_r_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] .io_update_folded_hist_hist_2_folded_hist - (tables_3_io_update_folded_hist_REG_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - .io_update_valid (tables_3_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - .io_update_correct (tables_3_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - .io_update_alloc (tables_3_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - .io_update_oldCtr (tables_3_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - .io_update_uValid (tables_3_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - .io_update_u (tables_3_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - .io_update_reset_u (tables_3_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - .io_update_target (tables_3_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - .io_update_old_target (tables_3_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + (tables_3_io_update_folded_hist_r_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + .io_update_valid (tables_3_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + .io_update_correct (tables_3_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + .io_update_alloc (tables_3_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + .io_update_oldCtr (tables_3_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + .io_update_uValid (tables_3_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + .io_update_u (tables_3_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + .io_update_reset_u (tables_3_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + .io_update_target (tables_3_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + .io_update_old_target (tables_3_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] ); - ITTageTable_4 tables_4 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + ITTageTable_4 tables_4 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -1012,193 +1025,193 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 .io_resp_bits_ctr (_tables_4_io_resp_bits_ctr), .io_resp_bits_u (_tables_4_io_resp_bits_u), .io_resp_bits_target (_tables_4_io_resp_bits_target), - .io_update_pc (tables_4_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_pc (tables_4_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40] .io_update_folded_hist_hist_10_folded_hist - (tables_4_io_update_folded_hist_REG_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + (tables_4_io_update_folded_hist_r_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] .io_update_folded_hist_hist_3_folded_hist - (tables_4_io_update_folded_hist_REG_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 - .io_update_valid (tables_4_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 - .io_update_correct (tables_4_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 - .io_update_alloc (tables_4_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 - .io_update_oldCtr (tables_4_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 - .io_update_uValid (tables_4_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 - .io_update_u (tables_4_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 - .io_update_reset_u (tables_4_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 - .io_update_target (tables_4_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 - .io_update_old_target (tables_4_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + (tables_4_io_update_folded_hist_r_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49] + .io_update_valid (tables_4_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41] + .io_update_correct (tables_4_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45] + .io_update_alloc (tables_4_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43] + .io_update_oldCtr (tables_4_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44] + .io_update_uValid (tables_4_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44] + .io_update_u (tables_4_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39] + .io_update_reset_u (tables_4_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43] + .io_update_target (tables_4_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44] + .io_update_old_target (tables_4_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48] ); assign io_out_s2_full_pred_0_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_jalr_target = - io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_0_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_jalr_target = - io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_1_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_jalr_target = - io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_last_may_be_rvi_call = - io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_2_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_jalr_target = - io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_fallThroughErr = - io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s2_full_pred_3_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_jalr_target = s3_tageTaken_dup_0 ? s3_tageTarget_dup_0 - : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24] assign io_out_s3_full_pred_0_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_0_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_jalr_target = s3_tageTaken_dup_1 ? s3_tageTarget_dup_1 - : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24] assign io_out_s3_full_pred_1_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_1_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_jalr_target = s3_tageTaken_dup_2 ? s3_tageTarget_dup_2 - : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24] assign io_out_s3_full_pred_2_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_2_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_jalr_target = s3_tageTaken_dup_3 ? s3_tageTarget_dup_3 - : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 - assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24] + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_s3_full_pred_3_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 - assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_meta = {122'h0, s3_provided, @@ -1213,44 +1226,44 @@ module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 resp_meta_allocate_bits_r, s3_tageTaken_dup_3, s3_providerTarget, - s3_altProviderTarget}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :396:39, :397:39, :398:39, :399:39, :400:39, :401:39, :403:39, :404:39, :405:39, :410:26, :498:50, :515:40, :516:40 + s3_altProviderTarget}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :390:39, :391:39, :392:39, :393:39, :394:39, :395:39, :397:39, :398:39, :399:39, :404:26, :492:50, :509:40, :510:40] assign io_out_last_stage_ftb_entry_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_brSlots_0_offset = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_brSlots_0_lower = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_brSlots_0_sharing = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_brSlots_0_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_tailSlot_offset = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_tailSlot_lower = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_tailSlot_tarStat = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_tailSlot_sharing = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_tailSlot_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_pftAddr = - io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_carry = - io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_isCall = - io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_isRet = - io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_isJalr = - io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = - io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_always_taken_0 = - io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] assign io_out_last_stage_ftb_entry_always_taken_1 = - io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7] endmodule diff --git a/rtl/ITTAGE/ITTageTable.sv b/rtl/ITTAGE/ITTageTable.sv index cc9b2c6..1a766cb 100644 --- a/rtl/ITTAGE/ITTageTable.sv +++ b/rtl/ITTAGE/ITTageTable.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,448 +55,172 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTageTable( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +module ITTageTable( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output io_resp_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_ctr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [40:0] io_resp_bits_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [3:0] io_update_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_correct, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_alloc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [1:0] io_update_oldCtr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_uValid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_reset_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_old_target // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] ); - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 - reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [7:0] s0_idx = {io_req_bits_pc[8:5], _GEN}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40} - reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 - reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40} - wire [8:0] update_wdata_tag = + wire _resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_1_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_0_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _us_io_rdata_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] + wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + reg [8:0] s1_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:211:68] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40}] + wire [8:0] update_tag = {io_update_pc[17:14], {io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist} - ^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43 - wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - assign _resp_invalid_by_write_WIRE = + ^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75,82}, :205:43] + wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + assign _resp_invalid_by_write_T_2 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 - & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 - wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 - wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 - wire [1:0] old_ctr = - _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 - wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 - wire [1:0] update_wdata_ctr = + & s1_bank_has_write_on_this_req_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33, :239:48] + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :254:33] + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :254:33] + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24, :276:20] + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20] + wire [1:0] update_wdata_ctr = io_update_alloc ? 2'h2 : (&old_ctr) & io_update_correct ? 2'h3 : update_wdata_ctr_oldSatNotTaken & ~io_update_correct ? 2'h0 - : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 - wire [38:0] update_wdata_target = + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20, :278:28] + wire [40:0] update_wdata_target = io_update_alloc | update_wdata_ctr_oldSatNotTaken ? io_update_target - : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} - wire [255:0] _validArray_T = - {io_update_valid & (&update_idx) | validArray[255], - io_update_valid & update_idx == 8'hFE | validArray[254], - io_update_valid & update_idx == 8'hFD | validArray[253], - io_update_valid & update_idx == 8'hFC | validArray[252], - io_update_valid & update_idx == 8'hFB | validArray[251], - io_update_valid & update_idx == 8'hFA | validArray[250], - io_update_valid & update_idx == 8'hF9 | validArray[249], - io_update_valid & update_idx == 8'hF8 | validArray[248], - io_update_valid & update_idx == 8'hF7 | validArray[247], - io_update_valid & update_idx == 8'hF6 | validArray[246], - io_update_valid & update_idx == 8'hF5 | validArray[245], - io_update_valid & update_idx == 8'hF4 | validArray[244], - io_update_valid & update_idx == 8'hF3 | validArray[243], - io_update_valid & update_idx == 8'hF2 | validArray[242], - io_update_valid & update_idx == 8'hF1 | validArray[241], - io_update_valid & update_idx == 8'hF0 | validArray[240], - io_update_valid & update_idx == 8'hEF | validArray[239], - io_update_valid & update_idx == 8'hEE | validArray[238], - io_update_valid & update_idx == 8'hED | validArray[237], - io_update_valid & update_idx == 8'hEC | validArray[236], - io_update_valid & update_idx == 8'hEB | validArray[235], - io_update_valid & update_idx == 8'hEA | validArray[234], - io_update_valid & update_idx == 8'hE9 | validArray[233], - io_update_valid & update_idx == 8'hE8 | validArray[232], - io_update_valid & update_idx == 8'hE7 | validArray[231], - io_update_valid & update_idx == 8'hE6 | validArray[230], - io_update_valid & update_idx == 8'hE5 | validArray[229], - io_update_valid & update_idx == 8'hE4 | validArray[228], - io_update_valid & update_idx == 8'hE3 | validArray[227], - io_update_valid & update_idx == 8'hE2 | validArray[226], - io_update_valid & update_idx == 8'hE1 | validArray[225], - io_update_valid & update_idx == 8'hE0 | validArray[224], - io_update_valid & update_idx == 8'hDF | validArray[223], - io_update_valid & update_idx == 8'hDE | validArray[222], - io_update_valid & update_idx == 8'hDD | validArray[221], - io_update_valid & update_idx == 8'hDC | validArray[220], - io_update_valid & update_idx == 8'hDB | validArray[219], - io_update_valid & update_idx == 8'hDA | validArray[218], - io_update_valid & update_idx == 8'hD9 | validArray[217], - io_update_valid & update_idx == 8'hD8 | validArray[216], - io_update_valid & update_idx == 8'hD7 | validArray[215], - io_update_valid & update_idx == 8'hD6 | validArray[214], - io_update_valid & update_idx == 8'hD5 | validArray[213], - io_update_valid & update_idx == 8'hD4 | validArray[212], - io_update_valid & update_idx == 8'hD3 | validArray[211], - io_update_valid & update_idx == 8'hD2 | validArray[210], - io_update_valid & update_idx == 8'hD1 | validArray[209], - io_update_valid & update_idx == 8'hD0 | validArray[208], - io_update_valid & update_idx == 8'hCF | validArray[207], - io_update_valid & update_idx == 8'hCE | validArray[206], - io_update_valid & update_idx == 8'hCD | validArray[205], - io_update_valid & update_idx == 8'hCC | validArray[204], - io_update_valid & update_idx == 8'hCB | validArray[203], - io_update_valid & update_idx == 8'hCA | validArray[202], - io_update_valid & update_idx == 8'hC9 | validArray[201], - io_update_valid & update_idx == 8'hC8 | validArray[200], - io_update_valid & update_idx == 8'hC7 | validArray[199], - io_update_valid & update_idx == 8'hC6 | validArray[198], - io_update_valid & update_idx == 8'hC5 | validArray[197], - io_update_valid & update_idx == 8'hC4 | validArray[196], - io_update_valid & update_idx == 8'hC3 | validArray[195], - io_update_valid & update_idx == 8'hC2 | validArray[194], - io_update_valid & update_idx == 8'hC1 | validArray[193], - io_update_valid & update_idx == 8'hC0 | validArray[192], - io_update_valid & update_idx == 8'hBF | validArray[191], - io_update_valid & update_idx == 8'hBE | validArray[190], - io_update_valid & update_idx == 8'hBD | validArray[189], - io_update_valid & update_idx == 8'hBC | validArray[188], - io_update_valid & update_idx == 8'hBB | validArray[187], - io_update_valid & update_idx == 8'hBA | validArray[186], - io_update_valid & update_idx == 8'hB9 | validArray[185], - io_update_valid & update_idx == 8'hB8 | validArray[184], - io_update_valid & update_idx == 8'hB7 | validArray[183], - io_update_valid & update_idx == 8'hB6 | validArray[182], - io_update_valid & update_idx == 8'hB5 | validArray[181], - io_update_valid & update_idx == 8'hB4 | validArray[180], - io_update_valid & update_idx == 8'hB3 | validArray[179], - io_update_valid & update_idx == 8'hB2 | validArray[178], - io_update_valid & update_idx == 8'hB1 | validArray[177], - io_update_valid & update_idx == 8'hB0 | validArray[176], - io_update_valid & update_idx == 8'hAF | validArray[175], - io_update_valid & update_idx == 8'hAE | validArray[174], - io_update_valid & update_idx == 8'hAD | validArray[173], - io_update_valid & update_idx == 8'hAC | validArray[172], - io_update_valid & update_idx == 8'hAB | validArray[171], - io_update_valid & update_idx == 8'hAA | validArray[170], - io_update_valid & update_idx == 8'hA9 | validArray[169], - io_update_valid & update_idx == 8'hA8 | validArray[168], - io_update_valid & update_idx == 8'hA7 | validArray[167], - io_update_valid & update_idx == 8'hA6 | validArray[166], - io_update_valid & update_idx == 8'hA5 | validArray[165], - io_update_valid & update_idx == 8'hA4 | validArray[164], - io_update_valid & update_idx == 8'hA3 | validArray[163], - io_update_valid & update_idx == 8'hA2 | validArray[162], - io_update_valid & update_idx == 8'hA1 | validArray[161], - io_update_valid & update_idx == 8'hA0 | validArray[160], - io_update_valid & update_idx == 8'h9F | validArray[159], - io_update_valid & update_idx == 8'h9E | validArray[158], - io_update_valid & update_idx == 8'h9D | validArray[157], - io_update_valid & update_idx == 8'h9C | validArray[156], - io_update_valid & update_idx == 8'h9B | validArray[155], - io_update_valid & update_idx == 8'h9A | validArray[154], - io_update_valid & update_idx == 8'h99 | validArray[153], - io_update_valid & update_idx == 8'h98 | validArray[152], - io_update_valid & update_idx == 8'h97 | validArray[151], - io_update_valid & update_idx == 8'h96 | validArray[150], - io_update_valid & update_idx == 8'h95 | validArray[149], - io_update_valid & update_idx == 8'h94 | validArray[148], - io_update_valid & update_idx == 8'h93 | validArray[147], - io_update_valid & update_idx == 8'h92 | validArray[146], - io_update_valid & update_idx == 8'h91 | validArray[145], - io_update_valid & update_idx == 8'h90 | validArray[144], - io_update_valid & update_idx == 8'h8F | validArray[143], - io_update_valid & update_idx == 8'h8E | validArray[142], - io_update_valid & update_idx == 8'h8D | validArray[141], - io_update_valid & update_idx == 8'h8C | validArray[140], - io_update_valid & update_idx == 8'h8B | validArray[139], - io_update_valid & update_idx == 8'h8A | validArray[138], - io_update_valid & update_idx == 8'h89 | validArray[137], - io_update_valid & update_idx == 8'h88 | validArray[136], - io_update_valid & update_idx == 8'h87 | validArray[135], - io_update_valid & update_idx == 8'h86 | validArray[134], - io_update_valid & update_idx == 8'h85 | validArray[133], - io_update_valid & update_idx == 8'h84 | validArray[132], - io_update_valid & update_idx == 8'h83 | validArray[131], - io_update_valid & update_idx == 8'h82 | validArray[130], - io_update_valid & update_idx == 8'h81 | validArray[129], - io_update_valid & update_idx == 8'h80 | validArray[128], - io_update_valid & update_idx == 8'h7F | validArray[127], - io_update_valid & update_idx == 8'h7E | validArray[126], - io_update_valid & update_idx == 8'h7D | validArray[125], - io_update_valid & update_idx == 8'h7C | validArray[124], - io_update_valid & update_idx == 8'h7B | validArray[123], - io_update_valid & update_idx == 8'h7A | validArray[122], - io_update_valid & update_idx == 8'h79 | validArray[121], - io_update_valid & update_idx == 8'h78 | validArray[120], - io_update_valid & update_idx == 8'h77 | validArray[119], - io_update_valid & update_idx == 8'h76 | validArray[118], - io_update_valid & update_idx == 8'h75 | validArray[117], - io_update_valid & update_idx == 8'h74 | validArray[116], - io_update_valid & update_idx == 8'h73 | validArray[115], - io_update_valid & update_idx == 8'h72 | validArray[114], - io_update_valid & update_idx == 8'h71 | validArray[113], - io_update_valid & update_idx == 8'h70 | validArray[112], - io_update_valid & update_idx == 8'h6F | validArray[111], - io_update_valid & update_idx == 8'h6E | validArray[110], - io_update_valid & update_idx == 8'h6D | validArray[109], - io_update_valid & update_idx == 8'h6C | validArray[108], - io_update_valid & update_idx == 8'h6B | validArray[107], - io_update_valid & update_idx == 8'h6A | validArray[106], - io_update_valid & update_idx == 8'h69 | validArray[105], - io_update_valid & update_idx == 8'h68 | validArray[104], - io_update_valid & update_idx == 8'h67 | validArray[103], - io_update_valid & update_idx == 8'h66 | validArray[102], - io_update_valid & update_idx == 8'h65 | validArray[101], - io_update_valid & update_idx == 8'h64 | validArray[100], - io_update_valid & update_idx == 8'h63 | validArray[99], - io_update_valid & update_idx == 8'h62 | validArray[98], - io_update_valid & update_idx == 8'h61 | validArray[97], - io_update_valid & update_idx == 8'h60 | validArray[96], - io_update_valid & update_idx == 8'h5F | validArray[95], - io_update_valid & update_idx == 8'h5E | validArray[94], - io_update_valid & update_idx == 8'h5D | validArray[93], - io_update_valid & update_idx == 8'h5C | validArray[92], - io_update_valid & update_idx == 8'h5B | validArray[91], - io_update_valid & update_idx == 8'h5A | validArray[90], - io_update_valid & update_idx == 8'h59 | validArray[89], - io_update_valid & update_idx == 8'h58 | validArray[88], - io_update_valid & update_idx == 8'h57 | validArray[87], - io_update_valid & update_idx == 8'h56 | validArray[86], - io_update_valid & update_idx == 8'h55 | validArray[85], - io_update_valid & update_idx == 8'h54 | validArray[84], - io_update_valid & update_idx == 8'h53 | validArray[83], - io_update_valid & update_idx == 8'h52 | validArray[82], - io_update_valid & update_idx == 8'h51 | validArray[81], - io_update_valid & update_idx == 8'h50 | validArray[80], - io_update_valid & update_idx == 8'h4F | validArray[79], - io_update_valid & update_idx == 8'h4E | validArray[78], - io_update_valid & update_idx == 8'h4D | validArray[77], - io_update_valid & update_idx == 8'h4C | validArray[76], - io_update_valid & update_idx == 8'h4B | validArray[75], - io_update_valid & update_idx == 8'h4A | validArray[74], - io_update_valid & update_idx == 8'h49 | validArray[73], - io_update_valid & update_idx == 8'h48 | validArray[72], - io_update_valid & update_idx == 8'h47 | validArray[71], - io_update_valid & update_idx == 8'h46 | validArray[70], - io_update_valid & update_idx == 8'h45 | validArray[69], - io_update_valid & update_idx == 8'h44 | validArray[68], - io_update_valid & update_idx == 8'h43 | validArray[67], - io_update_valid & update_idx == 8'h42 | validArray[66], - io_update_valid & update_idx == 8'h41 | validArray[65], - io_update_valid & update_idx == 8'h40 | validArray[64], - io_update_valid & update_idx == 8'h3F | validArray[63], - io_update_valid & update_idx == 8'h3E | validArray[62], - io_update_valid & update_idx == 8'h3D | validArray[61], - io_update_valid & update_idx == 8'h3C | validArray[60], - io_update_valid & update_idx == 8'h3B | validArray[59], - io_update_valid & update_idx == 8'h3A | validArray[58], - io_update_valid & update_idx == 8'h39 | validArray[57], - io_update_valid & update_idx == 8'h38 | validArray[56], - io_update_valid & update_idx == 8'h37 | validArray[55], - io_update_valid & update_idx == 8'h36 | validArray[54], - io_update_valid & update_idx == 8'h35 | validArray[53], - io_update_valid & update_idx == 8'h34 | validArray[52], - io_update_valid & update_idx == 8'h33 | validArray[51], - io_update_valid & update_idx == 8'h32 | validArray[50], - io_update_valid & update_idx == 8'h31 | validArray[49], - io_update_valid & update_idx == 8'h30 | validArray[48], - io_update_valid & update_idx == 8'h2F | validArray[47], - io_update_valid & update_idx == 8'h2E | validArray[46], - io_update_valid & update_idx == 8'h2D | validArray[45], - io_update_valid & update_idx == 8'h2C | validArray[44], - io_update_valid & update_idx == 8'h2B | validArray[43], - io_update_valid & update_idx == 8'h2A | validArray[42], - io_update_valid & update_idx == 8'h29 | validArray[41], - io_update_valid & update_idx == 8'h28 | validArray[40], - io_update_valid & update_idx == 8'h27 | validArray[39], - io_update_valid & update_idx == 8'h26 | validArray[38], - io_update_valid & update_idx == 8'h25 | validArray[37], - io_update_valid & update_idx == 8'h24 | validArray[36], - io_update_valid & update_idx == 8'h23 | validArray[35], - io_update_valid & update_idx == 8'h22 | validArray[34], - io_update_valid & update_idx == 8'h21 | validArray[33], - io_update_valid & update_idx == 8'h20 | validArray[32], - io_update_valid & update_idx == 8'h1F | validArray[31], - io_update_valid & update_idx == 8'h1E | validArray[30], - io_update_valid & update_idx == 8'h1D | validArray[29], - io_update_valid & update_idx == 8'h1C | validArray[28], - io_update_valid & update_idx == 8'h1B | validArray[27], - io_update_valid & update_idx == 8'h1A | validArray[26], - io_update_valid & update_idx == 8'h19 | validArray[25], - io_update_valid & update_idx == 8'h18 | validArray[24], - io_update_valid & update_idx == 8'h17 | validArray[23], - io_update_valid & update_idx == 8'h16 | validArray[22], - io_update_valid & update_idx == 8'h15 | validArray[21], - io_update_valid & update_idx == 8'h14 | validArray[20], - io_update_valid & update_idx == 8'h13 | validArray[19], - io_update_valid & update_idx == 8'h12 | validArray[18], - io_update_valid & update_idx == 8'h11 | validArray[17], - io_update_valid & update_idx == 8'h10 | validArray[16], - io_update_valid & update_idx == 8'hF | validArray[15], - io_update_valid & update_idx == 8'hE | validArray[14], - io_update_valid & update_idx == 8'hD | validArray[13], - io_update_valid & update_idx == 8'hC | validArray[12], - io_update_valid & update_idx == 8'hB | validArray[11], - io_update_valid & update_idx == 8'hA | validArray[10], - io_update_valid & update_idx == 8'h9 | validArray[9], - io_update_valid & update_idx == 8'h8 | validArray[8], - io_update_valid & update_idx == 8'h7 | validArray[7], - io_update_valid & update_idx == 8'h6 | validArray[6], - io_update_valid & update_idx == 8'h5 | validArray[5], - io_update_valid & update_idx == 8'h4 | validArray[4], - io_update_valid & update_idx == 8'h3 | validArray[3], - io_update_valid & update_idx == 8'h2 | validArray[2], - io_update_valid & update_idx == 8'h1 | validArray[1], - io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 - always @(posedge clock or posedge reset) begin - if (reset) - validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 - end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :213:36 + : io_update_old_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] s1_tag <= {io_req_bits_pc[17:14], {io_req_bits_pc[13], io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist} - ^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43, :213:68 - s1_bank_req_1h_0 <= ~(_GEN[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 - s1_bank_req_1h_1 <= _GEN[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + ^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75,82}, :205:43, :211:68] + s1_bank_req_1h_0 <= ~(_GEN[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :213:33] + s1_bank_req_1h_1 <= _GEN[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :213:33] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] end end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = - {_RANDOM[4'h0], - _RANDOM[4'h1], - _RANDOM[4'h2], - _RANDOM[4'h3], - _RANDOM[4'h4], - _RANDOM[4'h5], - _RANDOM[4'h6], - _RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 - s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 - s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} - s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68] + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + Folded1WDataModuleTemplate us ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] .clock (clock), .reset (reset), - .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 + .io_ren_0 (io_req_valid), + .io_raddr_0 ({io_req_bits_pc[8:5], _GEN}), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40}] .io_rdata_0 (_us_io_rdata_0), .io_wen (io_update_uValid), - .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 + .io_waddr (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40] .io_wdata (io_update_u), .io_resetEn (io_update_reset_u) ); - FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_21 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & ~(_GEN[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_r_req_valid (io_req_valid & ~(_GEN[0])), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40] + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_21 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & _GEN[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_r_req_valid (io_req_valid & _GEN[0]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40] + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + WrBypass_41 wrbypass ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] .clock (clock), .reset (reset), .io_wen (io_update_valid), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 - .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40] + .io_write_data_0 (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] .io_hit (_wrbypass_io_hit), .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) ); assign io_resp_valid = - _s1_req_rhit_T[0] + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag - & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53} + & ~_resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33, :217:44, :231:62, :234:{50,53}] assign io_resp_bits_ctr = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 - assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:18, :236:18] assign io_resp_bits_target = - (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] endmodule diff --git a/rtl/ITTAGE/ITTageTable_1.sv b/rtl/ITTAGE/ITTageTable_1.sv index 15668b3..b16941b 100644 --- a/rtl/ITTAGE/ITTageTable_1.sv +++ b/rtl/ITTAGE/ITTageTable_1.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,442 +55,167 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTageTable_1( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +module ITTageTable_1( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output io_resp_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_ctr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [40:0] io_resp_bits_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_update_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_correct, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_alloc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [1:0] io_update_oldCtr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_uValid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_reset_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_old_target // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] ); - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 - reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 - reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [8:0] update_wdata_tag = + wire _resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_1_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_0_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _us_io_rdata_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] + wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + reg [8:0] s1_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:211:68] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + wire [8:0] update_tag = {io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist} - ^ {io_update_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 - assign _resp_invalid_by_write_WIRE = + ^ {io_update_folded_hist_hist_14_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43] + assign _resp_invalid_by_write_T_2 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 - & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 - wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 - wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 - wire [1:0] old_ctr = - _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 - wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 - wire [1:0] update_wdata_ctr = + & s1_bank_has_write_on_this_req_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33, :239:48] + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :254:33] + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :254:33] + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24, :276:20] + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20] + wire [1:0] update_wdata_ctr = io_update_alloc ? 2'h2 : (&old_ctr) & io_update_correct ? 2'h3 : update_wdata_ctr_oldSatNotTaken & ~io_update_correct ? 2'h0 - : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 - wire [38:0] update_wdata_target = + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20, :278:28] + wire [40:0] update_wdata_target = io_update_alloc | update_wdata_ctr_oldSatNotTaken ? io_update_target - : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} - wire [255:0] _validArray_T = - {io_update_valid & (&update_idx) | validArray[255], - io_update_valid & update_idx == 8'hFE | validArray[254], - io_update_valid & update_idx == 8'hFD | validArray[253], - io_update_valid & update_idx == 8'hFC | validArray[252], - io_update_valid & update_idx == 8'hFB | validArray[251], - io_update_valid & update_idx == 8'hFA | validArray[250], - io_update_valid & update_idx == 8'hF9 | validArray[249], - io_update_valid & update_idx == 8'hF8 | validArray[248], - io_update_valid & update_idx == 8'hF7 | validArray[247], - io_update_valid & update_idx == 8'hF6 | validArray[246], - io_update_valid & update_idx == 8'hF5 | validArray[245], - io_update_valid & update_idx == 8'hF4 | validArray[244], - io_update_valid & update_idx == 8'hF3 | validArray[243], - io_update_valid & update_idx == 8'hF2 | validArray[242], - io_update_valid & update_idx == 8'hF1 | validArray[241], - io_update_valid & update_idx == 8'hF0 | validArray[240], - io_update_valid & update_idx == 8'hEF | validArray[239], - io_update_valid & update_idx == 8'hEE | validArray[238], - io_update_valid & update_idx == 8'hED | validArray[237], - io_update_valid & update_idx == 8'hEC | validArray[236], - io_update_valid & update_idx == 8'hEB | validArray[235], - io_update_valid & update_idx == 8'hEA | validArray[234], - io_update_valid & update_idx == 8'hE9 | validArray[233], - io_update_valid & update_idx == 8'hE8 | validArray[232], - io_update_valid & update_idx == 8'hE7 | validArray[231], - io_update_valid & update_idx == 8'hE6 | validArray[230], - io_update_valid & update_idx == 8'hE5 | validArray[229], - io_update_valid & update_idx == 8'hE4 | validArray[228], - io_update_valid & update_idx == 8'hE3 | validArray[227], - io_update_valid & update_idx == 8'hE2 | validArray[226], - io_update_valid & update_idx == 8'hE1 | validArray[225], - io_update_valid & update_idx == 8'hE0 | validArray[224], - io_update_valid & update_idx == 8'hDF | validArray[223], - io_update_valid & update_idx == 8'hDE | validArray[222], - io_update_valid & update_idx == 8'hDD | validArray[221], - io_update_valid & update_idx == 8'hDC | validArray[220], - io_update_valid & update_idx == 8'hDB | validArray[219], - io_update_valid & update_idx == 8'hDA | validArray[218], - io_update_valid & update_idx == 8'hD9 | validArray[217], - io_update_valid & update_idx == 8'hD8 | validArray[216], - io_update_valid & update_idx == 8'hD7 | validArray[215], - io_update_valid & update_idx == 8'hD6 | validArray[214], - io_update_valid & update_idx == 8'hD5 | validArray[213], - io_update_valid & update_idx == 8'hD4 | validArray[212], - io_update_valid & update_idx == 8'hD3 | validArray[211], - io_update_valid & update_idx == 8'hD2 | validArray[210], - io_update_valid & update_idx == 8'hD1 | validArray[209], - io_update_valid & update_idx == 8'hD0 | validArray[208], - io_update_valid & update_idx == 8'hCF | validArray[207], - io_update_valid & update_idx == 8'hCE | validArray[206], - io_update_valid & update_idx == 8'hCD | validArray[205], - io_update_valid & update_idx == 8'hCC | validArray[204], - io_update_valid & update_idx == 8'hCB | validArray[203], - io_update_valid & update_idx == 8'hCA | validArray[202], - io_update_valid & update_idx == 8'hC9 | validArray[201], - io_update_valid & update_idx == 8'hC8 | validArray[200], - io_update_valid & update_idx == 8'hC7 | validArray[199], - io_update_valid & update_idx == 8'hC6 | validArray[198], - io_update_valid & update_idx == 8'hC5 | validArray[197], - io_update_valid & update_idx == 8'hC4 | validArray[196], - io_update_valid & update_idx == 8'hC3 | validArray[195], - io_update_valid & update_idx == 8'hC2 | validArray[194], - io_update_valid & update_idx == 8'hC1 | validArray[193], - io_update_valid & update_idx == 8'hC0 | validArray[192], - io_update_valid & update_idx == 8'hBF | validArray[191], - io_update_valid & update_idx == 8'hBE | validArray[190], - io_update_valid & update_idx == 8'hBD | validArray[189], - io_update_valid & update_idx == 8'hBC | validArray[188], - io_update_valid & update_idx == 8'hBB | validArray[187], - io_update_valid & update_idx == 8'hBA | validArray[186], - io_update_valid & update_idx == 8'hB9 | validArray[185], - io_update_valid & update_idx == 8'hB8 | validArray[184], - io_update_valid & update_idx == 8'hB7 | validArray[183], - io_update_valid & update_idx == 8'hB6 | validArray[182], - io_update_valid & update_idx == 8'hB5 | validArray[181], - io_update_valid & update_idx == 8'hB4 | validArray[180], - io_update_valid & update_idx == 8'hB3 | validArray[179], - io_update_valid & update_idx == 8'hB2 | validArray[178], - io_update_valid & update_idx == 8'hB1 | validArray[177], - io_update_valid & update_idx == 8'hB0 | validArray[176], - io_update_valid & update_idx == 8'hAF | validArray[175], - io_update_valid & update_idx == 8'hAE | validArray[174], - io_update_valid & update_idx == 8'hAD | validArray[173], - io_update_valid & update_idx == 8'hAC | validArray[172], - io_update_valid & update_idx == 8'hAB | validArray[171], - io_update_valid & update_idx == 8'hAA | validArray[170], - io_update_valid & update_idx == 8'hA9 | validArray[169], - io_update_valid & update_idx == 8'hA8 | validArray[168], - io_update_valid & update_idx == 8'hA7 | validArray[167], - io_update_valid & update_idx == 8'hA6 | validArray[166], - io_update_valid & update_idx == 8'hA5 | validArray[165], - io_update_valid & update_idx == 8'hA4 | validArray[164], - io_update_valid & update_idx == 8'hA3 | validArray[163], - io_update_valid & update_idx == 8'hA2 | validArray[162], - io_update_valid & update_idx == 8'hA1 | validArray[161], - io_update_valid & update_idx == 8'hA0 | validArray[160], - io_update_valid & update_idx == 8'h9F | validArray[159], - io_update_valid & update_idx == 8'h9E | validArray[158], - io_update_valid & update_idx == 8'h9D | validArray[157], - io_update_valid & update_idx == 8'h9C | validArray[156], - io_update_valid & update_idx == 8'h9B | validArray[155], - io_update_valid & update_idx == 8'h9A | validArray[154], - io_update_valid & update_idx == 8'h99 | validArray[153], - io_update_valid & update_idx == 8'h98 | validArray[152], - io_update_valid & update_idx == 8'h97 | validArray[151], - io_update_valid & update_idx == 8'h96 | validArray[150], - io_update_valid & update_idx == 8'h95 | validArray[149], - io_update_valid & update_idx == 8'h94 | validArray[148], - io_update_valid & update_idx == 8'h93 | validArray[147], - io_update_valid & update_idx == 8'h92 | validArray[146], - io_update_valid & update_idx == 8'h91 | validArray[145], - io_update_valid & update_idx == 8'h90 | validArray[144], - io_update_valid & update_idx == 8'h8F | validArray[143], - io_update_valid & update_idx == 8'h8E | validArray[142], - io_update_valid & update_idx == 8'h8D | validArray[141], - io_update_valid & update_idx == 8'h8C | validArray[140], - io_update_valid & update_idx == 8'h8B | validArray[139], - io_update_valid & update_idx == 8'h8A | validArray[138], - io_update_valid & update_idx == 8'h89 | validArray[137], - io_update_valid & update_idx == 8'h88 | validArray[136], - io_update_valid & update_idx == 8'h87 | validArray[135], - io_update_valid & update_idx == 8'h86 | validArray[134], - io_update_valid & update_idx == 8'h85 | validArray[133], - io_update_valid & update_idx == 8'h84 | validArray[132], - io_update_valid & update_idx == 8'h83 | validArray[131], - io_update_valid & update_idx == 8'h82 | validArray[130], - io_update_valid & update_idx == 8'h81 | validArray[129], - io_update_valid & update_idx == 8'h80 | validArray[128], - io_update_valid & update_idx == 8'h7F | validArray[127], - io_update_valid & update_idx == 8'h7E | validArray[126], - io_update_valid & update_idx == 8'h7D | validArray[125], - io_update_valid & update_idx == 8'h7C | validArray[124], - io_update_valid & update_idx == 8'h7B | validArray[123], - io_update_valid & update_idx == 8'h7A | validArray[122], - io_update_valid & update_idx == 8'h79 | validArray[121], - io_update_valid & update_idx == 8'h78 | validArray[120], - io_update_valid & update_idx == 8'h77 | validArray[119], - io_update_valid & update_idx == 8'h76 | validArray[118], - io_update_valid & update_idx == 8'h75 | validArray[117], - io_update_valid & update_idx == 8'h74 | validArray[116], - io_update_valid & update_idx == 8'h73 | validArray[115], - io_update_valid & update_idx == 8'h72 | validArray[114], - io_update_valid & update_idx == 8'h71 | validArray[113], - io_update_valid & update_idx == 8'h70 | validArray[112], - io_update_valid & update_idx == 8'h6F | validArray[111], - io_update_valid & update_idx == 8'h6E | validArray[110], - io_update_valid & update_idx == 8'h6D | validArray[109], - io_update_valid & update_idx == 8'h6C | validArray[108], - io_update_valid & update_idx == 8'h6B | validArray[107], - io_update_valid & update_idx == 8'h6A | validArray[106], - io_update_valid & update_idx == 8'h69 | validArray[105], - io_update_valid & update_idx == 8'h68 | validArray[104], - io_update_valid & update_idx == 8'h67 | validArray[103], - io_update_valid & update_idx == 8'h66 | validArray[102], - io_update_valid & update_idx == 8'h65 | validArray[101], - io_update_valid & update_idx == 8'h64 | validArray[100], - io_update_valid & update_idx == 8'h63 | validArray[99], - io_update_valid & update_idx == 8'h62 | validArray[98], - io_update_valid & update_idx == 8'h61 | validArray[97], - io_update_valid & update_idx == 8'h60 | validArray[96], - io_update_valid & update_idx == 8'h5F | validArray[95], - io_update_valid & update_idx == 8'h5E | validArray[94], - io_update_valid & update_idx == 8'h5D | validArray[93], - io_update_valid & update_idx == 8'h5C | validArray[92], - io_update_valid & update_idx == 8'h5B | validArray[91], - io_update_valid & update_idx == 8'h5A | validArray[90], - io_update_valid & update_idx == 8'h59 | validArray[89], - io_update_valid & update_idx == 8'h58 | validArray[88], - io_update_valid & update_idx == 8'h57 | validArray[87], - io_update_valid & update_idx == 8'h56 | validArray[86], - io_update_valid & update_idx == 8'h55 | validArray[85], - io_update_valid & update_idx == 8'h54 | validArray[84], - io_update_valid & update_idx == 8'h53 | validArray[83], - io_update_valid & update_idx == 8'h52 | validArray[82], - io_update_valid & update_idx == 8'h51 | validArray[81], - io_update_valid & update_idx == 8'h50 | validArray[80], - io_update_valid & update_idx == 8'h4F | validArray[79], - io_update_valid & update_idx == 8'h4E | validArray[78], - io_update_valid & update_idx == 8'h4D | validArray[77], - io_update_valid & update_idx == 8'h4C | validArray[76], - io_update_valid & update_idx == 8'h4B | validArray[75], - io_update_valid & update_idx == 8'h4A | validArray[74], - io_update_valid & update_idx == 8'h49 | validArray[73], - io_update_valid & update_idx == 8'h48 | validArray[72], - io_update_valid & update_idx == 8'h47 | validArray[71], - io_update_valid & update_idx == 8'h46 | validArray[70], - io_update_valid & update_idx == 8'h45 | validArray[69], - io_update_valid & update_idx == 8'h44 | validArray[68], - io_update_valid & update_idx == 8'h43 | validArray[67], - io_update_valid & update_idx == 8'h42 | validArray[66], - io_update_valid & update_idx == 8'h41 | validArray[65], - io_update_valid & update_idx == 8'h40 | validArray[64], - io_update_valid & update_idx == 8'h3F | validArray[63], - io_update_valid & update_idx == 8'h3E | validArray[62], - io_update_valid & update_idx == 8'h3D | validArray[61], - io_update_valid & update_idx == 8'h3C | validArray[60], - io_update_valid & update_idx == 8'h3B | validArray[59], - io_update_valid & update_idx == 8'h3A | validArray[58], - io_update_valid & update_idx == 8'h39 | validArray[57], - io_update_valid & update_idx == 8'h38 | validArray[56], - io_update_valid & update_idx == 8'h37 | validArray[55], - io_update_valid & update_idx == 8'h36 | validArray[54], - io_update_valid & update_idx == 8'h35 | validArray[53], - io_update_valid & update_idx == 8'h34 | validArray[52], - io_update_valid & update_idx == 8'h33 | validArray[51], - io_update_valid & update_idx == 8'h32 | validArray[50], - io_update_valid & update_idx == 8'h31 | validArray[49], - io_update_valid & update_idx == 8'h30 | validArray[48], - io_update_valid & update_idx == 8'h2F | validArray[47], - io_update_valid & update_idx == 8'h2E | validArray[46], - io_update_valid & update_idx == 8'h2D | validArray[45], - io_update_valid & update_idx == 8'h2C | validArray[44], - io_update_valid & update_idx == 8'h2B | validArray[43], - io_update_valid & update_idx == 8'h2A | validArray[42], - io_update_valid & update_idx == 8'h29 | validArray[41], - io_update_valid & update_idx == 8'h28 | validArray[40], - io_update_valid & update_idx == 8'h27 | validArray[39], - io_update_valid & update_idx == 8'h26 | validArray[38], - io_update_valid & update_idx == 8'h25 | validArray[37], - io_update_valid & update_idx == 8'h24 | validArray[36], - io_update_valid & update_idx == 8'h23 | validArray[35], - io_update_valid & update_idx == 8'h22 | validArray[34], - io_update_valid & update_idx == 8'h21 | validArray[33], - io_update_valid & update_idx == 8'h20 | validArray[32], - io_update_valid & update_idx == 8'h1F | validArray[31], - io_update_valid & update_idx == 8'h1E | validArray[30], - io_update_valid & update_idx == 8'h1D | validArray[29], - io_update_valid & update_idx == 8'h1C | validArray[28], - io_update_valid & update_idx == 8'h1B | validArray[27], - io_update_valid & update_idx == 8'h1A | validArray[26], - io_update_valid & update_idx == 8'h19 | validArray[25], - io_update_valid & update_idx == 8'h18 | validArray[24], - io_update_valid & update_idx == 8'h17 | validArray[23], - io_update_valid & update_idx == 8'h16 | validArray[22], - io_update_valid & update_idx == 8'h15 | validArray[21], - io_update_valid & update_idx == 8'h14 | validArray[20], - io_update_valid & update_idx == 8'h13 | validArray[19], - io_update_valid & update_idx == 8'h12 | validArray[18], - io_update_valid & update_idx == 8'h11 | validArray[17], - io_update_valid & update_idx == 8'h10 | validArray[16], - io_update_valid & update_idx == 8'hF | validArray[15], - io_update_valid & update_idx == 8'hE | validArray[14], - io_update_valid & update_idx == 8'hD | validArray[13], - io_update_valid & update_idx == 8'hC | validArray[12], - io_update_valid & update_idx == 8'hB | validArray[11], - io_update_valid & update_idx == 8'hA | validArray[10], - io_update_valid & update_idx == 8'h9 | validArray[9], - io_update_valid & update_idx == 8'h8 | validArray[8], - io_update_valid & update_idx == 8'h7 | validArray[7], - io_update_valid & update_idx == 8'h6 | validArray[6], - io_update_valid & update_idx == 8'h5 | validArray[5], - io_update_valid & update_idx == 8'h4 | validArray[4], - io_update_valid & update_idx == 8'h3 | validArray[3], - io_update_valid & update_idx == 8'h2 | validArray[2], - io_update_valid & update_idx == 8'h1 | validArray[1], - io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 - always @(posedge clock or posedge reset) begin - if (reset) - validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 - end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + : io_update_old_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] s1_tag <= {io_req_bits_pc[17], io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist} - ^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 - s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 - s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + ^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43, :211:68] + s1_bank_req_1h_0 <= ~(s0_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :213:33] + s1_bank_req_1h_1 <= s0_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :213:33] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] end end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = - {_RANDOM[4'h0], - _RANDOM[4'h1], - _RANDOM[4'h2], - _RANDOM[4'h3], - _RANDOM[4'h4], - _RANDOM[4'h5], - _RANDOM[4'h6], - _RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 - s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 - s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} - s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68] + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + Folded1WDataModuleTemplate us ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] .clock (clock), .reset (reset), - .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_rdata_0 (_us_io_rdata_0), .io_wen (io_update_uValid), - .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_waddr (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_wdata (io_update_u), .io_resetEn (io_update_reset_u) ); - FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_21 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[7:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[7:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_21 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & s0_idx[0]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[7:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[7:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + WrBypass_41 wrbypass ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] .clock (clock), .reset (reset), .io_wen (io_update_valid), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 - .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] + .io_write_data_0 (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] .io_hit (_wrbypass_io_hit), .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) ); assign io_resp_valid = - _s1_req_rhit_T[0] + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag - & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53} + & ~_resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33, :217:44, :231:62, :234:{50,53}] assign io_resp_bits_ctr = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 - assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:18, :236:18] assign io_resp_bits_target = - (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] endmodule diff --git a/rtl/ITTAGE/ITTageTable_2.sv b/rtl/ITTAGE/ITTageTable_2.sv index 82959f1..3ea8dc8 100644 --- a/rtl/ITTAGE/ITTageTable_2.sv +++ b/rtl/ITTAGE/ITTageTable_2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,707 +55,168 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTageTable_2( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_req_bits_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_update_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +module ITTageTable_2( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_req_bits_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output io_resp_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_ctr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [40:0] io_resp_bits_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_update_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_update_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_correct, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_alloc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [1:0] io_update_oldCtr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_uValid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_reset_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_old_target // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] ); - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 - reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 - reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [8:0] update_wdata_tag = + wire _resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_1_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_0_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _us_io_rdata_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + reg [8:0] s1_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:211:68] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + wire [8:0] update_tag = io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist - ^ {io_update_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 - assign _resp_invalid_by_write_WIRE = + ^ {io_update_folded_hist_hist_4_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43] + assign _resp_invalid_by_write_T_2 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 - & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 - wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 - wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 - wire [1:0] old_ctr = - _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 - wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 - wire [1:0] update_wdata_ctr = + & s1_bank_has_write_on_this_req_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33, :239:48] + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :254:33] + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :254:33] + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24, :276:20] + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20] + wire [1:0] update_wdata_ctr = io_update_alloc ? 2'h2 : (&old_ctr) & io_update_correct ? 2'h3 : update_wdata_ctr_oldSatNotTaken & ~io_update_correct ? 2'h0 - : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 - wire [38:0] update_wdata_target = + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20, :278:28] + wire [40:0] update_wdata_target = io_update_alloc | update_wdata_ctr_oldSatNotTaken ? io_update_target - : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} - wire [511:0] _validArray_T = - {io_update_valid & (&update_idx) | validArray[511], - io_update_valid & update_idx == 9'h1FE | validArray[510], - io_update_valid & update_idx == 9'h1FD | validArray[509], - io_update_valid & update_idx == 9'h1FC | validArray[508], - io_update_valid & update_idx == 9'h1FB | validArray[507], - io_update_valid & update_idx == 9'h1FA | validArray[506], - io_update_valid & update_idx == 9'h1F9 | validArray[505], - io_update_valid & update_idx == 9'h1F8 | validArray[504], - io_update_valid & update_idx == 9'h1F7 | validArray[503], - io_update_valid & update_idx == 9'h1F6 | validArray[502], - io_update_valid & update_idx == 9'h1F5 | validArray[501], - io_update_valid & update_idx == 9'h1F4 | validArray[500], - io_update_valid & update_idx == 9'h1F3 | validArray[499], - io_update_valid & update_idx == 9'h1F2 | validArray[498], - io_update_valid & update_idx == 9'h1F1 | validArray[497], - io_update_valid & update_idx == 9'h1F0 | validArray[496], - io_update_valid & update_idx == 9'h1EF | validArray[495], - io_update_valid & update_idx == 9'h1EE | validArray[494], - io_update_valid & update_idx == 9'h1ED | validArray[493], - io_update_valid & update_idx == 9'h1EC | validArray[492], - io_update_valid & update_idx == 9'h1EB | validArray[491], - io_update_valid & update_idx == 9'h1EA | validArray[490], - io_update_valid & update_idx == 9'h1E9 | validArray[489], - io_update_valid & update_idx == 9'h1E8 | validArray[488], - io_update_valid & update_idx == 9'h1E7 | validArray[487], - io_update_valid & update_idx == 9'h1E6 | validArray[486], - io_update_valid & update_idx == 9'h1E5 | validArray[485], - io_update_valid & update_idx == 9'h1E4 | validArray[484], - io_update_valid & update_idx == 9'h1E3 | validArray[483], - io_update_valid & update_idx == 9'h1E2 | validArray[482], - io_update_valid & update_idx == 9'h1E1 | validArray[481], - io_update_valid & update_idx == 9'h1E0 | validArray[480], - io_update_valid & update_idx == 9'h1DF | validArray[479], - io_update_valid & update_idx == 9'h1DE | validArray[478], - io_update_valid & update_idx == 9'h1DD | validArray[477], - io_update_valid & update_idx == 9'h1DC | validArray[476], - io_update_valid & update_idx == 9'h1DB | validArray[475], - io_update_valid & update_idx == 9'h1DA | validArray[474], - io_update_valid & update_idx == 9'h1D9 | validArray[473], - io_update_valid & update_idx == 9'h1D8 | validArray[472], - io_update_valid & update_idx == 9'h1D7 | validArray[471], - io_update_valid & update_idx == 9'h1D6 | validArray[470], - io_update_valid & update_idx == 9'h1D5 | validArray[469], - io_update_valid & update_idx == 9'h1D4 | validArray[468], - io_update_valid & update_idx == 9'h1D3 | validArray[467], - io_update_valid & update_idx == 9'h1D2 | validArray[466], - io_update_valid & update_idx == 9'h1D1 | validArray[465], - io_update_valid & update_idx == 9'h1D0 | validArray[464], - io_update_valid & update_idx == 9'h1CF | validArray[463], - io_update_valid & update_idx == 9'h1CE | validArray[462], - io_update_valid & update_idx == 9'h1CD | validArray[461], - io_update_valid & update_idx == 9'h1CC | validArray[460], - io_update_valid & update_idx == 9'h1CB | validArray[459], - io_update_valid & update_idx == 9'h1CA | validArray[458], - io_update_valid & update_idx == 9'h1C9 | validArray[457], - io_update_valid & update_idx == 9'h1C8 | validArray[456], - io_update_valid & update_idx == 9'h1C7 | validArray[455], - io_update_valid & update_idx == 9'h1C6 | validArray[454], - io_update_valid & update_idx == 9'h1C5 | validArray[453], - io_update_valid & update_idx == 9'h1C4 | validArray[452], - io_update_valid & update_idx == 9'h1C3 | validArray[451], - io_update_valid & update_idx == 9'h1C2 | validArray[450], - io_update_valid & update_idx == 9'h1C1 | validArray[449], - io_update_valid & update_idx == 9'h1C0 | validArray[448], - io_update_valid & update_idx == 9'h1BF | validArray[447], - io_update_valid & update_idx == 9'h1BE | validArray[446], - io_update_valid & update_idx == 9'h1BD | validArray[445], - io_update_valid & update_idx == 9'h1BC | validArray[444], - io_update_valid & update_idx == 9'h1BB | validArray[443], - io_update_valid & update_idx == 9'h1BA | validArray[442], - io_update_valid & update_idx == 9'h1B9 | validArray[441], - io_update_valid & update_idx == 9'h1B8 | validArray[440], - io_update_valid & update_idx == 9'h1B7 | validArray[439], - io_update_valid & update_idx == 9'h1B6 | validArray[438], - io_update_valid & update_idx == 9'h1B5 | validArray[437], - io_update_valid & update_idx == 9'h1B4 | validArray[436], - io_update_valid & update_idx == 9'h1B3 | validArray[435], - io_update_valid & update_idx == 9'h1B2 | validArray[434], - io_update_valid & update_idx == 9'h1B1 | validArray[433], - io_update_valid & update_idx == 9'h1B0 | validArray[432], - io_update_valid & update_idx == 9'h1AF | validArray[431], - io_update_valid & update_idx == 9'h1AE | validArray[430], - io_update_valid & update_idx == 9'h1AD | validArray[429], - io_update_valid & update_idx == 9'h1AC | validArray[428], - io_update_valid & update_idx == 9'h1AB | validArray[427], - io_update_valid & update_idx == 9'h1AA | validArray[426], - io_update_valid & update_idx == 9'h1A9 | validArray[425], - io_update_valid & update_idx == 9'h1A8 | validArray[424], - io_update_valid & update_idx == 9'h1A7 | validArray[423], - io_update_valid & update_idx == 9'h1A6 | validArray[422], - io_update_valid & update_idx == 9'h1A5 | validArray[421], - io_update_valid & update_idx == 9'h1A4 | validArray[420], - io_update_valid & update_idx == 9'h1A3 | validArray[419], - io_update_valid & update_idx == 9'h1A2 | validArray[418], - io_update_valid & update_idx == 9'h1A1 | validArray[417], - io_update_valid & update_idx == 9'h1A0 | validArray[416], - io_update_valid & update_idx == 9'h19F | validArray[415], - io_update_valid & update_idx == 9'h19E | validArray[414], - io_update_valid & update_idx == 9'h19D | validArray[413], - io_update_valid & update_idx == 9'h19C | validArray[412], - io_update_valid & update_idx == 9'h19B | validArray[411], - io_update_valid & update_idx == 9'h19A | validArray[410], - io_update_valid & update_idx == 9'h199 | validArray[409], - io_update_valid & update_idx == 9'h198 | validArray[408], - io_update_valid & update_idx == 9'h197 | validArray[407], - io_update_valid & update_idx == 9'h196 | validArray[406], - io_update_valid & update_idx == 9'h195 | validArray[405], - io_update_valid & update_idx == 9'h194 | validArray[404], - io_update_valid & update_idx == 9'h193 | validArray[403], - io_update_valid & update_idx == 9'h192 | validArray[402], - io_update_valid & update_idx == 9'h191 | validArray[401], - io_update_valid & update_idx == 9'h190 | validArray[400], - io_update_valid & update_idx == 9'h18F | validArray[399], - io_update_valid & update_idx == 9'h18E | validArray[398], - io_update_valid & update_idx == 9'h18D | validArray[397], - io_update_valid & update_idx == 9'h18C | validArray[396], - io_update_valid & update_idx == 9'h18B | validArray[395], - io_update_valid & update_idx == 9'h18A | validArray[394], - io_update_valid & update_idx == 9'h189 | validArray[393], - io_update_valid & update_idx == 9'h188 | validArray[392], - io_update_valid & update_idx == 9'h187 | validArray[391], - io_update_valid & update_idx == 9'h186 | validArray[390], - io_update_valid & update_idx == 9'h185 | validArray[389], - io_update_valid & update_idx == 9'h184 | validArray[388], - io_update_valid & update_idx == 9'h183 | validArray[387], - io_update_valid & update_idx == 9'h182 | validArray[386], - io_update_valid & update_idx == 9'h181 | validArray[385], - io_update_valid & update_idx == 9'h180 | validArray[384], - io_update_valid & update_idx == 9'h17F | validArray[383], - io_update_valid & update_idx == 9'h17E | validArray[382], - io_update_valid & update_idx == 9'h17D | validArray[381], - io_update_valid & update_idx == 9'h17C | validArray[380], - io_update_valid & update_idx == 9'h17B | validArray[379], - io_update_valid & update_idx == 9'h17A | validArray[378], - io_update_valid & update_idx == 9'h179 | validArray[377], - io_update_valid & update_idx == 9'h178 | validArray[376], - io_update_valid & update_idx == 9'h177 | validArray[375], - io_update_valid & update_idx == 9'h176 | validArray[374], - io_update_valid & update_idx == 9'h175 | validArray[373], - io_update_valid & update_idx == 9'h174 | validArray[372], - io_update_valid & update_idx == 9'h173 | validArray[371], - io_update_valid & update_idx == 9'h172 | validArray[370], - io_update_valid & update_idx == 9'h171 | validArray[369], - io_update_valid & update_idx == 9'h170 | validArray[368], - io_update_valid & update_idx == 9'h16F | validArray[367], - io_update_valid & update_idx == 9'h16E | validArray[366], - io_update_valid & update_idx == 9'h16D | validArray[365], - io_update_valid & update_idx == 9'h16C | validArray[364], - io_update_valid & update_idx == 9'h16B | validArray[363], - io_update_valid & update_idx == 9'h16A | validArray[362], - io_update_valid & update_idx == 9'h169 | validArray[361], - io_update_valid & update_idx == 9'h168 | validArray[360], - io_update_valid & update_idx == 9'h167 | validArray[359], - io_update_valid & update_idx == 9'h166 | validArray[358], - io_update_valid & update_idx == 9'h165 | validArray[357], - io_update_valid & update_idx == 9'h164 | validArray[356], - io_update_valid & update_idx == 9'h163 | validArray[355], - io_update_valid & update_idx == 9'h162 | validArray[354], - io_update_valid & update_idx == 9'h161 | validArray[353], - io_update_valid & update_idx == 9'h160 | validArray[352], - io_update_valid & update_idx == 9'h15F | validArray[351], - io_update_valid & update_idx == 9'h15E | validArray[350], - io_update_valid & update_idx == 9'h15D | validArray[349], - io_update_valid & update_idx == 9'h15C | validArray[348], - io_update_valid & update_idx == 9'h15B | validArray[347], - io_update_valid & update_idx == 9'h15A | validArray[346], - io_update_valid & update_idx == 9'h159 | validArray[345], - io_update_valid & update_idx == 9'h158 | validArray[344], - io_update_valid & update_idx == 9'h157 | validArray[343], - io_update_valid & update_idx == 9'h156 | validArray[342], - io_update_valid & update_idx == 9'h155 | validArray[341], - io_update_valid & update_idx == 9'h154 | validArray[340], - io_update_valid & update_idx == 9'h153 | validArray[339], - io_update_valid & update_idx == 9'h152 | validArray[338], - io_update_valid & update_idx == 9'h151 | validArray[337], - io_update_valid & update_idx == 9'h150 | validArray[336], - io_update_valid & update_idx == 9'h14F | validArray[335], - io_update_valid & update_idx == 9'h14E | validArray[334], - io_update_valid & update_idx == 9'h14D | validArray[333], - io_update_valid & update_idx == 9'h14C | validArray[332], - io_update_valid & update_idx == 9'h14B | validArray[331], - io_update_valid & update_idx == 9'h14A | validArray[330], - io_update_valid & update_idx == 9'h149 | validArray[329], - io_update_valid & update_idx == 9'h148 | validArray[328], - io_update_valid & update_idx == 9'h147 | validArray[327], - io_update_valid & update_idx == 9'h146 | validArray[326], - io_update_valid & update_idx == 9'h145 | validArray[325], - io_update_valid & update_idx == 9'h144 | validArray[324], - io_update_valid & update_idx == 9'h143 | validArray[323], - io_update_valid & update_idx == 9'h142 | validArray[322], - io_update_valid & update_idx == 9'h141 | validArray[321], - io_update_valid & update_idx == 9'h140 | validArray[320], - io_update_valid & update_idx == 9'h13F | validArray[319], - io_update_valid & update_idx == 9'h13E | validArray[318], - io_update_valid & update_idx == 9'h13D | validArray[317], - io_update_valid & update_idx == 9'h13C | validArray[316], - io_update_valid & update_idx == 9'h13B | validArray[315], - io_update_valid & update_idx == 9'h13A | validArray[314], - io_update_valid & update_idx == 9'h139 | validArray[313], - io_update_valid & update_idx == 9'h138 | validArray[312], - io_update_valid & update_idx == 9'h137 | validArray[311], - io_update_valid & update_idx == 9'h136 | validArray[310], - io_update_valid & update_idx == 9'h135 | validArray[309], - io_update_valid & update_idx == 9'h134 | validArray[308], - io_update_valid & update_idx == 9'h133 | validArray[307], - io_update_valid & update_idx == 9'h132 | validArray[306], - io_update_valid & update_idx == 9'h131 | validArray[305], - io_update_valid & update_idx == 9'h130 | validArray[304], - io_update_valid & update_idx == 9'h12F | validArray[303], - io_update_valid & update_idx == 9'h12E | validArray[302], - io_update_valid & update_idx == 9'h12D | validArray[301], - io_update_valid & update_idx == 9'h12C | validArray[300], - io_update_valid & update_idx == 9'h12B | validArray[299], - io_update_valid & update_idx == 9'h12A | validArray[298], - io_update_valid & update_idx == 9'h129 | validArray[297], - io_update_valid & update_idx == 9'h128 | validArray[296], - io_update_valid & update_idx == 9'h127 | validArray[295], - io_update_valid & update_idx == 9'h126 | validArray[294], - io_update_valid & update_idx == 9'h125 | validArray[293], - io_update_valid & update_idx == 9'h124 | validArray[292], - io_update_valid & update_idx == 9'h123 | validArray[291], - io_update_valid & update_idx == 9'h122 | validArray[290], - io_update_valid & update_idx == 9'h121 | validArray[289], - io_update_valid & update_idx == 9'h120 | validArray[288], - io_update_valid & update_idx == 9'h11F | validArray[287], - io_update_valid & update_idx == 9'h11E | validArray[286], - io_update_valid & update_idx == 9'h11D | validArray[285], - io_update_valid & update_idx == 9'h11C | validArray[284], - io_update_valid & update_idx == 9'h11B | validArray[283], - io_update_valid & update_idx == 9'h11A | validArray[282], - io_update_valid & update_idx == 9'h119 | validArray[281], - io_update_valid & update_idx == 9'h118 | validArray[280], - io_update_valid & update_idx == 9'h117 | validArray[279], - io_update_valid & update_idx == 9'h116 | validArray[278], - io_update_valid & update_idx == 9'h115 | validArray[277], - io_update_valid & update_idx == 9'h114 | validArray[276], - io_update_valid & update_idx == 9'h113 | validArray[275], - io_update_valid & update_idx == 9'h112 | validArray[274], - io_update_valid & update_idx == 9'h111 | validArray[273], - io_update_valid & update_idx == 9'h110 | validArray[272], - io_update_valid & update_idx == 9'h10F | validArray[271], - io_update_valid & update_idx == 9'h10E | validArray[270], - io_update_valid & update_idx == 9'h10D | validArray[269], - io_update_valid & update_idx == 9'h10C | validArray[268], - io_update_valid & update_idx == 9'h10B | validArray[267], - io_update_valid & update_idx == 9'h10A | validArray[266], - io_update_valid & update_idx == 9'h109 | validArray[265], - io_update_valid & update_idx == 9'h108 | validArray[264], - io_update_valid & update_idx == 9'h107 | validArray[263], - io_update_valid & update_idx == 9'h106 | validArray[262], - io_update_valid & update_idx == 9'h105 | validArray[261], - io_update_valid & update_idx == 9'h104 | validArray[260], - io_update_valid & update_idx == 9'h103 | validArray[259], - io_update_valid & update_idx == 9'h102 | validArray[258], - io_update_valid & update_idx == 9'h101 | validArray[257], - io_update_valid & update_idx == 9'h100 | validArray[256], - io_update_valid & update_idx == 9'hFF | validArray[255], - io_update_valid & update_idx == 9'hFE | validArray[254], - io_update_valid & update_idx == 9'hFD | validArray[253], - io_update_valid & update_idx == 9'hFC | validArray[252], - io_update_valid & update_idx == 9'hFB | validArray[251], - io_update_valid & update_idx == 9'hFA | validArray[250], - io_update_valid & update_idx == 9'hF9 | validArray[249], - io_update_valid & update_idx == 9'hF8 | validArray[248], - io_update_valid & update_idx == 9'hF7 | validArray[247], - io_update_valid & update_idx == 9'hF6 | validArray[246], - io_update_valid & update_idx == 9'hF5 | validArray[245], - io_update_valid & update_idx == 9'hF4 | validArray[244], - io_update_valid & update_idx == 9'hF3 | validArray[243], - io_update_valid & update_idx == 9'hF2 | validArray[242], - io_update_valid & update_idx == 9'hF1 | validArray[241], - io_update_valid & update_idx == 9'hF0 | validArray[240], - io_update_valid & update_idx == 9'hEF | validArray[239], - io_update_valid & update_idx == 9'hEE | validArray[238], - io_update_valid & update_idx == 9'hED | validArray[237], - io_update_valid & update_idx == 9'hEC | validArray[236], - io_update_valid & update_idx == 9'hEB | validArray[235], - io_update_valid & update_idx == 9'hEA | validArray[234], - io_update_valid & update_idx == 9'hE9 | validArray[233], - io_update_valid & update_idx == 9'hE8 | validArray[232], - io_update_valid & update_idx == 9'hE7 | validArray[231], - io_update_valid & update_idx == 9'hE6 | validArray[230], - io_update_valid & update_idx == 9'hE5 | validArray[229], - io_update_valid & update_idx == 9'hE4 | validArray[228], - io_update_valid & update_idx == 9'hE3 | validArray[227], - io_update_valid & update_idx == 9'hE2 | validArray[226], - io_update_valid & update_idx == 9'hE1 | validArray[225], - io_update_valid & update_idx == 9'hE0 | validArray[224], - io_update_valid & update_idx == 9'hDF | validArray[223], - io_update_valid & update_idx == 9'hDE | validArray[222], - io_update_valid & update_idx == 9'hDD | validArray[221], - io_update_valid & update_idx == 9'hDC | validArray[220], - io_update_valid & update_idx == 9'hDB | validArray[219], - io_update_valid & update_idx == 9'hDA | validArray[218], - io_update_valid & update_idx == 9'hD9 | validArray[217], - io_update_valid & update_idx == 9'hD8 | validArray[216], - io_update_valid & update_idx == 9'hD7 | validArray[215], - io_update_valid & update_idx == 9'hD6 | validArray[214], - io_update_valid & update_idx == 9'hD5 | validArray[213], - io_update_valid & update_idx == 9'hD4 | validArray[212], - io_update_valid & update_idx == 9'hD3 | validArray[211], - io_update_valid & update_idx == 9'hD2 | validArray[210], - io_update_valid & update_idx == 9'hD1 | validArray[209], - io_update_valid & update_idx == 9'hD0 | validArray[208], - io_update_valid & update_idx == 9'hCF | validArray[207], - io_update_valid & update_idx == 9'hCE | validArray[206], - io_update_valid & update_idx == 9'hCD | validArray[205], - io_update_valid & update_idx == 9'hCC | validArray[204], - io_update_valid & update_idx == 9'hCB | validArray[203], - io_update_valid & update_idx == 9'hCA | validArray[202], - io_update_valid & update_idx == 9'hC9 | validArray[201], - io_update_valid & update_idx == 9'hC8 | validArray[200], - io_update_valid & update_idx == 9'hC7 | validArray[199], - io_update_valid & update_idx == 9'hC6 | validArray[198], - io_update_valid & update_idx == 9'hC5 | validArray[197], - io_update_valid & update_idx == 9'hC4 | validArray[196], - io_update_valid & update_idx == 9'hC3 | validArray[195], - io_update_valid & update_idx == 9'hC2 | validArray[194], - io_update_valid & update_idx == 9'hC1 | validArray[193], - io_update_valid & update_idx == 9'hC0 | validArray[192], - io_update_valid & update_idx == 9'hBF | validArray[191], - io_update_valid & update_idx == 9'hBE | validArray[190], - io_update_valid & update_idx == 9'hBD | validArray[189], - io_update_valid & update_idx == 9'hBC | validArray[188], - io_update_valid & update_idx == 9'hBB | validArray[187], - io_update_valid & update_idx == 9'hBA | validArray[186], - io_update_valid & update_idx == 9'hB9 | validArray[185], - io_update_valid & update_idx == 9'hB8 | validArray[184], - io_update_valid & update_idx == 9'hB7 | validArray[183], - io_update_valid & update_idx == 9'hB6 | validArray[182], - io_update_valid & update_idx == 9'hB5 | validArray[181], - io_update_valid & update_idx == 9'hB4 | validArray[180], - io_update_valid & update_idx == 9'hB3 | validArray[179], - io_update_valid & update_idx == 9'hB2 | validArray[178], - io_update_valid & update_idx == 9'hB1 | validArray[177], - io_update_valid & update_idx == 9'hB0 | validArray[176], - io_update_valid & update_idx == 9'hAF | validArray[175], - io_update_valid & update_idx == 9'hAE | validArray[174], - io_update_valid & update_idx == 9'hAD | validArray[173], - io_update_valid & update_idx == 9'hAC | validArray[172], - io_update_valid & update_idx == 9'hAB | validArray[171], - io_update_valid & update_idx == 9'hAA | validArray[170], - io_update_valid & update_idx == 9'hA9 | validArray[169], - io_update_valid & update_idx == 9'hA8 | validArray[168], - io_update_valid & update_idx == 9'hA7 | validArray[167], - io_update_valid & update_idx == 9'hA6 | validArray[166], - io_update_valid & update_idx == 9'hA5 | validArray[165], - io_update_valid & update_idx == 9'hA4 | validArray[164], - io_update_valid & update_idx == 9'hA3 | validArray[163], - io_update_valid & update_idx == 9'hA2 | validArray[162], - io_update_valid & update_idx == 9'hA1 | validArray[161], - io_update_valid & update_idx == 9'hA0 | validArray[160], - io_update_valid & update_idx == 9'h9F | validArray[159], - io_update_valid & update_idx == 9'h9E | validArray[158], - io_update_valid & update_idx == 9'h9D | validArray[157], - io_update_valid & update_idx == 9'h9C | validArray[156], - io_update_valid & update_idx == 9'h9B | validArray[155], - io_update_valid & update_idx == 9'h9A | validArray[154], - io_update_valid & update_idx == 9'h99 | validArray[153], - io_update_valid & update_idx == 9'h98 | validArray[152], - io_update_valid & update_idx == 9'h97 | validArray[151], - io_update_valid & update_idx == 9'h96 | validArray[150], - io_update_valid & update_idx == 9'h95 | validArray[149], - io_update_valid & update_idx == 9'h94 | validArray[148], - io_update_valid & update_idx == 9'h93 | validArray[147], - io_update_valid & update_idx == 9'h92 | validArray[146], - io_update_valid & update_idx == 9'h91 | validArray[145], - io_update_valid & update_idx == 9'h90 | validArray[144], - io_update_valid & update_idx == 9'h8F | validArray[143], - io_update_valid & update_idx == 9'h8E | validArray[142], - io_update_valid & update_idx == 9'h8D | validArray[141], - io_update_valid & update_idx == 9'h8C | validArray[140], - io_update_valid & update_idx == 9'h8B | validArray[139], - io_update_valid & update_idx == 9'h8A | validArray[138], - io_update_valid & update_idx == 9'h89 | validArray[137], - io_update_valid & update_idx == 9'h88 | validArray[136], - io_update_valid & update_idx == 9'h87 | validArray[135], - io_update_valid & update_idx == 9'h86 | validArray[134], - io_update_valid & update_idx == 9'h85 | validArray[133], - io_update_valid & update_idx == 9'h84 | validArray[132], - io_update_valid & update_idx == 9'h83 | validArray[131], - io_update_valid & update_idx == 9'h82 | validArray[130], - io_update_valid & update_idx == 9'h81 | validArray[129], - io_update_valid & update_idx == 9'h80 | validArray[128], - io_update_valid & update_idx == 9'h7F | validArray[127], - io_update_valid & update_idx == 9'h7E | validArray[126], - io_update_valid & update_idx == 9'h7D | validArray[125], - io_update_valid & update_idx == 9'h7C | validArray[124], - io_update_valid & update_idx == 9'h7B | validArray[123], - io_update_valid & update_idx == 9'h7A | validArray[122], - io_update_valid & update_idx == 9'h79 | validArray[121], - io_update_valid & update_idx == 9'h78 | validArray[120], - io_update_valid & update_idx == 9'h77 | validArray[119], - io_update_valid & update_idx == 9'h76 | validArray[118], - io_update_valid & update_idx == 9'h75 | validArray[117], - io_update_valid & update_idx == 9'h74 | validArray[116], - io_update_valid & update_idx == 9'h73 | validArray[115], - io_update_valid & update_idx == 9'h72 | validArray[114], - io_update_valid & update_idx == 9'h71 | validArray[113], - io_update_valid & update_idx == 9'h70 | validArray[112], - io_update_valid & update_idx == 9'h6F | validArray[111], - io_update_valid & update_idx == 9'h6E | validArray[110], - io_update_valid & update_idx == 9'h6D | validArray[109], - io_update_valid & update_idx == 9'h6C | validArray[108], - io_update_valid & update_idx == 9'h6B | validArray[107], - io_update_valid & update_idx == 9'h6A | validArray[106], - io_update_valid & update_idx == 9'h69 | validArray[105], - io_update_valid & update_idx == 9'h68 | validArray[104], - io_update_valid & update_idx == 9'h67 | validArray[103], - io_update_valid & update_idx == 9'h66 | validArray[102], - io_update_valid & update_idx == 9'h65 | validArray[101], - io_update_valid & update_idx == 9'h64 | validArray[100], - io_update_valid & update_idx == 9'h63 | validArray[99], - io_update_valid & update_idx == 9'h62 | validArray[98], - io_update_valid & update_idx == 9'h61 | validArray[97], - io_update_valid & update_idx == 9'h60 | validArray[96], - io_update_valid & update_idx == 9'h5F | validArray[95], - io_update_valid & update_idx == 9'h5E | validArray[94], - io_update_valid & update_idx == 9'h5D | validArray[93], - io_update_valid & update_idx == 9'h5C | validArray[92], - io_update_valid & update_idx == 9'h5B | validArray[91], - io_update_valid & update_idx == 9'h5A | validArray[90], - io_update_valid & update_idx == 9'h59 | validArray[89], - io_update_valid & update_idx == 9'h58 | validArray[88], - io_update_valid & update_idx == 9'h57 | validArray[87], - io_update_valid & update_idx == 9'h56 | validArray[86], - io_update_valid & update_idx == 9'h55 | validArray[85], - io_update_valid & update_idx == 9'h54 | validArray[84], - io_update_valid & update_idx == 9'h53 | validArray[83], - io_update_valid & update_idx == 9'h52 | validArray[82], - io_update_valid & update_idx == 9'h51 | validArray[81], - io_update_valid & update_idx == 9'h50 | validArray[80], - io_update_valid & update_idx == 9'h4F | validArray[79], - io_update_valid & update_idx == 9'h4E | validArray[78], - io_update_valid & update_idx == 9'h4D | validArray[77], - io_update_valid & update_idx == 9'h4C | validArray[76], - io_update_valid & update_idx == 9'h4B | validArray[75], - io_update_valid & update_idx == 9'h4A | validArray[74], - io_update_valid & update_idx == 9'h49 | validArray[73], - io_update_valid & update_idx == 9'h48 | validArray[72], - io_update_valid & update_idx == 9'h47 | validArray[71], - io_update_valid & update_idx == 9'h46 | validArray[70], - io_update_valid & update_idx == 9'h45 | validArray[69], - io_update_valid & update_idx == 9'h44 | validArray[68], - io_update_valid & update_idx == 9'h43 | validArray[67], - io_update_valid & update_idx == 9'h42 | validArray[66], - io_update_valid & update_idx == 9'h41 | validArray[65], - io_update_valid & update_idx == 9'h40 | validArray[64], - io_update_valid & update_idx == 9'h3F | validArray[63], - io_update_valid & update_idx == 9'h3E | validArray[62], - io_update_valid & update_idx == 9'h3D | validArray[61], - io_update_valid & update_idx == 9'h3C | validArray[60], - io_update_valid & update_idx == 9'h3B | validArray[59], - io_update_valid & update_idx == 9'h3A | validArray[58], - io_update_valid & update_idx == 9'h39 | validArray[57], - io_update_valid & update_idx == 9'h38 | validArray[56], - io_update_valid & update_idx == 9'h37 | validArray[55], - io_update_valid & update_idx == 9'h36 | validArray[54], - io_update_valid & update_idx == 9'h35 | validArray[53], - io_update_valid & update_idx == 9'h34 | validArray[52], - io_update_valid & update_idx == 9'h33 | validArray[51], - io_update_valid & update_idx == 9'h32 | validArray[50], - io_update_valid & update_idx == 9'h31 | validArray[49], - io_update_valid & update_idx == 9'h30 | validArray[48], - io_update_valid & update_idx == 9'h2F | validArray[47], - io_update_valid & update_idx == 9'h2E | validArray[46], - io_update_valid & update_idx == 9'h2D | validArray[45], - io_update_valid & update_idx == 9'h2C | validArray[44], - io_update_valid & update_idx == 9'h2B | validArray[43], - io_update_valid & update_idx == 9'h2A | validArray[42], - io_update_valid & update_idx == 9'h29 | validArray[41], - io_update_valid & update_idx == 9'h28 | validArray[40], - io_update_valid & update_idx == 9'h27 | validArray[39], - io_update_valid & update_idx == 9'h26 | validArray[38], - io_update_valid & update_idx == 9'h25 | validArray[37], - io_update_valid & update_idx == 9'h24 | validArray[36], - io_update_valid & update_idx == 9'h23 | validArray[35], - io_update_valid & update_idx == 9'h22 | validArray[34], - io_update_valid & update_idx == 9'h21 | validArray[33], - io_update_valid & update_idx == 9'h20 | validArray[32], - io_update_valid & update_idx == 9'h1F | validArray[31], - io_update_valid & update_idx == 9'h1E | validArray[30], - io_update_valid & update_idx == 9'h1D | validArray[29], - io_update_valid & update_idx == 9'h1C | validArray[28], - io_update_valid & update_idx == 9'h1B | validArray[27], - io_update_valid & update_idx == 9'h1A | validArray[26], - io_update_valid & update_idx == 9'h19 | validArray[25], - io_update_valid & update_idx == 9'h18 | validArray[24], - io_update_valid & update_idx == 9'h17 | validArray[23], - io_update_valid & update_idx == 9'h16 | validArray[22], - io_update_valid & update_idx == 9'h15 | validArray[21], - io_update_valid & update_idx == 9'h14 | validArray[20], - io_update_valid & update_idx == 9'h13 | validArray[19], - io_update_valid & update_idx == 9'h12 | validArray[18], - io_update_valid & update_idx == 9'h11 | validArray[17], - io_update_valid & update_idx == 9'h10 | validArray[16], - io_update_valid & update_idx == 9'hF | validArray[15], - io_update_valid & update_idx == 9'hE | validArray[14], - io_update_valid & update_idx == 9'hD | validArray[13], - io_update_valid & update_idx == 9'hC | validArray[12], - io_update_valid & update_idx == 9'hB | validArray[11], - io_update_valid & update_idx == 9'hA | validArray[10], - io_update_valid & update_idx == 9'h9 | validArray[9], - io_update_valid & update_idx == 9'h8 | validArray[8], - io_update_valid & update_idx == 9'h7 | validArray[7], - io_update_valid & update_idx == 9'h6 | validArray[6], - io_update_valid & update_idx == 9'h5 | validArray[5], - io_update_valid & update_idx == 9'h4 | validArray[4], - io_update_valid & update_idx == 9'h3 | validArray[3], - io_update_valid & update_idx == 9'h2 | validArray[2], - io_update_valid & update_idx == 9'h1 | validArray[1], - io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 - always @(posedge clock or posedge reset) begin - if (reset) - validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 - end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + : io_update_old_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] s1_tag <= io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist - ^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 - s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 - s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + ^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43, :211:68] + s1_bank_req_1h_0 <= ~(s0_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :213:33] + s1_bank_req_1h_1 <= s0_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :213:33] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] end end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = - {_RANDOM[5'h0], - _RANDOM[5'h1], - _RANDOM[5'h2], - _RANDOM[5'h3], - _RANDOM[5'h4], - _RANDOM[5'h5], - _RANDOM[5'h6], - _RANDOM[5'h7], - _RANDOM[5'h8], - _RANDOM[5'h9], - _RANDOM[5'hA], - _RANDOM[5'hB], - _RANDOM[5'hC], - _RANDOM[5'hD], - _RANDOM[5'hE], - _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 - s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 - s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} - s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68] + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + Folded1WDataModuleTemplate_2 us ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] .clock (clock), .reset (reset), - .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_rdata_0 (_us_io_rdata_0), .io_wen (io_update_uValid), - .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_waddr (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_wdata (io_update_u), .io_resetEn (io_update_reset_u) ); - FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & s0_idx[0]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + WrBypass_43 wrbypass ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] .clock (clock), .reset (reset), .io_wen (io_update_valid), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 - .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] + .io_write_data_0 (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] .io_hit (_wrbypass_io_hit), .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) ); assign io_resp_valid = - _s1_req_rhit_T[0] + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag - & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + & ~_resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33, :217:44, :231:62, :234:{50,53}] assign io_resp_bits_ctr = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 - assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:18, :236:18] assign io_resp_bits_target = - (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] endmodule diff --git a/rtl/ITTAGE/ITTageTable_3.sv b/rtl/ITTAGE/ITTageTable_3.sv index 96b5747..6cab0c1 100644 --- a/rtl/ITTAGE/ITTageTable_3.sv +++ b/rtl/ITTAGE/ITTageTable_3.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,707 +55,168 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTageTable_3( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_req_bits_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_update_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +module ITTageTable_3( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_req_bits_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output io_resp_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_ctr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [40:0] io_resp_bits_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_update_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_update_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_correct, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_alloc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [1:0] io_update_oldCtr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_uValid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_reset_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_old_target // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] ); - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 - reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 - reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [8:0] update_wdata_tag = + wire _resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_1_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_0_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _us_io_rdata_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + reg [8:0] s1_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:211:68] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + wire [8:0] update_tag = io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist - ^ {io_update_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 - assign _resp_invalid_by_write_WIRE = + ^ {io_update_folded_hist_hist_2_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43] + assign _resp_invalid_by_write_T_2 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 - & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 - wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 - wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 - wire [1:0] old_ctr = - _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 - wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 - wire [1:0] update_wdata_ctr = + & s1_bank_has_write_on_this_req_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33, :239:48] + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :254:33] + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :254:33] + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24, :276:20] + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20] + wire [1:0] update_wdata_ctr = io_update_alloc ? 2'h2 : (&old_ctr) & io_update_correct ? 2'h3 : update_wdata_ctr_oldSatNotTaken & ~io_update_correct ? 2'h0 - : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 - wire [38:0] update_wdata_target = + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20, :278:28] + wire [40:0] update_wdata_target = io_update_alloc | update_wdata_ctr_oldSatNotTaken ? io_update_target - : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} - wire [511:0] _validArray_T = - {io_update_valid & (&update_idx) | validArray[511], - io_update_valid & update_idx == 9'h1FE | validArray[510], - io_update_valid & update_idx == 9'h1FD | validArray[509], - io_update_valid & update_idx == 9'h1FC | validArray[508], - io_update_valid & update_idx == 9'h1FB | validArray[507], - io_update_valid & update_idx == 9'h1FA | validArray[506], - io_update_valid & update_idx == 9'h1F9 | validArray[505], - io_update_valid & update_idx == 9'h1F8 | validArray[504], - io_update_valid & update_idx == 9'h1F7 | validArray[503], - io_update_valid & update_idx == 9'h1F6 | validArray[502], - io_update_valid & update_idx == 9'h1F5 | validArray[501], - io_update_valid & update_idx == 9'h1F4 | validArray[500], - io_update_valid & update_idx == 9'h1F3 | validArray[499], - io_update_valid & update_idx == 9'h1F2 | validArray[498], - io_update_valid & update_idx == 9'h1F1 | validArray[497], - io_update_valid & update_idx == 9'h1F0 | validArray[496], - io_update_valid & update_idx == 9'h1EF | validArray[495], - io_update_valid & update_idx == 9'h1EE | validArray[494], - io_update_valid & update_idx == 9'h1ED | validArray[493], - io_update_valid & update_idx == 9'h1EC | validArray[492], - io_update_valid & update_idx == 9'h1EB | validArray[491], - io_update_valid & update_idx == 9'h1EA | validArray[490], - io_update_valid & update_idx == 9'h1E9 | validArray[489], - io_update_valid & update_idx == 9'h1E8 | validArray[488], - io_update_valid & update_idx == 9'h1E7 | validArray[487], - io_update_valid & update_idx == 9'h1E6 | validArray[486], - io_update_valid & update_idx == 9'h1E5 | validArray[485], - io_update_valid & update_idx == 9'h1E4 | validArray[484], - io_update_valid & update_idx == 9'h1E3 | validArray[483], - io_update_valid & update_idx == 9'h1E2 | validArray[482], - io_update_valid & update_idx == 9'h1E1 | validArray[481], - io_update_valid & update_idx == 9'h1E0 | validArray[480], - io_update_valid & update_idx == 9'h1DF | validArray[479], - io_update_valid & update_idx == 9'h1DE | validArray[478], - io_update_valid & update_idx == 9'h1DD | validArray[477], - io_update_valid & update_idx == 9'h1DC | validArray[476], - io_update_valid & update_idx == 9'h1DB | validArray[475], - io_update_valid & update_idx == 9'h1DA | validArray[474], - io_update_valid & update_idx == 9'h1D9 | validArray[473], - io_update_valid & update_idx == 9'h1D8 | validArray[472], - io_update_valid & update_idx == 9'h1D7 | validArray[471], - io_update_valid & update_idx == 9'h1D6 | validArray[470], - io_update_valid & update_idx == 9'h1D5 | validArray[469], - io_update_valid & update_idx == 9'h1D4 | validArray[468], - io_update_valid & update_idx == 9'h1D3 | validArray[467], - io_update_valid & update_idx == 9'h1D2 | validArray[466], - io_update_valid & update_idx == 9'h1D1 | validArray[465], - io_update_valid & update_idx == 9'h1D0 | validArray[464], - io_update_valid & update_idx == 9'h1CF | validArray[463], - io_update_valid & update_idx == 9'h1CE | validArray[462], - io_update_valid & update_idx == 9'h1CD | validArray[461], - io_update_valid & update_idx == 9'h1CC | validArray[460], - io_update_valid & update_idx == 9'h1CB | validArray[459], - io_update_valid & update_idx == 9'h1CA | validArray[458], - io_update_valid & update_idx == 9'h1C9 | validArray[457], - io_update_valid & update_idx == 9'h1C8 | validArray[456], - io_update_valid & update_idx == 9'h1C7 | validArray[455], - io_update_valid & update_idx == 9'h1C6 | validArray[454], - io_update_valid & update_idx == 9'h1C5 | validArray[453], - io_update_valid & update_idx == 9'h1C4 | validArray[452], - io_update_valid & update_idx == 9'h1C3 | validArray[451], - io_update_valid & update_idx == 9'h1C2 | validArray[450], - io_update_valid & update_idx == 9'h1C1 | validArray[449], - io_update_valid & update_idx == 9'h1C0 | validArray[448], - io_update_valid & update_idx == 9'h1BF | validArray[447], - io_update_valid & update_idx == 9'h1BE | validArray[446], - io_update_valid & update_idx == 9'h1BD | validArray[445], - io_update_valid & update_idx == 9'h1BC | validArray[444], - io_update_valid & update_idx == 9'h1BB | validArray[443], - io_update_valid & update_idx == 9'h1BA | validArray[442], - io_update_valid & update_idx == 9'h1B9 | validArray[441], - io_update_valid & update_idx == 9'h1B8 | validArray[440], - io_update_valid & update_idx == 9'h1B7 | validArray[439], - io_update_valid & update_idx == 9'h1B6 | validArray[438], - io_update_valid & update_idx == 9'h1B5 | validArray[437], - io_update_valid & update_idx == 9'h1B4 | validArray[436], - io_update_valid & update_idx == 9'h1B3 | validArray[435], - io_update_valid & update_idx == 9'h1B2 | validArray[434], - io_update_valid & update_idx == 9'h1B1 | validArray[433], - io_update_valid & update_idx == 9'h1B0 | validArray[432], - io_update_valid & update_idx == 9'h1AF | validArray[431], - io_update_valid & update_idx == 9'h1AE | validArray[430], - io_update_valid & update_idx == 9'h1AD | validArray[429], - io_update_valid & update_idx == 9'h1AC | validArray[428], - io_update_valid & update_idx == 9'h1AB | validArray[427], - io_update_valid & update_idx == 9'h1AA | validArray[426], - io_update_valid & update_idx == 9'h1A9 | validArray[425], - io_update_valid & update_idx == 9'h1A8 | validArray[424], - io_update_valid & update_idx == 9'h1A7 | validArray[423], - io_update_valid & update_idx == 9'h1A6 | validArray[422], - io_update_valid & update_idx == 9'h1A5 | validArray[421], - io_update_valid & update_idx == 9'h1A4 | validArray[420], - io_update_valid & update_idx == 9'h1A3 | validArray[419], - io_update_valid & update_idx == 9'h1A2 | validArray[418], - io_update_valid & update_idx == 9'h1A1 | validArray[417], - io_update_valid & update_idx == 9'h1A0 | validArray[416], - io_update_valid & update_idx == 9'h19F | validArray[415], - io_update_valid & update_idx == 9'h19E | validArray[414], - io_update_valid & update_idx == 9'h19D | validArray[413], - io_update_valid & update_idx == 9'h19C | validArray[412], - io_update_valid & update_idx == 9'h19B | validArray[411], - io_update_valid & update_idx == 9'h19A | validArray[410], - io_update_valid & update_idx == 9'h199 | validArray[409], - io_update_valid & update_idx == 9'h198 | validArray[408], - io_update_valid & update_idx == 9'h197 | validArray[407], - io_update_valid & update_idx == 9'h196 | validArray[406], - io_update_valid & update_idx == 9'h195 | validArray[405], - io_update_valid & update_idx == 9'h194 | validArray[404], - io_update_valid & update_idx == 9'h193 | validArray[403], - io_update_valid & update_idx == 9'h192 | validArray[402], - io_update_valid & update_idx == 9'h191 | validArray[401], - io_update_valid & update_idx == 9'h190 | validArray[400], - io_update_valid & update_idx == 9'h18F | validArray[399], - io_update_valid & update_idx == 9'h18E | validArray[398], - io_update_valid & update_idx == 9'h18D | validArray[397], - io_update_valid & update_idx == 9'h18C | validArray[396], - io_update_valid & update_idx == 9'h18B | validArray[395], - io_update_valid & update_idx == 9'h18A | validArray[394], - io_update_valid & update_idx == 9'h189 | validArray[393], - io_update_valid & update_idx == 9'h188 | validArray[392], - io_update_valid & update_idx == 9'h187 | validArray[391], - io_update_valid & update_idx == 9'h186 | validArray[390], - io_update_valid & update_idx == 9'h185 | validArray[389], - io_update_valid & update_idx == 9'h184 | validArray[388], - io_update_valid & update_idx == 9'h183 | validArray[387], - io_update_valid & update_idx == 9'h182 | validArray[386], - io_update_valid & update_idx == 9'h181 | validArray[385], - io_update_valid & update_idx == 9'h180 | validArray[384], - io_update_valid & update_idx == 9'h17F | validArray[383], - io_update_valid & update_idx == 9'h17E | validArray[382], - io_update_valid & update_idx == 9'h17D | validArray[381], - io_update_valid & update_idx == 9'h17C | validArray[380], - io_update_valid & update_idx == 9'h17B | validArray[379], - io_update_valid & update_idx == 9'h17A | validArray[378], - io_update_valid & update_idx == 9'h179 | validArray[377], - io_update_valid & update_idx == 9'h178 | validArray[376], - io_update_valid & update_idx == 9'h177 | validArray[375], - io_update_valid & update_idx == 9'h176 | validArray[374], - io_update_valid & update_idx == 9'h175 | validArray[373], - io_update_valid & update_idx == 9'h174 | validArray[372], - io_update_valid & update_idx == 9'h173 | validArray[371], - io_update_valid & update_idx == 9'h172 | validArray[370], - io_update_valid & update_idx == 9'h171 | validArray[369], - io_update_valid & update_idx == 9'h170 | validArray[368], - io_update_valid & update_idx == 9'h16F | validArray[367], - io_update_valid & update_idx == 9'h16E | validArray[366], - io_update_valid & update_idx == 9'h16D | validArray[365], - io_update_valid & update_idx == 9'h16C | validArray[364], - io_update_valid & update_idx == 9'h16B | validArray[363], - io_update_valid & update_idx == 9'h16A | validArray[362], - io_update_valid & update_idx == 9'h169 | validArray[361], - io_update_valid & update_idx == 9'h168 | validArray[360], - io_update_valid & update_idx == 9'h167 | validArray[359], - io_update_valid & update_idx == 9'h166 | validArray[358], - io_update_valid & update_idx == 9'h165 | validArray[357], - io_update_valid & update_idx == 9'h164 | validArray[356], - io_update_valid & update_idx == 9'h163 | validArray[355], - io_update_valid & update_idx == 9'h162 | validArray[354], - io_update_valid & update_idx == 9'h161 | validArray[353], - io_update_valid & update_idx == 9'h160 | validArray[352], - io_update_valid & update_idx == 9'h15F | validArray[351], - io_update_valid & update_idx == 9'h15E | validArray[350], - io_update_valid & update_idx == 9'h15D | validArray[349], - io_update_valid & update_idx == 9'h15C | validArray[348], - io_update_valid & update_idx == 9'h15B | validArray[347], - io_update_valid & update_idx == 9'h15A | validArray[346], - io_update_valid & update_idx == 9'h159 | validArray[345], - io_update_valid & update_idx == 9'h158 | validArray[344], - io_update_valid & update_idx == 9'h157 | validArray[343], - io_update_valid & update_idx == 9'h156 | validArray[342], - io_update_valid & update_idx == 9'h155 | validArray[341], - io_update_valid & update_idx == 9'h154 | validArray[340], - io_update_valid & update_idx == 9'h153 | validArray[339], - io_update_valid & update_idx == 9'h152 | validArray[338], - io_update_valid & update_idx == 9'h151 | validArray[337], - io_update_valid & update_idx == 9'h150 | validArray[336], - io_update_valid & update_idx == 9'h14F | validArray[335], - io_update_valid & update_idx == 9'h14E | validArray[334], - io_update_valid & update_idx == 9'h14D | validArray[333], - io_update_valid & update_idx == 9'h14C | validArray[332], - io_update_valid & update_idx == 9'h14B | validArray[331], - io_update_valid & update_idx == 9'h14A | validArray[330], - io_update_valid & update_idx == 9'h149 | validArray[329], - io_update_valid & update_idx == 9'h148 | validArray[328], - io_update_valid & update_idx == 9'h147 | validArray[327], - io_update_valid & update_idx == 9'h146 | validArray[326], - io_update_valid & update_idx == 9'h145 | validArray[325], - io_update_valid & update_idx == 9'h144 | validArray[324], - io_update_valid & update_idx == 9'h143 | validArray[323], - io_update_valid & update_idx == 9'h142 | validArray[322], - io_update_valid & update_idx == 9'h141 | validArray[321], - io_update_valid & update_idx == 9'h140 | validArray[320], - io_update_valid & update_idx == 9'h13F | validArray[319], - io_update_valid & update_idx == 9'h13E | validArray[318], - io_update_valid & update_idx == 9'h13D | validArray[317], - io_update_valid & update_idx == 9'h13C | validArray[316], - io_update_valid & update_idx == 9'h13B | validArray[315], - io_update_valid & update_idx == 9'h13A | validArray[314], - io_update_valid & update_idx == 9'h139 | validArray[313], - io_update_valid & update_idx == 9'h138 | validArray[312], - io_update_valid & update_idx == 9'h137 | validArray[311], - io_update_valid & update_idx == 9'h136 | validArray[310], - io_update_valid & update_idx == 9'h135 | validArray[309], - io_update_valid & update_idx == 9'h134 | validArray[308], - io_update_valid & update_idx == 9'h133 | validArray[307], - io_update_valid & update_idx == 9'h132 | validArray[306], - io_update_valid & update_idx == 9'h131 | validArray[305], - io_update_valid & update_idx == 9'h130 | validArray[304], - io_update_valid & update_idx == 9'h12F | validArray[303], - io_update_valid & update_idx == 9'h12E | validArray[302], - io_update_valid & update_idx == 9'h12D | validArray[301], - io_update_valid & update_idx == 9'h12C | validArray[300], - io_update_valid & update_idx == 9'h12B | validArray[299], - io_update_valid & update_idx == 9'h12A | validArray[298], - io_update_valid & update_idx == 9'h129 | validArray[297], - io_update_valid & update_idx == 9'h128 | validArray[296], - io_update_valid & update_idx == 9'h127 | validArray[295], - io_update_valid & update_idx == 9'h126 | validArray[294], - io_update_valid & update_idx == 9'h125 | validArray[293], - io_update_valid & update_idx == 9'h124 | validArray[292], - io_update_valid & update_idx == 9'h123 | validArray[291], - io_update_valid & update_idx == 9'h122 | validArray[290], - io_update_valid & update_idx == 9'h121 | validArray[289], - io_update_valid & update_idx == 9'h120 | validArray[288], - io_update_valid & update_idx == 9'h11F | validArray[287], - io_update_valid & update_idx == 9'h11E | validArray[286], - io_update_valid & update_idx == 9'h11D | validArray[285], - io_update_valid & update_idx == 9'h11C | validArray[284], - io_update_valid & update_idx == 9'h11B | validArray[283], - io_update_valid & update_idx == 9'h11A | validArray[282], - io_update_valid & update_idx == 9'h119 | validArray[281], - io_update_valid & update_idx == 9'h118 | validArray[280], - io_update_valid & update_idx == 9'h117 | validArray[279], - io_update_valid & update_idx == 9'h116 | validArray[278], - io_update_valid & update_idx == 9'h115 | validArray[277], - io_update_valid & update_idx == 9'h114 | validArray[276], - io_update_valid & update_idx == 9'h113 | validArray[275], - io_update_valid & update_idx == 9'h112 | validArray[274], - io_update_valid & update_idx == 9'h111 | validArray[273], - io_update_valid & update_idx == 9'h110 | validArray[272], - io_update_valid & update_idx == 9'h10F | validArray[271], - io_update_valid & update_idx == 9'h10E | validArray[270], - io_update_valid & update_idx == 9'h10D | validArray[269], - io_update_valid & update_idx == 9'h10C | validArray[268], - io_update_valid & update_idx == 9'h10B | validArray[267], - io_update_valid & update_idx == 9'h10A | validArray[266], - io_update_valid & update_idx == 9'h109 | validArray[265], - io_update_valid & update_idx == 9'h108 | validArray[264], - io_update_valid & update_idx == 9'h107 | validArray[263], - io_update_valid & update_idx == 9'h106 | validArray[262], - io_update_valid & update_idx == 9'h105 | validArray[261], - io_update_valid & update_idx == 9'h104 | validArray[260], - io_update_valid & update_idx == 9'h103 | validArray[259], - io_update_valid & update_idx == 9'h102 | validArray[258], - io_update_valid & update_idx == 9'h101 | validArray[257], - io_update_valid & update_idx == 9'h100 | validArray[256], - io_update_valid & update_idx == 9'hFF | validArray[255], - io_update_valid & update_idx == 9'hFE | validArray[254], - io_update_valid & update_idx == 9'hFD | validArray[253], - io_update_valid & update_idx == 9'hFC | validArray[252], - io_update_valid & update_idx == 9'hFB | validArray[251], - io_update_valid & update_idx == 9'hFA | validArray[250], - io_update_valid & update_idx == 9'hF9 | validArray[249], - io_update_valid & update_idx == 9'hF8 | validArray[248], - io_update_valid & update_idx == 9'hF7 | validArray[247], - io_update_valid & update_idx == 9'hF6 | validArray[246], - io_update_valid & update_idx == 9'hF5 | validArray[245], - io_update_valid & update_idx == 9'hF4 | validArray[244], - io_update_valid & update_idx == 9'hF3 | validArray[243], - io_update_valid & update_idx == 9'hF2 | validArray[242], - io_update_valid & update_idx == 9'hF1 | validArray[241], - io_update_valid & update_idx == 9'hF0 | validArray[240], - io_update_valid & update_idx == 9'hEF | validArray[239], - io_update_valid & update_idx == 9'hEE | validArray[238], - io_update_valid & update_idx == 9'hED | validArray[237], - io_update_valid & update_idx == 9'hEC | validArray[236], - io_update_valid & update_idx == 9'hEB | validArray[235], - io_update_valid & update_idx == 9'hEA | validArray[234], - io_update_valid & update_idx == 9'hE9 | validArray[233], - io_update_valid & update_idx == 9'hE8 | validArray[232], - io_update_valid & update_idx == 9'hE7 | validArray[231], - io_update_valid & update_idx == 9'hE6 | validArray[230], - io_update_valid & update_idx == 9'hE5 | validArray[229], - io_update_valid & update_idx == 9'hE4 | validArray[228], - io_update_valid & update_idx == 9'hE3 | validArray[227], - io_update_valid & update_idx == 9'hE2 | validArray[226], - io_update_valid & update_idx == 9'hE1 | validArray[225], - io_update_valid & update_idx == 9'hE0 | validArray[224], - io_update_valid & update_idx == 9'hDF | validArray[223], - io_update_valid & update_idx == 9'hDE | validArray[222], - io_update_valid & update_idx == 9'hDD | validArray[221], - io_update_valid & update_idx == 9'hDC | validArray[220], - io_update_valid & update_idx == 9'hDB | validArray[219], - io_update_valid & update_idx == 9'hDA | validArray[218], - io_update_valid & update_idx == 9'hD9 | validArray[217], - io_update_valid & update_idx == 9'hD8 | validArray[216], - io_update_valid & update_idx == 9'hD7 | validArray[215], - io_update_valid & update_idx == 9'hD6 | validArray[214], - io_update_valid & update_idx == 9'hD5 | validArray[213], - io_update_valid & update_idx == 9'hD4 | validArray[212], - io_update_valid & update_idx == 9'hD3 | validArray[211], - io_update_valid & update_idx == 9'hD2 | validArray[210], - io_update_valid & update_idx == 9'hD1 | validArray[209], - io_update_valid & update_idx == 9'hD0 | validArray[208], - io_update_valid & update_idx == 9'hCF | validArray[207], - io_update_valid & update_idx == 9'hCE | validArray[206], - io_update_valid & update_idx == 9'hCD | validArray[205], - io_update_valid & update_idx == 9'hCC | validArray[204], - io_update_valid & update_idx == 9'hCB | validArray[203], - io_update_valid & update_idx == 9'hCA | validArray[202], - io_update_valid & update_idx == 9'hC9 | validArray[201], - io_update_valid & update_idx == 9'hC8 | validArray[200], - io_update_valid & update_idx == 9'hC7 | validArray[199], - io_update_valid & update_idx == 9'hC6 | validArray[198], - io_update_valid & update_idx == 9'hC5 | validArray[197], - io_update_valid & update_idx == 9'hC4 | validArray[196], - io_update_valid & update_idx == 9'hC3 | validArray[195], - io_update_valid & update_idx == 9'hC2 | validArray[194], - io_update_valid & update_idx == 9'hC1 | validArray[193], - io_update_valid & update_idx == 9'hC0 | validArray[192], - io_update_valid & update_idx == 9'hBF | validArray[191], - io_update_valid & update_idx == 9'hBE | validArray[190], - io_update_valid & update_idx == 9'hBD | validArray[189], - io_update_valid & update_idx == 9'hBC | validArray[188], - io_update_valid & update_idx == 9'hBB | validArray[187], - io_update_valid & update_idx == 9'hBA | validArray[186], - io_update_valid & update_idx == 9'hB9 | validArray[185], - io_update_valid & update_idx == 9'hB8 | validArray[184], - io_update_valid & update_idx == 9'hB7 | validArray[183], - io_update_valid & update_idx == 9'hB6 | validArray[182], - io_update_valid & update_idx == 9'hB5 | validArray[181], - io_update_valid & update_idx == 9'hB4 | validArray[180], - io_update_valid & update_idx == 9'hB3 | validArray[179], - io_update_valid & update_idx == 9'hB2 | validArray[178], - io_update_valid & update_idx == 9'hB1 | validArray[177], - io_update_valid & update_idx == 9'hB0 | validArray[176], - io_update_valid & update_idx == 9'hAF | validArray[175], - io_update_valid & update_idx == 9'hAE | validArray[174], - io_update_valid & update_idx == 9'hAD | validArray[173], - io_update_valid & update_idx == 9'hAC | validArray[172], - io_update_valid & update_idx == 9'hAB | validArray[171], - io_update_valid & update_idx == 9'hAA | validArray[170], - io_update_valid & update_idx == 9'hA9 | validArray[169], - io_update_valid & update_idx == 9'hA8 | validArray[168], - io_update_valid & update_idx == 9'hA7 | validArray[167], - io_update_valid & update_idx == 9'hA6 | validArray[166], - io_update_valid & update_idx == 9'hA5 | validArray[165], - io_update_valid & update_idx == 9'hA4 | validArray[164], - io_update_valid & update_idx == 9'hA3 | validArray[163], - io_update_valid & update_idx == 9'hA2 | validArray[162], - io_update_valid & update_idx == 9'hA1 | validArray[161], - io_update_valid & update_idx == 9'hA0 | validArray[160], - io_update_valid & update_idx == 9'h9F | validArray[159], - io_update_valid & update_idx == 9'h9E | validArray[158], - io_update_valid & update_idx == 9'h9D | validArray[157], - io_update_valid & update_idx == 9'h9C | validArray[156], - io_update_valid & update_idx == 9'h9B | validArray[155], - io_update_valid & update_idx == 9'h9A | validArray[154], - io_update_valid & update_idx == 9'h99 | validArray[153], - io_update_valid & update_idx == 9'h98 | validArray[152], - io_update_valid & update_idx == 9'h97 | validArray[151], - io_update_valid & update_idx == 9'h96 | validArray[150], - io_update_valid & update_idx == 9'h95 | validArray[149], - io_update_valid & update_idx == 9'h94 | validArray[148], - io_update_valid & update_idx == 9'h93 | validArray[147], - io_update_valid & update_idx == 9'h92 | validArray[146], - io_update_valid & update_idx == 9'h91 | validArray[145], - io_update_valid & update_idx == 9'h90 | validArray[144], - io_update_valid & update_idx == 9'h8F | validArray[143], - io_update_valid & update_idx == 9'h8E | validArray[142], - io_update_valid & update_idx == 9'h8D | validArray[141], - io_update_valid & update_idx == 9'h8C | validArray[140], - io_update_valid & update_idx == 9'h8B | validArray[139], - io_update_valid & update_idx == 9'h8A | validArray[138], - io_update_valid & update_idx == 9'h89 | validArray[137], - io_update_valid & update_idx == 9'h88 | validArray[136], - io_update_valid & update_idx == 9'h87 | validArray[135], - io_update_valid & update_idx == 9'h86 | validArray[134], - io_update_valid & update_idx == 9'h85 | validArray[133], - io_update_valid & update_idx == 9'h84 | validArray[132], - io_update_valid & update_idx == 9'h83 | validArray[131], - io_update_valid & update_idx == 9'h82 | validArray[130], - io_update_valid & update_idx == 9'h81 | validArray[129], - io_update_valid & update_idx == 9'h80 | validArray[128], - io_update_valid & update_idx == 9'h7F | validArray[127], - io_update_valid & update_idx == 9'h7E | validArray[126], - io_update_valid & update_idx == 9'h7D | validArray[125], - io_update_valid & update_idx == 9'h7C | validArray[124], - io_update_valid & update_idx == 9'h7B | validArray[123], - io_update_valid & update_idx == 9'h7A | validArray[122], - io_update_valid & update_idx == 9'h79 | validArray[121], - io_update_valid & update_idx == 9'h78 | validArray[120], - io_update_valid & update_idx == 9'h77 | validArray[119], - io_update_valid & update_idx == 9'h76 | validArray[118], - io_update_valid & update_idx == 9'h75 | validArray[117], - io_update_valid & update_idx == 9'h74 | validArray[116], - io_update_valid & update_idx == 9'h73 | validArray[115], - io_update_valid & update_idx == 9'h72 | validArray[114], - io_update_valid & update_idx == 9'h71 | validArray[113], - io_update_valid & update_idx == 9'h70 | validArray[112], - io_update_valid & update_idx == 9'h6F | validArray[111], - io_update_valid & update_idx == 9'h6E | validArray[110], - io_update_valid & update_idx == 9'h6D | validArray[109], - io_update_valid & update_idx == 9'h6C | validArray[108], - io_update_valid & update_idx == 9'h6B | validArray[107], - io_update_valid & update_idx == 9'h6A | validArray[106], - io_update_valid & update_idx == 9'h69 | validArray[105], - io_update_valid & update_idx == 9'h68 | validArray[104], - io_update_valid & update_idx == 9'h67 | validArray[103], - io_update_valid & update_idx == 9'h66 | validArray[102], - io_update_valid & update_idx == 9'h65 | validArray[101], - io_update_valid & update_idx == 9'h64 | validArray[100], - io_update_valid & update_idx == 9'h63 | validArray[99], - io_update_valid & update_idx == 9'h62 | validArray[98], - io_update_valid & update_idx == 9'h61 | validArray[97], - io_update_valid & update_idx == 9'h60 | validArray[96], - io_update_valid & update_idx == 9'h5F | validArray[95], - io_update_valid & update_idx == 9'h5E | validArray[94], - io_update_valid & update_idx == 9'h5D | validArray[93], - io_update_valid & update_idx == 9'h5C | validArray[92], - io_update_valid & update_idx == 9'h5B | validArray[91], - io_update_valid & update_idx == 9'h5A | validArray[90], - io_update_valid & update_idx == 9'h59 | validArray[89], - io_update_valid & update_idx == 9'h58 | validArray[88], - io_update_valid & update_idx == 9'h57 | validArray[87], - io_update_valid & update_idx == 9'h56 | validArray[86], - io_update_valid & update_idx == 9'h55 | validArray[85], - io_update_valid & update_idx == 9'h54 | validArray[84], - io_update_valid & update_idx == 9'h53 | validArray[83], - io_update_valid & update_idx == 9'h52 | validArray[82], - io_update_valid & update_idx == 9'h51 | validArray[81], - io_update_valid & update_idx == 9'h50 | validArray[80], - io_update_valid & update_idx == 9'h4F | validArray[79], - io_update_valid & update_idx == 9'h4E | validArray[78], - io_update_valid & update_idx == 9'h4D | validArray[77], - io_update_valid & update_idx == 9'h4C | validArray[76], - io_update_valid & update_idx == 9'h4B | validArray[75], - io_update_valid & update_idx == 9'h4A | validArray[74], - io_update_valid & update_idx == 9'h49 | validArray[73], - io_update_valid & update_idx == 9'h48 | validArray[72], - io_update_valid & update_idx == 9'h47 | validArray[71], - io_update_valid & update_idx == 9'h46 | validArray[70], - io_update_valid & update_idx == 9'h45 | validArray[69], - io_update_valid & update_idx == 9'h44 | validArray[68], - io_update_valid & update_idx == 9'h43 | validArray[67], - io_update_valid & update_idx == 9'h42 | validArray[66], - io_update_valid & update_idx == 9'h41 | validArray[65], - io_update_valid & update_idx == 9'h40 | validArray[64], - io_update_valid & update_idx == 9'h3F | validArray[63], - io_update_valid & update_idx == 9'h3E | validArray[62], - io_update_valid & update_idx == 9'h3D | validArray[61], - io_update_valid & update_idx == 9'h3C | validArray[60], - io_update_valid & update_idx == 9'h3B | validArray[59], - io_update_valid & update_idx == 9'h3A | validArray[58], - io_update_valid & update_idx == 9'h39 | validArray[57], - io_update_valid & update_idx == 9'h38 | validArray[56], - io_update_valid & update_idx == 9'h37 | validArray[55], - io_update_valid & update_idx == 9'h36 | validArray[54], - io_update_valid & update_idx == 9'h35 | validArray[53], - io_update_valid & update_idx == 9'h34 | validArray[52], - io_update_valid & update_idx == 9'h33 | validArray[51], - io_update_valid & update_idx == 9'h32 | validArray[50], - io_update_valid & update_idx == 9'h31 | validArray[49], - io_update_valid & update_idx == 9'h30 | validArray[48], - io_update_valid & update_idx == 9'h2F | validArray[47], - io_update_valid & update_idx == 9'h2E | validArray[46], - io_update_valid & update_idx == 9'h2D | validArray[45], - io_update_valid & update_idx == 9'h2C | validArray[44], - io_update_valid & update_idx == 9'h2B | validArray[43], - io_update_valid & update_idx == 9'h2A | validArray[42], - io_update_valid & update_idx == 9'h29 | validArray[41], - io_update_valid & update_idx == 9'h28 | validArray[40], - io_update_valid & update_idx == 9'h27 | validArray[39], - io_update_valid & update_idx == 9'h26 | validArray[38], - io_update_valid & update_idx == 9'h25 | validArray[37], - io_update_valid & update_idx == 9'h24 | validArray[36], - io_update_valid & update_idx == 9'h23 | validArray[35], - io_update_valid & update_idx == 9'h22 | validArray[34], - io_update_valid & update_idx == 9'h21 | validArray[33], - io_update_valid & update_idx == 9'h20 | validArray[32], - io_update_valid & update_idx == 9'h1F | validArray[31], - io_update_valid & update_idx == 9'h1E | validArray[30], - io_update_valid & update_idx == 9'h1D | validArray[29], - io_update_valid & update_idx == 9'h1C | validArray[28], - io_update_valid & update_idx == 9'h1B | validArray[27], - io_update_valid & update_idx == 9'h1A | validArray[26], - io_update_valid & update_idx == 9'h19 | validArray[25], - io_update_valid & update_idx == 9'h18 | validArray[24], - io_update_valid & update_idx == 9'h17 | validArray[23], - io_update_valid & update_idx == 9'h16 | validArray[22], - io_update_valid & update_idx == 9'h15 | validArray[21], - io_update_valid & update_idx == 9'h14 | validArray[20], - io_update_valid & update_idx == 9'h13 | validArray[19], - io_update_valid & update_idx == 9'h12 | validArray[18], - io_update_valid & update_idx == 9'h11 | validArray[17], - io_update_valid & update_idx == 9'h10 | validArray[16], - io_update_valid & update_idx == 9'hF | validArray[15], - io_update_valid & update_idx == 9'hE | validArray[14], - io_update_valid & update_idx == 9'hD | validArray[13], - io_update_valid & update_idx == 9'hC | validArray[12], - io_update_valid & update_idx == 9'hB | validArray[11], - io_update_valid & update_idx == 9'hA | validArray[10], - io_update_valid & update_idx == 9'h9 | validArray[9], - io_update_valid & update_idx == 9'h8 | validArray[8], - io_update_valid & update_idx == 9'h7 | validArray[7], - io_update_valid & update_idx == 9'h6 | validArray[6], - io_update_valid & update_idx == 9'h5 | validArray[5], - io_update_valid & update_idx == 9'h4 | validArray[4], - io_update_valid & update_idx == 9'h3 | validArray[3], - io_update_valid & update_idx == 9'h2 | validArray[2], - io_update_valid & update_idx == 9'h1 | validArray[1], - io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 - always @(posedge clock or posedge reset) begin - if (reset) - validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 - end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + : io_update_old_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] s1_tag <= io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist - ^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 - s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 - s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + ^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43, :211:68] + s1_bank_req_1h_0 <= ~(s0_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :213:33] + s1_bank_req_1h_1 <= s0_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :213:33] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] end end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = - {_RANDOM[5'h0], - _RANDOM[5'h1], - _RANDOM[5'h2], - _RANDOM[5'h3], - _RANDOM[5'h4], - _RANDOM[5'h5], - _RANDOM[5'h6], - _RANDOM[5'h7], - _RANDOM[5'h8], - _RANDOM[5'h9], - _RANDOM[5'hA], - _RANDOM[5'hB], - _RANDOM[5'hC], - _RANDOM[5'hD], - _RANDOM[5'hE], - _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 - s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 - s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} - s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68] + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + Folded1WDataModuleTemplate_2 us ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] .clock (clock), .reset (reset), - .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_rdata_0 (_us_io_rdata_0), .io_wen (io_update_uValid), - .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_waddr (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_wdata (io_update_u), .io_resetEn (io_update_reset_u) ); - FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & s0_idx[0]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + WrBypass_43 wrbypass ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] .clock (clock), .reset (reset), .io_wen (io_update_valid), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 - .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] + .io_write_data_0 (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] .io_hit (_wrbypass_io_hit), .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) ); assign io_resp_valid = - _s1_req_rhit_T[0] + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag - & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + & ~_resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33, :217:44, :231:62, :234:{50,53}] assign io_resp_bits_ctr = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 - assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:18, :236:18] assign io_resp_bits_target = - (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] endmodule diff --git a/rtl/ITTAGE/ITTageTable_4.sv b/rtl/ITTAGE/ITTageTable_4.sv index a2f43ce..a4806ab 100644 --- a/rtl/ITTAGE/ITTageTable_4.sv +++ b/rtl/ITTAGE/ITTageTable_4.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,707 +55,168 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module ITTageTable_4( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_req_bits_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [8:0] io_update_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +module ITTageTable_4( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_req_bits_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output io_resp_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_ctr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [1:0] io_resp_bits_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + output [40:0] io_resp_bits_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [8:0] io_update_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [7:0] io_update_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_correct, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_alloc, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [1:0] io_update_oldCtr, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_uValid, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input io_update_reset_u, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_target, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] + input [40:0] io_update_old_target // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] ); - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 - wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 - wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 - reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 - reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 - wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 - wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 - wire [8:0] update_wdata_tag = + wire _resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_1_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire [40:0] _table_banks_0_io_r_resp_data_0_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] + wire _us_io_rdata_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + reg [8:0] s1_tag; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:211:68] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48] + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :205:43] + wire [8:0] update_tag = io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist - ^ {io_update_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 - assign _resp_invalid_by_write_WIRE = + ^ {io_update_folded_hist_hist_3_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43] + assign _resp_invalid_by_write_T_2 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 - & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 - wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 - wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 - wire [1:0] old_ctr = - _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 - wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 - wire [1:0] update_wdata_ctr = + & s1_bank_has_write_on_this_req_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:213:33, :239:48] + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :254:33] + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :254:33] + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24, :276:20] + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20] + wire [1:0] update_wdata_ctr = io_update_alloc ? 2'h2 : (&old_ctr) & io_update_correct ? 2'h3 : update_wdata_ctr_oldSatNotTaken & ~io_update_correct ? 2'h0 - : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 - wire [38:0] update_wdata_target = + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:276:20, :278:28] + wire [40:0] update_wdata_target = io_update_alloc | update_wdata_ctr_oldSatNotTaken ? io_update_target - : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} - wire [511:0] _validArray_T = - {io_update_valid & (&update_idx) | validArray[511], - io_update_valid & update_idx == 9'h1FE | validArray[510], - io_update_valid & update_idx == 9'h1FD | validArray[509], - io_update_valid & update_idx == 9'h1FC | validArray[508], - io_update_valid & update_idx == 9'h1FB | validArray[507], - io_update_valid & update_idx == 9'h1FA | validArray[506], - io_update_valid & update_idx == 9'h1F9 | validArray[505], - io_update_valid & update_idx == 9'h1F8 | validArray[504], - io_update_valid & update_idx == 9'h1F7 | validArray[503], - io_update_valid & update_idx == 9'h1F6 | validArray[502], - io_update_valid & update_idx == 9'h1F5 | validArray[501], - io_update_valid & update_idx == 9'h1F4 | validArray[500], - io_update_valid & update_idx == 9'h1F3 | validArray[499], - io_update_valid & update_idx == 9'h1F2 | validArray[498], - io_update_valid & update_idx == 9'h1F1 | validArray[497], - io_update_valid & update_idx == 9'h1F0 | validArray[496], - io_update_valid & update_idx == 9'h1EF | validArray[495], - io_update_valid & update_idx == 9'h1EE | validArray[494], - io_update_valid & update_idx == 9'h1ED | validArray[493], - io_update_valid & update_idx == 9'h1EC | validArray[492], - io_update_valid & update_idx == 9'h1EB | validArray[491], - io_update_valid & update_idx == 9'h1EA | validArray[490], - io_update_valid & update_idx == 9'h1E9 | validArray[489], - io_update_valid & update_idx == 9'h1E8 | validArray[488], - io_update_valid & update_idx == 9'h1E7 | validArray[487], - io_update_valid & update_idx == 9'h1E6 | validArray[486], - io_update_valid & update_idx == 9'h1E5 | validArray[485], - io_update_valid & update_idx == 9'h1E4 | validArray[484], - io_update_valid & update_idx == 9'h1E3 | validArray[483], - io_update_valid & update_idx == 9'h1E2 | validArray[482], - io_update_valid & update_idx == 9'h1E1 | validArray[481], - io_update_valid & update_idx == 9'h1E0 | validArray[480], - io_update_valid & update_idx == 9'h1DF | validArray[479], - io_update_valid & update_idx == 9'h1DE | validArray[478], - io_update_valid & update_idx == 9'h1DD | validArray[477], - io_update_valid & update_idx == 9'h1DC | validArray[476], - io_update_valid & update_idx == 9'h1DB | validArray[475], - io_update_valid & update_idx == 9'h1DA | validArray[474], - io_update_valid & update_idx == 9'h1D9 | validArray[473], - io_update_valid & update_idx == 9'h1D8 | validArray[472], - io_update_valid & update_idx == 9'h1D7 | validArray[471], - io_update_valid & update_idx == 9'h1D6 | validArray[470], - io_update_valid & update_idx == 9'h1D5 | validArray[469], - io_update_valid & update_idx == 9'h1D4 | validArray[468], - io_update_valid & update_idx == 9'h1D3 | validArray[467], - io_update_valid & update_idx == 9'h1D2 | validArray[466], - io_update_valid & update_idx == 9'h1D1 | validArray[465], - io_update_valid & update_idx == 9'h1D0 | validArray[464], - io_update_valid & update_idx == 9'h1CF | validArray[463], - io_update_valid & update_idx == 9'h1CE | validArray[462], - io_update_valid & update_idx == 9'h1CD | validArray[461], - io_update_valid & update_idx == 9'h1CC | validArray[460], - io_update_valid & update_idx == 9'h1CB | validArray[459], - io_update_valid & update_idx == 9'h1CA | validArray[458], - io_update_valid & update_idx == 9'h1C9 | validArray[457], - io_update_valid & update_idx == 9'h1C8 | validArray[456], - io_update_valid & update_idx == 9'h1C7 | validArray[455], - io_update_valid & update_idx == 9'h1C6 | validArray[454], - io_update_valid & update_idx == 9'h1C5 | validArray[453], - io_update_valid & update_idx == 9'h1C4 | validArray[452], - io_update_valid & update_idx == 9'h1C3 | validArray[451], - io_update_valid & update_idx == 9'h1C2 | validArray[450], - io_update_valid & update_idx == 9'h1C1 | validArray[449], - io_update_valid & update_idx == 9'h1C0 | validArray[448], - io_update_valid & update_idx == 9'h1BF | validArray[447], - io_update_valid & update_idx == 9'h1BE | validArray[446], - io_update_valid & update_idx == 9'h1BD | validArray[445], - io_update_valid & update_idx == 9'h1BC | validArray[444], - io_update_valid & update_idx == 9'h1BB | validArray[443], - io_update_valid & update_idx == 9'h1BA | validArray[442], - io_update_valid & update_idx == 9'h1B9 | validArray[441], - io_update_valid & update_idx == 9'h1B8 | validArray[440], - io_update_valid & update_idx == 9'h1B7 | validArray[439], - io_update_valid & update_idx == 9'h1B6 | validArray[438], - io_update_valid & update_idx == 9'h1B5 | validArray[437], - io_update_valid & update_idx == 9'h1B4 | validArray[436], - io_update_valid & update_idx == 9'h1B3 | validArray[435], - io_update_valid & update_idx == 9'h1B2 | validArray[434], - io_update_valid & update_idx == 9'h1B1 | validArray[433], - io_update_valid & update_idx == 9'h1B0 | validArray[432], - io_update_valid & update_idx == 9'h1AF | validArray[431], - io_update_valid & update_idx == 9'h1AE | validArray[430], - io_update_valid & update_idx == 9'h1AD | validArray[429], - io_update_valid & update_idx == 9'h1AC | validArray[428], - io_update_valid & update_idx == 9'h1AB | validArray[427], - io_update_valid & update_idx == 9'h1AA | validArray[426], - io_update_valid & update_idx == 9'h1A9 | validArray[425], - io_update_valid & update_idx == 9'h1A8 | validArray[424], - io_update_valid & update_idx == 9'h1A7 | validArray[423], - io_update_valid & update_idx == 9'h1A6 | validArray[422], - io_update_valid & update_idx == 9'h1A5 | validArray[421], - io_update_valid & update_idx == 9'h1A4 | validArray[420], - io_update_valid & update_idx == 9'h1A3 | validArray[419], - io_update_valid & update_idx == 9'h1A2 | validArray[418], - io_update_valid & update_idx == 9'h1A1 | validArray[417], - io_update_valid & update_idx == 9'h1A0 | validArray[416], - io_update_valid & update_idx == 9'h19F | validArray[415], - io_update_valid & update_idx == 9'h19E | validArray[414], - io_update_valid & update_idx == 9'h19D | validArray[413], - io_update_valid & update_idx == 9'h19C | validArray[412], - io_update_valid & update_idx == 9'h19B | validArray[411], - io_update_valid & update_idx == 9'h19A | validArray[410], - io_update_valid & update_idx == 9'h199 | validArray[409], - io_update_valid & update_idx == 9'h198 | validArray[408], - io_update_valid & update_idx == 9'h197 | validArray[407], - io_update_valid & update_idx == 9'h196 | validArray[406], - io_update_valid & update_idx == 9'h195 | validArray[405], - io_update_valid & update_idx == 9'h194 | validArray[404], - io_update_valid & update_idx == 9'h193 | validArray[403], - io_update_valid & update_idx == 9'h192 | validArray[402], - io_update_valid & update_idx == 9'h191 | validArray[401], - io_update_valid & update_idx == 9'h190 | validArray[400], - io_update_valid & update_idx == 9'h18F | validArray[399], - io_update_valid & update_idx == 9'h18E | validArray[398], - io_update_valid & update_idx == 9'h18D | validArray[397], - io_update_valid & update_idx == 9'h18C | validArray[396], - io_update_valid & update_idx == 9'h18B | validArray[395], - io_update_valid & update_idx == 9'h18A | validArray[394], - io_update_valid & update_idx == 9'h189 | validArray[393], - io_update_valid & update_idx == 9'h188 | validArray[392], - io_update_valid & update_idx == 9'h187 | validArray[391], - io_update_valid & update_idx == 9'h186 | validArray[390], - io_update_valid & update_idx == 9'h185 | validArray[389], - io_update_valid & update_idx == 9'h184 | validArray[388], - io_update_valid & update_idx == 9'h183 | validArray[387], - io_update_valid & update_idx == 9'h182 | validArray[386], - io_update_valid & update_idx == 9'h181 | validArray[385], - io_update_valid & update_idx == 9'h180 | validArray[384], - io_update_valid & update_idx == 9'h17F | validArray[383], - io_update_valid & update_idx == 9'h17E | validArray[382], - io_update_valid & update_idx == 9'h17D | validArray[381], - io_update_valid & update_idx == 9'h17C | validArray[380], - io_update_valid & update_idx == 9'h17B | validArray[379], - io_update_valid & update_idx == 9'h17A | validArray[378], - io_update_valid & update_idx == 9'h179 | validArray[377], - io_update_valid & update_idx == 9'h178 | validArray[376], - io_update_valid & update_idx == 9'h177 | validArray[375], - io_update_valid & update_idx == 9'h176 | validArray[374], - io_update_valid & update_idx == 9'h175 | validArray[373], - io_update_valid & update_idx == 9'h174 | validArray[372], - io_update_valid & update_idx == 9'h173 | validArray[371], - io_update_valid & update_idx == 9'h172 | validArray[370], - io_update_valid & update_idx == 9'h171 | validArray[369], - io_update_valid & update_idx == 9'h170 | validArray[368], - io_update_valid & update_idx == 9'h16F | validArray[367], - io_update_valid & update_idx == 9'h16E | validArray[366], - io_update_valid & update_idx == 9'h16D | validArray[365], - io_update_valid & update_idx == 9'h16C | validArray[364], - io_update_valid & update_idx == 9'h16B | validArray[363], - io_update_valid & update_idx == 9'h16A | validArray[362], - io_update_valid & update_idx == 9'h169 | validArray[361], - io_update_valid & update_idx == 9'h168 | validArray[360], - io_update_valid & update_idx == 9'h167 | validArray[359], - io_update_valid & update_idx == 9'h166 | validArray[358], - io_update_valid & update_idx == 9'h165 | validArray[357], - io_update_valid & update_idx == 9'h164 | validArray[356], - io_update_valid & update_idx == 9'h163 | validArray[355], - io_update_valid & update_idx == 9'h162 | validArray[354], - io_update_valid & update_idx == 9'h161 | validArray[353], - io_update_valid & update_idx == 9'h160 | validArray[352], - io_update_valid & update_idx == 9'h15F | validArray[351], - io_update_valid & update_idx == 9'h15E | validArray[350], - io_update_valid & update_idx == 9'h15D | validArray[349], - io_update_valid & update_idx == 9'h15C | validArray[348], - io_update_valid & update_idx == 9'h15B | validArray[347], - io_update_valid & update_idx == 9'h15A | validArray[346], - io_update_valid & update_idx == 9'h159 | validArray[345], - io_update_valid & update_idx == 9'h158 | validArray[344], - io_update_valid & update_idx == 9'h157 | validArray[343], - io_update_valid & update_idx == 9'h156 | validArray[342], - io_update_valid & update_idx == 9'h155 | validArray[341], - io_update_valid & update_idx == 9'h154 | validArray[340], - io_update_valid & update_idx == 9'h153 | validArray[339], - io_update_valid & update_idx == 9'h152 | validArray[338], - io_update_valid & update_idx == 9'h151 | validArray[337], - io_update_valid & update_idx == 9'h150 | validArray[336], - io_update_valid & update_idx == 9'h14F | validArray[335], - io_update_valid & update_idx == 9'h14E | validArray[334], - io_update_valid & update_idx == 9'h14D | validArray[333], - io_update_valid & update_idx == 9'h14C | validArray[332], - io_update_valid & update_idx == 9'h14B | validArray[331], - io_update_valid & update_idx == 9'h14A | validArray[330], - io_update_valid & update_idx == 9'h149 | validArray[329], - io_update_valid & update_idx == 9'h148 | validArray[328], - io_update_valid & update_idx == 9'h147 | validArray[327], - io_update_valid & update_idx == 9'h146 | validArray[326], - io_update_valid & update_idx == 9'h145 | validArray[325], - io_update_valid & update_idx == 9'h144 | validArray[324], - io_update_valid & update_idx == 9'h143 | validArray[323], - io_update_valid & update_idx == 9'h142 | validArray[322], - io_update_valid & update_idx == 9'h141 | validArray[321], - io_update_valid & update_idx == 9'h140 | validArray[320], - io_update_valid & update_idx == 9'h13F | validArray[319], - io_update_valid & update_idx == 9'h13E | validArray[318], - io_update_valid & update_idx == 9'h13D | validArray[317], - io_update_valid & update_idx == 9'h13C | validArray[316], - io_update_valid & update_idx == 9'h13B | validArray[315], - io_update_valid & update_idx == 9'h13A | validArray[314], - io_update_valid & update_idx == 9'h139 | validArray[313], - io_update_valid & update_idx == 9'h138 | validArray[312], - io_update_valid & update_idx == 9'h137 | validArray[311], - io_update_valid & update_idx == 9'h136 | validArray[310], - io_update_valid & update_idx == 9'h135 | validArray[309], - io_update_valid & update_idx == 9'h134 | validArray[308], - io_update_valid & update_idx == 9'h133 | validArray[307], - io_update_valid & update_idx == 9'h132 | validArray[306], - io_update_valid & update_idx == 9'h131 | validArray[305], - io_update_valid & update_idx == 9'h130 | validArray[304], - io_update_valid & update_idx == 9'h12F | validArray[303], - io_update_valid & update_idx == 9'h12E | validArray[302], - io_update_valid & update_idx == 9'h12D | validArray[301], - io_update_valid & update_idx == 9'h12C | validArray[300], - io_update_valid & update_idx == 9'h12B | validArray[299], - io_update_valid & update_idx == 9'h12A | validArray[298], - io_update_valid & update_idx == 9'h129 | validArray[297], - io_update_valid & update_idx == 9'h128 | validArray[296], - io_update_valid & update_idx == 9'h127 | validArray[295], - io_update_valid & update_idx == 9'h126 | validArray[294], - io_update_valid & update_idx == 9'h125 | validArray[293], - io_update_valid & update_idx == 9'h124 | validArray[292], - io_update_valid & update_idx == 9'h123 | validArray[291], - io_update_valid & update_idx == 9'h122 | validArray[290], - io_update_valid & update_idx == 9'h121 | validArray[289], - io_update_valid & update_idx == 9'h120 | validArray[288], - io_update_valid & update_idx == 9'h11F | validArray[287], - io_update_valid & update_idx == 9'h11E | validArray[286], - io_update_valid & update_idx == 9'h11D | validArray[285], - io_update_valid & update_idx == 9'h11C | validArray[284], - io_update_valid & update_idx == 9'h11B | validArray[283], - io_update_valid & update_idx == 9'h11A | validArray[282], - io_update_valid & update_idx == 9'h119 | validArray[281], - io_update_valid & update_idx == 9'h118 | validArray[280], - io_update_valid & update_idx == 9'h117 | validArray[279], - io_update_valid & update_idx == 9'h116 | validArray[278], - io_update_valid & update_idx == 9'h115 | validArray[277], - io_update_valid & update_idx == 9'h114 | validArray[276], - io_update_valid & update_idx == 9'h113 | validArray[275], - io_update_valid & update_idx == 9'h112 | validArray[274], - io_update_valid & update_idx == 9'h111 | validArray[273], - io_update_valid & update_idx == 9'h110 | validArray[272], - io_update_valid & update_idx == 9'h10F | validArray[271], - io_update_valid & update_idx == 9'h10E | validArray[270], - io_update_valid & update_idx == 9'h10D | validArray[269], - io_update_valid & update_idx == 9'h10C | validArray[268], - io_update_valid & update_idx == 9'h10B | validArray[267], - io_update_valid & update_idx == 9'h10A | validArray[266], - io_update_valid & update_idx == 9'h109 | validArray[265], - io_update_valid & update_idx == 9'h108 | validArray[264], - io_update_valid & update_idx == 9'h107 | validArray[263], - io_update_valid & update_idx == 9'h106 | validArray[262], - io_update_valid & update_idx == 9'h105 | validArray[261], - io_update_valid & update_idx == 9'h104 | validArray[260], - io_update_valid & update_idx == 9'h103 | validArray[259], - io_update_valid & update_idx == 9'h102 | validArray[258], - io_update_valid & update_idx == 9'h101 | validArray[257], - io_update_valid & update_idx == 9'h100 | validArray[256], - io_update_valid & update_idx == 9'hFF | validArray[255], - io_update_valid & update_idx == 9'hFE | validArray[254], - io_update_valid & update_idx == 9'hFD | validArray[253], - io_update_valid & update_idx == 9'hFC | validArray[252], - io_update_valid & update_idx == 9'hFB | validArray[251], - io_update_valid & update_idx == 9'hFA | validArray[250], - io_update_valid & update_idx == 9'hF9 | validArray[249], - io_update_valid & update_idx == 9'hF8 | validArray[248], - io_update_valid & update_idx == 9'hF7 | validArray[247], - io_update_valid & update_idx == 9'hF6 | validArray[246], - io_update_valid & update_idx == 9'hF5 | validArray[245], - io_update_valid & update_idx == 9'hF4 | validArray[244], - io_update_valid & update_idx == 9'hF3 | validArray[243], - io_update_valid & update_idx == 9'hF2 | validArray[242], - io_update_valid & update_idx == 9'hF1 | validArray[241], - io_update_valid & update_idx == 9'hF0 | validArray[240], - io_update_valid & update_idx == 9'hEF | validArray[239], - io_update_valid & update_idx == 9'hEE | validArray[238], - io_update_valid & update_idx == 9'hED | validArray[237], - io_update_valid & update_idx == 9'hEC | validArray[236], - io_update_valid & update_idx == 9'hEB | validArray[235], - io_update_valid & update_idx == 9'hEA | validArray[234], - io_update_valid & update_idx == 9'hE9 | validArray[233], - io_update_valid & update_idx == 9'hE8 | validArray[232], - io_update_valid & update_idx == 9'hE7 | validArray[231], - io_update_valid & update_idx == 9'hE6 | validArray[230], - io_update_valid & update_idx == 9'hE5 | validArray[229], - io_update_valid & update_idx == 9'hE4 | validArray[228], - io_update_valid & update_idx == 9'hE3 | validArray[227], - io_update_valid & update_idx == 9'hE2 | validArray[226], - io_update_valid & update_idx == 9'hE1 | validArray[225], - io_update_valid & update_idx == 9'hE0 | validArray[224], - io_update_valid & update_idx == 9'hDF | validArray[223], - io_update_valid & update_idx == 9'hDE | validArray[222], - io_update_valid & update_idx == 9'hDD | validArray[221], - io_update_valid & update_idx == 9'hDC | validArray[220], - io_update_valid & update_idx == 9'hDB | validArray[219], - io_update_valid & update_idx == 9'hDA | validArray[218], - io_update_valid & update_idx == 9'hD9 | validArray[217], - io_update_valid & update_idx == 9'hD8 | validArray[216], - io_update_valid & update_idx == 9'hD7 | validArray[215], - io_update_valid & update_idx == 9'hD6 | validArray[214], - io_update_valid & update_idx == 9'hD5 | validArray[213], - io_update_valid & update_idx == 9'hD4 | validArray[212], - io_update_valid & update_idx == 9'hD3 | validArray[211], - io_update_valid & update_idx == 9'hD2 | validArray[210], - io_update_valid & update_idx == 9'hD1 | validArray[209], - io_update_valid & update_idx == 9'hD0 | validArray[208], - io_update_valid & update_idx == 9'hCF | validArray[207], - io_update_valid & update_idx == 9'hCE | validArray[206], - io_update_valid & update_idx == 9'hCD | validArray[205], - io_update_valid & update_idx == 9'hCC | validArray[204], - io_update_valid & update_idx == 9'hCB | validArray[203], - io_update_valid & update_idx == 9'hCA | validArray[202], - io_update_valid & update_idx == 9'hC9 | validArray[201], - io_update_valid & update_idx == 9'hC8 | validArray[200], - io_update_valid & update_idx == 9'hC7 | validArray[199], - io_update_valid & update_idx == 9'hC6 | validArray[198], - io_update_valid & update_idx == 9'hC5 | validArray[197], - io_update_valid & update_idx == 9'hC4 | validArray[196], - io_update_valid & update_idx == 9'hC3 | validArray[195], - io_update_valid & update_idx == 9'hC2 | validArray[194], - io_update_valid & update_idx == 9'hC1 | validArray[193], - io_update_valid & update_idx == 9'hC0 | validArray[192], - io_update_valid & update_idx == 9'hBF | validArray[191], - io_update_valid & update_idx == 9'hBE | validArray[190], - io_update_valid & update_idx == 9'hBD | validArray[189], - io_update_valid & update_idx == 9'hBC | validArray[188], - io_update_valid & update_idx == 9'hBB | validArray[187], - io_update_valid & update_idx == 9'hBA | validArray[186], - io_update_valid & update_idx == 9'hB9 | validArray[185], - io_update_valid & update_idx == 9'hB8 | validArray[184], - io_update_valid & update_idx == 9'hB7 | validArray[183], - io_update_valid & update_idx == 9'hB6 | validArray[182], - io_update_valid & update_idx == 9'hB5 | validArray[181], - io_update_valid & update_idx == 9'hB4 | validArray[180], - io_update_valid & update_idx == 9'hB3 | validArray[179], - io_update_valid & update_idx == 9'hB2 | validArray[178], - io_update_valid & update_idx == 9'hB1 | validArray[177], - io_update_valid & update_idx == 9'hB0 | validArray[176], - io_update_valid & update_idx == 9'hAF | validArray[175], - io_update_valid & update_idx == 9'hAE | validArray[174], - io_update_valid & update_idx == 9'hAD | validArray[173], - io_update_valid & update_idx == 9'hAC | validArray[172], - io_update_valid & update_idx == 9'hAB | validArray[171], - io_update_valid & update_idx == 9'hAA | validArray[170], - io_update_valid & update_idx == 9'hA9 | validArray[169], - io_update_valid & update_idx == 9'hA8 | validArray[168], - io_update_valid & update_idx == 9'hA7 | validArray[167], - io_update_valid & update_idx == 9'hA6 | validArray[166], - io_update_valid & update_idx == 9'hA5 | validArray[165], - io_update_valid & update_idx == 9'hA4 | validArray[164], - io_update_valid & update_idx == 9'hA3 | validArray[163], - io_update_valid & update_idx == 9'hA2 | validArray[162], - io_update_valid & update_idx == 9'hA1 | validArray[161], - io_update_valid & update_idx == 9'hA0 | validArray[160], - io_update_valid & update_idx == 9'h9F | validArray[159], - io_update_valid & update_idx == 9'h9E | validArray[158], - io_update_valid & update_idx == 9'h9D | validArray[157], - io_update_valid & update_idx == 9'h9C | validArray[156], - io_update_valid & update_idx == 9'h9B | validArray[155], - io_update_valid & update_idx == 9'h9A | validArray[154], - io_update_valid & update_idx == 9'h99 | validArray[153], - io_update_valid & update_idx == 9'h98 | validArray[152], - io_update_valid & update_idx == 9'h97 | validArray[151], - io_update_valid & update_idx == 9'h96 | validArray[150], - io_update_valid & update_idx == 9'h95 | validArray[149], - io_update_valid & update_idx == 9'h94 | validArray[148], - io_update_valid & update_idx == 9'h93 | validArray[147], - io_update_valid & update_idx == 9'h92 | validArray[146], - io_update_valid & update_idx == 9'h91 | validArray[145], - io_update_valid & update_idx == 9'h90 | validArray[144], - io_update_valid & update_idx == 9'h8F | validArray[143], - io_update_valid & update_idx == 9'h8E | validArray[142], - io_update_valid & update_idx == 9'h8D | validArray[141], - io_update_valid & update_idx == 9'h8C | validArray[140], - io_update_valid & update_idx == 9'h8B | validArray[139], - io_update_valid & update_idx == 9'h8A | validArray[138], - io_update_valid & update_idx == 9'h89 | validArray[137], - io_update_valid & update_idx == 9'h88 | validArray[136], - io_update_valid & update_idx == 9'h87 | validArray[135], - io_update_valid & update_idx == 9'h86 | validArray[134], - io_update_valid & update_idx == 9'h85 | validArray[133], - io_update_valid & update_idx == 9'h84 | validArray[132], - io_update_valid & update_idx == 9'h83 | validArray[131], - io_update_valid & update_idx == 9'h82 | validArray[130], - io_update_valid & update_idx == 9'h81 | validArray[129], - io_update_valid & update_idx == 9'h80 | validArray[128], - io_update_valid & update_idx == 9'h7F | validArray[127], - io_update_valid & update_idx == 9'h7E | validArray[126], - io_update_valid & update_idx == 9'h7D | validArray[125], - io_update_valid & update_idx == 9'h7C | validArray[124], - io_update_valid & update_idx == 9'h7B | validArray[123], - io_update_valid & update_idx == 9'h7A | validArray[122], - io_update_valid & update_idx == 9'h79 | validArray[121], - io_update_valid & update_idx == 9'h78 | validArray[120], - io_update_valid & update_idx == 9'h77 | validArray[119], - io_update_valid & update_idx == 9'h76 | validArray[118], - io_update_valid & update_idx == 9'h75 | validArray[117], - io_update_valid & update_idx == 9'h74 | validArray[116], - io_update_valid & update_idx == 9'h73 | validArray[115], - io_update_valid & update_idx == 9'h72 | validArray[114], - io_update_valid & update_idx == 9'h71 | validArray[113], - io_update_valid & update_idx == 9'h70 | validArray[112], - io_update_valid & update_idx == 9'h6F | validArray[111], - io_update_valid & update_idx == 9'h6E | validArray[110], - io_update_valid & update_idx == 9'h6D | validArray[109], - io_update_valid & update_idx == 9'h6C | validArray[108], - io_update_valid & update_idx == 9'h6B | validArray[107], - io_update_valid & update_idx == 9'h6A | validArray[106], - io_update_valid & update_idx == 9'h69 | validArray[105], - io_update_valid & update_idx == 9'h68 | validArray[104], - io_update_valid & update_idx == 9'h67 | validArray[103], - io_update_valid & update_idx == 9'h66 | validArray[102], - io_update_valid & update_idx == 9'h65 | validArray[101], - io_update_valid & update_idx == 9'h64 | validArray[100], - io_update_valid & update_idx == 9'h63 | validArray[99], - io_update_valid & update_idx == 9'h62 | validArray[98], - io_update_valid & update_idx == 9'h61 | validArray[97], - io_update_valid & update_idx == 9'h60 | validArray[96], - io_update_valid & update_idx == 9'h5F | validArray[95], - io_update_valid & update_idx == 9'h5E | validArray[94], - io_update_valid & update_idx == 9'h5D | validArray[93], - io_update_valid & update_idx == 9'h5C | validArray[92], - io_update_valid & update_idx == 9'h5B | validArray[91], - io_update_valid & update_idx == 9'h5A | validArray[90], - io_update_valid & update_idx == 9'h59 | validArray[89], - io_update_valid & update_idx == 9'h58 | validArray[88], - io_update_valid & update_idx == 9'h57 | validArray[87], - io_update_valid & update_idx == 9'h56 | validArray[86], - io_update_valid & update_idx == 9'h55 | validArray[85], - io_update_valid & update_idx == 9'h54 | validArray[84], - io_update_valid & update_idx == 9'h53 | validArray[83], - io_update_valid & update_idx == 9'h52 | validArray[82], - io_update_valid & update_idx == 9'h51 | validArray[81], - io_update_valid & update_idx == 9'h50 | validArray[80], - io_update_valid & update_idx == 9'h4F | validArray[79], - io_update_valid & update_idx == 9'h4E | validArray[78], - io_update_valid & update_idx == 9'h4D | validArray[77], - io_update_valid & update_idx == 9'h4C | validArray[76], - io_update_valid & update_idx == 9'h4B | validArray[75], - io_update_valid & update_idx == 9'h4A | validArray[74], - io_update_valid & update_idx == 9'h49 | validArray[73], - io_update_valid & update_idx == 9'h48 | validArray[72], - io_update_valid & update_idx == 9'h47 | validArray[71], - io_update_valid & update_idx == 9'h46 | validArray[70], - io_update_valid & update_idx == 9'h45 | validArray[69], - io_update_valid & update_idx == 9'h44 | validArray[68], - io_update_valid & update_idx == 9'h43 | validArray[67], - io_update_valid & update_idx == 9'h42 | validArray[66], - io_update_valid & update_idx == 9'h41 | validArray[65], - io_update_valid & update_idx == 9'h40 | validArray[64], - io_update_valid & update_idx == 9'h3F | validArray[63], - io_update_valid & update_idx == 9'h3E | validArray[62], - io_update_valid & update_idx == 9'h3D | validArray[61], - io_update_valid & update_idx == 9'h3C | validArray[60], - io_update_valid & update_idx == 9'h3B | validArray[59], - io_update_valid & update_idx == 9'h3A | validArray[58], - io_update_valid & update_idx == 9'h39 | validArray[57], - io_update_valid & update_idx == 9'h38 | validArray[56], - io_update_valid & update_idx == 9'h37 | validArray[55], - io_update_valid & update_idx == 9'h36 | validArray[54], - io_update_valid & update_idx == 9'h35 | validArray[53], - io_update_valid & update_idx == 9'h34 | validArray[52], - io_update_valid & update_idx == 9'h33 | validArray[51], - io_update_valid & update_idx == 9'h32 | validArray[50], - io_update_valid & update_idx == 9'h31 | validArray[49], - io_update_valid & update_idx == 9'h30 | validArray[48], - io_update_valid & update_idx == 9'h2F | validArray[47], - io_update_valid & update_idx == 9'h2E | validArray[46], - io_update_valid & update_idx == 9'h2D | validArray[45], - io_update_valid & update_idx == 9'h2C | validArray[44], - io_update_valid & update_idx == 9'h2B | validArray[43], - io_update_valid & update_idx == 9'h2A | validArray[42], - io_update_valid & update_idx == 9'h29 | validArray[41], - io_update_valid & update_idx == 9'h28 | validArray[40], - io_update_valid & update_idx == 9'h27 | validArray[39], - io_update_valid & update_idx == 9'h26 | validArray[38], - io_update_valid & update_idx == 9'h25 | validArray[37], - io_update_valid & update_idx == 9'h24 | validArray[36], - io_update_valid & update_idx == 9'h23 | validArray[35], - io_update_valid & update_idx == 9'h22 | validArray[34], - io_update_valid & update_idx == 9'h21 | validArray[33], - io_update_valid & update_idx == 9'h20 | validArray[32], - io_update_valid & update_idx == 9'h1F | validArray[31], - io_update_valid & update_idx == 9'h1E | validArray[30], - io_update_valid & update_idx == 9'h1D | validArray[29], - io_update_valid & update_idx == 9'h1C | validArray[28], - io_update_valid & update_idx == 9'h1B | validArray[27], - io_update_valid & update_idx == 9'h1A | validArray[26], - io_update_valid & update_idx == 9'h19 | validArray[25], - io_update_valid & update_idx == 9'h18 | validArray[24], - io_update_valid & update_idx == 9'h17 | validArray[23], - io_update_valid & update_idx == 9'h16 | validArray[22], - io_update_valid & update_idx == 9'h15 | validArray[21], - io_update_valid & update_idx == 9'h14 | validArray[20], - io_update_valid & update_idx == 9'h13 | validArray[19], - io_update_valid & update_idx == 9'h12 | validArray[18], - io_update_valid & update_idx == 9'h11 | validArray[17], - io_update_valid & update_idx == 9'h10 | validArray[16], - io_update_valid & update_idx == 9'hF | validArray[15], - io_update_valid & update_idx == 9'hE | validArray[14], - io_update_valid & update_idx == 9'hD | validArray[13], - io_update_valid & update_idx == 9'hC | validArray[12], - io_update_valid & update_idx == 9'hB | validArray[11], - io_update_valid & update_idx == 9'hA | validArray[10], - io_update_valid & update_idx == 9'h9 | validArray[9], - io_update_valid & update_idx == 9'h8 | validArray[8], - io_update_valid & update_idx == 9'h7 | validArray[7], - io_update_valid & update_idx == 9'h6 | validArray[6], - io_update_valid & update_idx == 9'h5 | validArray[5], - io_update_valid & update_idx == 9'h4 | validArray[4], - io_update_valid & update_idx == 9'h3 | validArray[3], - io_update_valid & update_idx == 9'h2 | validArray[2], - io_update_valid & update_idx == 9'h1 | validArray[1], - io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 - always @(posedge clock or posedge reset) begin - if (reset) - validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 - else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 - end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 - s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + : io_update_old_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14] s1_tag <= io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist - ^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 - s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 - s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + ^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :182:{32,52,61,75}, :205:43, :211:68] + s1_bank_req_1h_0 <= ~(s0_idx[0]); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :213:33] + s1_bank_req_1h_1 <= s0_idx[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :213:33] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:239:48, :254:33] end end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = - {_RANDOM[5'h0], - _RANDOM[5'h1], - _RANDOM[5'h2], - _RANDOM[5'h3], - _RANDOM[5'h4], - _RANDOM[5'h5], - _RANDOM[5'h6], - _RANDOM[5'h7], - _RANDOM[5'h8], - _RANDOM[5'h9], - _RANDOM[5'hA], - _RANDOM[5'hB], - _RANDOM[5'hC], - _RANDOM[5'hD], - _RANDOM[5'hE], - _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 - s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 - s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} - s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68] + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :239:48] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + Folded1WDataModuleTemplate_2 us ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:215:18] .clock (clock), .reset (reset), - .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_rdata_0 (_us_io_rdata_0), .io_wen (io_update_uValid), - .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_waddr (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] .io_wdata (io_update_u), .io_resetEn (io_update_reset_u) ); - FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + FoldedSRAMTemplate_25 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:217:44] .clock (clock), .reset (reset), - .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 - .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_req_valid (io_req_valid & s0_idx[0]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :221:50] + .io_r_req_bits_setIdx (s0_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 - .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} - .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 - .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 - .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:254:33] + .io_w_req_bits_setIdx (update_idx[8:1]), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61] + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] + .io_w_req_bits_data_0_target (update_wdata_target) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29] ); - WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + WrBypass_43 wrbypass ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:270:24] .clock (clock), .reset (reset), .io_wen (io_update_valid), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 - .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31] + .io_write_data_0 (update_wdata_ctr), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28] .io_hit (_wrbypass_io_hit), .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) ); assign io_resp_valid = - _s1_req_rhit_T[0] + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag - & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + & ~_resp_invalid_by_write_T_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :211:68, :213:33, :217:44, :231:62, :234:{50,53}] assign io_resp_bits_ctr = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 - assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:18, :236:18] assign io_resp_bits_target = - (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) - | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:33, :217:44] endmodule diff --git a/rtl/ITTAGE/SRAMTemplate_35.sv b/rtl/ITTAGE/SRAMTemplate_35.sv deleted file mode 100644 index 819e442..0000000 --- a/rtl/ITTAGE/SRAMTemplate_35.sv +++ /dev/null @@ -1,143 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_35( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 -); - - wire [6:0] writeAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 - wire readEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 - wire writeEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - wire [49:0] _array_0_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [6:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign writeEnable = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - assign readEnable = io_r_req_valid & ~writeEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} - assign writeAddr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg [49:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [49:0] _rdata_WIRE = rdata_REG ? _array_0_RW0_rdata : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet <= 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - else begin - _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 7'(_resetSet + 7'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 - end - end // always @(posedge, posedge) - always @(posedge clock) begin - rdata_REG <= readEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 - if (rdata_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= _array_0_RW0_rdata; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[3'h0][7:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - rdata_REG = _RANDOM[3'h2][24]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][10:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_0_0 array_0 ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .RW0_addr (writeEnable ? writeAddr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 - .RW0_en (readEnable | writeEnable), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 - .RW0_clk (clock), - .RW0_wmode (writeEnable), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - .RW0_wdata - ({_resetState ? 9'h0 : io_w_req_bits_data_0_tag, - _resetState ? 2'h0 : io_w_req_bits_data_0_ctr, - _resetState ? 39'h0 : io_w_req_bits_data_0_target}), // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51,102} - .RW0_rdata (_array_0_RW0_rdata) - ); - assign io_r_resp_data_0_tag = _rdata_WIRE[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_ctr = _rdata_WIRE[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_target = _rdata_WIRE[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 -endmodule - diff --git a/rtl/ITTAGE/SRAMTemplate_39.sv b/rtl/ITTAGE/SRAMTemplate_39.sv index e80ce9c..a7c8753 100644 --- a/rtl/ITTAGE/SRAMTemplate_39.sv +++ b/rtl/ITTAGE/SRAMTemplate_39.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,120 +55,95 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module SRAMTemplate_39( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [8:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [38:0] io_r_resp_data_1_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [38:0] io_w_req_bits_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [38:0] io_w_req_bits_data_1_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 +module SRAMTemplate_39( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [6:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [8:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [40:0] io_r_resp_data_0_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [6:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [40:0] io_w_req_bits_data_0_target // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] ); - wire [38:0] _wdata_T_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [8:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [38:0] _wdata_T_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [1:0] _wdata_T_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [8:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [6:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 - wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 - wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - wire [99:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [6:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} - assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - assign _wdata_T_0_tag = _resetState ? 9'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_ctr = _resetState ? 2'h0 : io_w_req_bits_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_target = _resetState ? 39'h0 : io_w_req_bits_data_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_tag = _resetState ? 9'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_ctr = _resetState ? 2'h0 : io_w_req_bits_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_target = _resetState ? 39'h0 : io_w_req_bits_data_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg [49:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [49:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [49:0] _rdata_WIRE = rdata_REG ? _array_RW0_rdata[49:0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 - wire [49:0] _rdata_WIRE_1 = rdata_REG ? _array_RW0_rdata[99:50] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet <= 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + wire [6:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19] + wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + wire [52:0] _array_0_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [6:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}] + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [52:0] rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [52:0] _rdata_T_0 = rdata_last_r ? _array_0_RW0_rdata : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet <= 7'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] end - else begin - _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 7'(_resetSet + 7'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 7'(_resetSet + 7'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + if (realRen | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + rdata_last_r <= realRen; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] end end // always @(posedge, posedge) - always @(posedge clock) begin - rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 - if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= _array_RW0_rdata[49:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_1 <= _array_RW0_rdata[99:50]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - end + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= _array_0_RW0_rdata; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:7]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + logic [31:0] _RANDOM[0:4]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin - _RANDOM[i[2:0]] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[3'h0][7:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - rdata_REG = _RANDOM[3'h4][25]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_0 = {_RANDOM[3'h4][31:26], _RANDOM[3'h5], _RANDOM[3'h6][11:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_1 = {_RANDOM[3'h6][31:12], _RANDOM[3'h7][29:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[3'h0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[3'h0][7:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + rdata_last_r = _RANDOM[3'h2][24]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][13:0]}; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet = 7'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - array_8 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 - .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 + array_0_0 array_0 ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19] + .RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38] .RW0_clk (clock), - .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + .RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] .RW0_wdata - ({_wdata_T_1_tag, - _wdata_T_1_ctr, - _wdata_T_1_target, - _wdata_T_0_tag, - _wdata_T_0_ctr, - _wdata_T_0_target}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 - .RW0_rdata (_array_RW0_rdata), - .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} + ({~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_0_tag, + _resetState ? 2'h0 : io_w_req_bits_data_0_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_0_target}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :144:14, :158:30, :175:{18,43}, :176:13] + .RW0_rdata (_array_0_RW0_rdata) ); - assign io_r_resp_data_0_tag = _rdata_WIRE[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_ctr = _rdata_WIRE[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_target = _rdata_WIRE[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_tag = _rdata_WIRE_1[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_ctr = _rdata_WIRE_1[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_target = _rdata_WIRE_1[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_0_valid = _rdata_T_0[52]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_tag = _rdata_T_0[51:43]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_ctr = _rdata_T_0[42:41]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_target = _rdata_T_0[40:0]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] endmodule diff --git a/rtl/ITTAGE/SRAMTemplate_43.sv b/rtl/ITTAGE/SRAMTemplate_43.sv new file mode 100644 index 0000000..d6b65e1 --- /dev/null +++ b/rtl/ITTAGE/SRAMTemplate_43.sv @@ -0,0 +1,171 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_43( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [6:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [8:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [40:0] io_r_resp_data_0_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [8:0] io_r_resp_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [40:0] io_r_resp_data_1_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [6:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [40:0] io_w_req_bits_data_0_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [40:0] io_w_req_bits_data_1_target, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] +); + + wire [6:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19] + wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + wire [105:0] _array_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [6:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}] + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [52:0] rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [52:0] rdata_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [52:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[52:0] : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + wire [52:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[105:53] : rdata_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet <= 7'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 7'(_resetSet + 7'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + if (realRen | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + rdata_last_r <= realRen; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + end + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (rdata_last_r) begin // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= _array_RW0_rdata[52:0]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_1 <= _array_RW0_rdata[105:53]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:8]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[4'h0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[4'h0][7:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + rdata_last_r = _RANDOM[4'h4][25]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_0 = {_RANDOM[4'h4][31:26], _RANDOM[4'h5], _RANDOM[4'h6][14:0]}; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_1 = {_RANDOM[4'h6][31:15], _RANDOM[4'h7], _RANDOM[4'h8][3:0]}; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet = 7'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_8 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19] + .RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38] + .RW0_clk (clock), + .RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + .RW0_wdata + ({~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_1_tag, + _resetState ? 2'h0 : io_w_req_bits_data_1_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_1_target, + ~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_0_tag, + _resetState ? 2'h0 : io_w_req_bits_data_0_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_0_target}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :144:14, :158:30, :175:{18,43}, :176:13] + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}] + ); + assign io_r_resp_data_0_valid = _rdata_T_0[52]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_tag = _rdata_T_0[51:43]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_ctr = _rdata_T_0[42:41]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_target = _rdata_T_0[40:0]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_valid = _rdata_T_1[52]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_tag = _rdata_T_1[51:43]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_ctr = _rdata_T_1[42:41]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_target = _rdata_T_1[40:0]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] +endmodule + diff --git a/rtl/ITTAGE/WrBypass_41.sv b/rtl/ITTAGE/WrBypass_41.sv index 420c0ae..9257dbd 100644 --- a/rtl/ITTAGE/WrBypass_41.sv +++ b/rtl/ITTAGE/WrBypass_41.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,105 +55,103 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_41( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_41( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [7:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_0_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = - {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = - _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 - reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 - wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire [1:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - always @(posedge clock or posedge reset) begin - if (reset) begin - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29] + reg [2:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + if (io_wen) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] state_reg <= {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], - state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_41 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_41 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_0_4x2 data_mem_0_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (io_hit_data_0_bits), - .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), .W0_data (io_write_data_0) ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] endmodule diff --git a/rtl/ITTAGE/WrBypass_43.sv b/rtl/ITTAGE/WrBypass_43.sv index b3782c0..e55c343 100644 --- a/rtl/ITTAGE/WrBypass_43.sv +++ b/rtl/ITTAGE/WrBypass_43.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,105 +55,103 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_43( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_43( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [8:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_0_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = - {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = - _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 - reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 - wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire [1:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - always @(posedge clock or posedge reset) begin - if (reset) begin - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29] + reg [2:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + if (io_wen) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] state_reg <= {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], - state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_43 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_43 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_0_4x2 data_mem_0_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (io_hit_data_0_bits), - .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), .W0_data (io_write_data_0) ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] endmodule diff --git a/rtl/ITTAGE/array_0_0.sv b/rtl/ITTAGE/array_0_0.sv index 00faa30..3aca7bd 100644 --- a/rtl/ITTAGE/array_0_0.sv +++ b/rtl/ITTAGE/array_0_0.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,16 +55,16 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_0_0( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_0_0( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [6:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, - input [49:0] RW0_wdata, - output [49:0] RW0_rdata + input [52:0] RW0_wdata, + output [52:0] RW0_rdata ); - array_0_0_ext array_0_0_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_0_0_ext array_0_0_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), diff --git a/rtl/ITTAGE/array_8.sv b/rtl/ITTAGE/array_8.sv index 3fc16d7..c0aa896 100644 --- a/rtl/ITTAGE/array_8.sv +++ b/rtl/ITTAGE/array_8.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,17 +55,17 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_8( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - input [6:0] RW0_addr, - input RW0_en, - input RW0_clk, - input RW0_wmode, - input [99:0] RW0_wdata, - output [99:0] RW0_rdata, - input [1:0] RW0_wmask +module array_8( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + input [6:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [105:0] RW0_wdata, + output [105:0] RW0_rdata, + input [1:0] RW0_wmask ); - array_8_ext array_8_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_8_ext array_8_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), diff --git a/rtl/ITTAGE/data_16x16.sv b/rtl/ITTAGE/data_16x16.sv index 8e23125..3876aab 100644 --- a/rtl/ITTAGE/data_16x16.sv +++ b/rtl/ITTAGE/data_16x16.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_16x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 +module data_16x16( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] input [3:0] R0_addr, input R0_en, input R0_clk, @@ -71,25 +71,25 @@ module data_16x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:21 input [15:0] W1_data ); - reg [15:0] Memory[0:15]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - always @(posedge W0_clk) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - if (W0_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[W0_addr] <= W0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - if (W1_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[W1_addr] <= W1_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + reg [15:0] Memory[0:15]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + always @(posedge W0_clk) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + if (W0_en & 1'h1) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[W0_addr] <= W0_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + if (W1_en & 1'h1) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[W1_addr] <= W1_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - reg [31:0] _RANDOM_MEM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - `ifdef RANDOMIZE_MEM_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + `ifdef ENABLE_INITIAL_MEM_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + reg [31:0] _RANDOM_MEM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + initial begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + `ifdef RANDOMIZE_MEM_INIT // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin - _RANDOM_MEM = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[i[3:0]] = _RANDOM_MEM[15:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - end // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + _RANDOM_MEM = `RANDOM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[i[3:0]] = _RANDOM_MEM[15:0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + end // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] endmodule diff --git a/rtl/ITTAGE/data_32x16.sv b/rtl/ITTAGE/data_32x16.sv index 1e56f90..700895d 100644 --- a/rtl/ITTAGE/data_32x16.sv +++ b/rtl/ITTAGE/data_32x16.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_32x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 +module data_32x16( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] input [4:0] R0_addr, input R0_en, input R0_clk, @@ -71,25 +71,25 @@ module data_32x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:21 input [15:0] W1_data ); - reg [15:0] Memory[0:31]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - always @(posedge W0_clk) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - if (W0_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[W0_addr] <= W0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - if (W1_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[W1_addr] <= W1_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + reg [15:0] Memory[0:31]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + always @(posedge W0_clk) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + if (W0_en & 1'h1) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[W0_addr] <= W0_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + if (W1_en & 1'h1) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[W1_addr] <= W1_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - reg [31:0] _RANDOM_MEM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - `ifdef RANDOMIZE_MEM_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + `ifdef ENABLE_INITIAL_MEM_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + reg [31:0] _RANDOM_MEM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + initial begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + `ifdef RANDOMIZE_MEM_INIT // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin - _RANDOM_MEM = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - Memory[i[4:0]] = _RANDOM_MEM[15:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 - end // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + _RANDOM_MEM = `RANDOM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + Memory[i[4:0]] = _RANDOM_MEM[15:0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] + end // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17 + assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17] endmodule diff --git a/rtl/ITTAGE/data_mem_0_4x2.sv b/rtl/ITTAGE/data_mem_0_4x2.sv index c2c81d9..bc27f7b 100644 --- a/rtl/ITTAGE/data_mem_0_4x2.sv +++ b/rtl/ITTAGE/data_mem_0_4x2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_mem_0_4x2( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +module data_mem_0_4x2( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] input [1:0] R0_addr, input R0_en, input R0_clk, @@ -67,23 +67,23 @@ module data_mem_0_4x2( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 input [1:0] W0_data ); - reg [1:0] Memory[0:3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & 1'h1) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr] <= W0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [1:0] Memory[0:3]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + always @(posedge W0_clk) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & 1'h1) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr] <= W0_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef ENABLE_INITIAL_MEM_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + reg [31:0] _RANDOM_MEM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `ifdef RANDOMIZE_MEM_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[i[1:0]] = _RANDOM_MEM[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + _RANDOM_MEM = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[i[1:0]] = _RANDOM_MEM[1:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + end // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 2'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R0_data = R0_en ? Memory[R0_addr] : 2'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] endmodule diff --git a/rtl/RAS/RAS.sv b/rtl/RAS/RAS.sv index 6235572..35393ab 100644 --- a/rtl/RAS/RAS.sv +++ b/rtl/RAS/RAS.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,573 +55,584 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module RAS( // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - input clock, - input reset, - input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s3_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s3_redirect_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_NOS_value // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module RAS( // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + input clock, // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + input reset, // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_spec_info_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_spec_info_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_NOS_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_last_stage_spec_info_topAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_ras_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s3_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s3_redirect_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_cfi_idx_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_cfi_idx_bits, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_jmp_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_level, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_redirect_bits_cfiUpdate_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isRVC, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_redirect_bits_cfiUpdate_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_redirect_bits_cfiUpdate_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_NOS_value // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] ); - wire [38:0] _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [3:0] _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [2:0] _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [4:0] _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [4:0] _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [4:0] _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 - wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 - reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 - reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - wire [38:0] _s2_spec_new_addr_T_1 = - 39'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr - + {37'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0}); // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :637:45 - wire _s2_spec_pop_WIRE_0 = + wire [40:0] _RASStack_io_spec_pop_addr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [3:0] _RASStack_io_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [2:0] _RASStack_io_sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire _RASStack_io_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [4:0] _RASStack_io_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire _RASStack_io_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [4:0] _RASStack_io_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire _RASStack_io_NOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [4:0] _RASStack_io_NOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] + wire [35:0] _reset_vector_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + reg [40:0] s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s2_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s2_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86] + reg [40:0] s3_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg [40:0] s3_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86] + reg REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + reg REG_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + wire [40:0] _s2_spec_new_addr_T_1 = + 41'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + + {39'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0}); // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :637:45] + wire _s2_spec_pop_T_8 = io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 - & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s2_spec_pop_T_9 = io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] wire s2_spec_push = - io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit) & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) & io_in_bits_resp_in_0_s2_full_pred_2_hit & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:{67,70} + & io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :512:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:{67,70}] wire s2_spec_pop = - io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit) & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) & io_in_bits_resp_in_0_s2_full_pred_2_hit & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:70, :549:67 - wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:558:18 - reg [38:0] s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:574:25 - reg [38:0] s3_spec_new_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:575:35 - wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:583:18 - reg s3_pushed_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:592:34 - reg s3_popped_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:593:34 - wire _s3_pop_WIRE_0 = + & io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :512:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:70, :549:67] + wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable; // @[src/main/scala/xiangshan/frontend/newRAS.scala:558:18] + reg [40:0] s3_top; // @[src/main/scala/xiangshan/frontend/newRAS.scala:574:25] + reg [40:0] s3_spec_new_addr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:575:35] + wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable; // @[src/main/scala/xiangshan/frontend/newRAS.scala:583:18] + reg s3_pushed_in_s2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:592:34] + reg s3_popped_in_s2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:593:34] + wire _s3_pop_T_8 = io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 - & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s3_pop_T_9 = io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] wire s3_push = - ~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + ~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit) & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) & io_in_bits_resp_in_0_s3_full_pred_2_hit & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :513:44 + & io_in_bits_resp_in_0_s3_full_pred_2_is_call; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :512:5, :514:44] wire s3_pop = - ~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + ~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit) & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) & io_in_bits_resp_in_0_s3_full_pred_2_hit & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing - & io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :514:44 - reg [3:0] s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg [2:0] s3_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg [4:0] s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg [4:0] s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg [4:0] s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - reg redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [38:0] redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [3:0] redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [1:0] redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [4:0] redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [4:0] redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - reg [4:0] redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + & io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :512:5, :515:44] + reg [3:0] s3_meta_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg [2:0] s3_meta_sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg s3_meta_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg [4:0] s3_meta_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg s3_meta_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg [4:0] s3_meta_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg s3_meta_NOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg [4:0] s3_meta_NOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + reg redirect_next_valid_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg redirect_next_bits_r_level; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [40:0] redirect_next_bits_r_cfiUpdate_pc; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_pd_isRVC; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_pd_isCall; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_pd_isRet; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [3:0] redirect_next_bits_r_cfiUpdate_ssp; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [1:0] redirect_next_bits_r_cfiUpdate_sctr; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_TOSW_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] redirect_next_bits_r_cfiUpdate_TOSW_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_TOSR_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] redirect_next_bits_r_cfiUpdate_TOSR_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg redirect_next_bits_r_cfiUpdate_NOS_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] redirect_next_bits_r_cfiUpdate_NOS_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] wire _GEN_1 = - io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77 - wire [38:0] _GEN_2 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 - always @(posedge clock) begin - if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - s1_pc_dup_0 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_1 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_2 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_3 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:658:77] + wire [40:0] _GEN_2 = {5'h0, _reset_vector_delay_io_out}; // @[src/main/scala/xiangshan/frontend/BPU.scala:192:39, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/Hold.scala:100:23] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + if (REG_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + s1_pc_dup_0 <= _GEN_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_1 <= _GEN_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_2 <= _GEN_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_3 <= _GEN_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] end - else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + else begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + if (io_s0_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] end - if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 - if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - s3_top <= _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :574:25 - s3_spec_new_addr <= _s2_spec_new_addr_T_1; // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :575:35 - s3_pushed_in_s2 <= s2_spec_push; // src/main/scala/xiangshan/frontend/newRAS.scala:548:67, :592:34 - s3_popped_in_s2 <= s2_spec_pop; // src/main/scala/xiangshan/frontend/newRAS.scala:549:67, :593:34 - s3_meta_ssp <= _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_sctr <= _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_TOSW_value <= _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_TOSR_value <= _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_NOS_flag <= _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 - s3_meta_NOS_value <= _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + if (io_s1_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_0 <= s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + if (io_s1_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_1 <= s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + if (io_s1_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_2 <= s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + if (io_s1_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_pc_dup_3 <= s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86] + if (io_s2_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_0 <= s2_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + if (io_s2_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_1 <= s2_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + if (io_s2_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_2 <= s2_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + s3_top <= _RASStack_io_spec_pop_addr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :574:25] + s3_spec_new_addr <= _s2_spec_new_addr_T_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :575:35] + s3_pushed_in_s2 <= s2_spec_push; // @[src/main/scala/xiangshan/frontend/newRAS.scala:548:67, :592:34] + s3_popped_in_s2 <= s2_spec_pop; // @[src/main/scala/xiangshan/frontend/newRAS.scala:549:67, :593:34] + s3_meta_ssp <= _RASStack_io_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_sctr <= _RASStack_io_sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_TOSW_value <= _RASStack_io_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_TOSR_value <= _RASStack_io_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_NOS_flag <= _RASStack_io_NOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + s3_meta_NOS_value <= _RASStack_io_NOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26] + end + if (io_s2_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pc_dup_3 <= s2_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86] + REG <= reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + REG_1 <= REG & ~reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24,39,42}] + if (io_redirect_valid) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + redirect_next_bits_r_level <= io_redirect_bits_level; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] end - if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 - REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} - redirect_valid <= io_redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_level <= io_redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - redirect_bits_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + if (reset) // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + redirect_next_valid_last_r <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + else if (io_redirect_valid | redirect_next_valid_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + redirect_next_valid_last_r <= io_redirect_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - initial begin // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + logic [31:0] _RANDOM[0:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + initial begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - for (logic [4:0] i = 5'h0; i < 5'h15; i += 5'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - end // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s1_pc_dup_1 = {_RANDOM[5'h1][31:7], _RANDOM[5'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s1_pc_dup_2 = {_RANDOM[5'h2][31:14], _RANDOM[5'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s1_pc_dup_3 = {_RANDOM[5'h3][31:21], _RANDOM[5'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s2_pc_dup_0 = {_RANDOM[5'h4][31:28], _RANDOM[5'h5], _RANDOM[5'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s2_pc_dup_1 = {_RANDOM[5'h6][31:3], _RANDOM[5'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s2_pc_dup_2 = {_RANDOM[5'h7][31:10], _RANDOM[5'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s2_pc_dup_3 = {_RANDOM[5'h8][31:17], _RANDOM[5'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s3_pc_dup_0 = {_RANDOM[5'h9][31:24], _RANDOM[5'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s3_pc_dup_1 = {_RANDOM[5'hA][31], _RANDOM[5'hB], _RANDOM[5'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s3_pc_dup_2 = {_RANDOM[5'hC][31:6], _RANDOM[5'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s3_pc_dup_3 = {_RANDOM[5'hD][31:13], _RANDOM[5'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - REG = _RANDOM[5'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - REG_1 = _RANDOM[5'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - s3_top = {_RANDOM[5'hE][31:22], _RANDOM[5'hF][28:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25 - s3_spec_new_addr = {_RANDOM[5'hF][31:29], _RANDOM[5'h10], _RANDOM[5'h11][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :575:35 - s3_pushed_in_s2 = _RANDOM[5'h11][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :592:34 - s3_popped_in_s2 = _RANDOM[5'h11][5]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :593:34 - s3_meta_ssp = _RANDOM[5'h11][9:6]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_sctr = _RANDOM[5'h11][12:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_TOSW_flag = _RANDOM[5'h11][13]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_TOSW_value = _RANDOM[5'h11][18:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_TOSR_flag = _RANDOM[5'h11][19]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_TOSR_value = _RANDOM[5'h11][24:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_NOS_flag = _RANDOM[5'h11][25]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - s3_meta_NOS_value = _RANDOM[5'h11][30:26]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 - redirect_valid = _RANDOM[5'h11][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :621:25 - redirect_bits_level = _RANDOM[5'h12][21]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_pc = {_RANDOM[5'h12][31:23], _RANDOM[5'h13][29:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_pd_isRVC = _RANDOM[5'h13][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_pd_isCall = _RANDOM[5'h14][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_pd_isRet = _RANDOM[5'h14][3]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_ssp = _RANDOM[5'h14][7:4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_sctr = _RANDOM[5'h14][9:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_TOSW_flag = _RANDOM[5'h14][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_TOSW_value = _RANDOM[5'h14][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_TOSR_flag = _RANDOM[5'h14][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_TOSR_value = _RANDOM[5'h14][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_NOS_flag = _RANDOM[5'h14][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 - redirect_bits_cfiUpdate_NOS_value = _RANDOM[5'h14][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + end // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s2_pc_dup_0 = {_RANDOM[5'h5][31:4], _RANDOM[5'h6][12:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s2_pc_dup_1 = {_RANDOM[5'h6][31:13], _RANDOM[5'h7][21:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s2_pc_dup_2 = {_RANDOM[5'h7][31:22], _RANDOM[5'h8][30:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s2_pc_dup_3 = {_RANDOM[5'h8][31], _RANDOM[5'h9], _RANDOM[5'hA][7:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s3_pc_dup_0 = {_RANDOM[5'hA][31:8], _RANDOM[5'hB][16:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, :189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s3_pc_dup_1 = {_RANDOM[5'hB][31:17], _RANDOM[5'hC][25:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s3_pc_dup_2 = {_RANDOM[5'hC][31:26], _RANDOM[5'hD], _RANDOM[5'hE][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s3_pc_dup_3 = {_RANDOM[5'hE][31:3], _RANDOM[5'hF][11:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + REG = _RANDOM[5'hF][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, :191:24, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + REG_1 = _RANDOM[5'hF][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, :191:16, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + s3_top = {_RANDOM[5'hF][31:14], _RANDOM[5'h10][22:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25] + s3_spec_new_addr = {_RANDOM[5'h10][31:23], _RANDOM[5'h11]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :575:35] + s3_pushed_in_s2 = _RANDOM[5'h12][0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34] + s3_popped_in_s2 = _RANDOM[5'h12][1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :593:34] + s3_meta_ssp = _RANDOM[5'h12][5:2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_sctr = _RANDOM[5'h12][8:6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_TOSW_flag = _RANDOM[5'h12][9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_TOSW_value = _RANDOM[5'h12][14:10]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_TOSR_flag = _RANDOM[5'h12][15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_TOSR_value = _RANDOM[5'h12][20:16]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_NOS_flag = _RANDOM[5'h12][21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + s3_meta_NOS_value = _RANDOM[5'h12][26:22]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, :603:26] + redirect_next_valid_last_r = _RANDOM[5'h12][27]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :592:34, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + redirect_next_bits_r_level = _RANDOM[5'h13][17]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pc = {_RANDOM[5'h13][31:19], _RANDOM[5'h14][27:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[5'h14][29]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[5'h15][0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[5'h15][1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_ssp = _RANDOM[5'h15][5:2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_sctr = _RANDOM[5'h15][7:6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[5'h15][8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[5'h15][13:9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[5'h15][14]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[5'h15][19:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[5'h15][20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + redirect_next_bits_r_cfiUpdate_NOS_value = _RANDOM[5'h15][25:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, utility/src/main/scala/utility/BitUtils.scala:33:27] `endif // RANDOMIZE_REG_INIT + if (reset) // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + redirect_next_valid_last_r = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_2 reset_vector_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in (io_reset_vector), .io_out (_reset_vector_delay_io_out) ); - RASStack RASStack ( // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + RASStack RASStack ( // @[src/main/scala/xiangshan/frontend/newRAS.scala:536:21] .clock (clock), .reset (reset), - .io_spec_push_valid (s2_spec_push), // src/main/scala/xiangshan/frontend/newRAS.scala:548:67 - .io_spec_pop_valid (s2_spec_pop), // src/main/scala/xiangshan/frontend/newRAS.scala:549:67 - .io_spec_push_addr (_s2_spec_new_addr_T_1), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55 + .io_spec_push_valid (s2_spec_push), // @[src/main/scala/xiangshan/frontend/newRAS.scala:548:67] + .io_spec_pop_valid (s2_spec_pop), // @[src/main/scala/xiangshan/frontend/newRAS.scala:549:67] + .io_spec_push_addr (_s2_spec_new_addr_T_1), // @[src/main/scala/xiangshan/frontend/newRAS.scala:542:55] .io_s2_fire (io_s2_fire_2), .io_s3_fire (io_s3_fire_2), .io_s3_cancel - (io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, :514:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :593:34, :597:{33,53,65,84} - .io_s3_meta_ssp (s3_meta_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_sctr (s3_meta_sctr), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_TOSW_flag (s3_meta_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_TOSW_value (s3_meta_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_TOSR_flag (s3_meta_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_TOSR_value (s3_meta_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_NOS_flag (s3_meta_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_meta_NOS_value (s3_meta_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 - .io_s3_missed_pop (s3_pop & ~s3_popped_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:514:44, src/main/scala/xiangshan/frontend/newRAS.scala:593:34, :606:{33,36} - .io_s3_missed_push (s3_push & ~s3_pushed_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :607:{35,38} - .io_s3_pushAddr (s3_spec_new_addr), // src/main/scala/xiangshan/frontend/newRAS.scala:575:35 + (io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:514:44, :515:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :593:34, :597:{33,53,65,84}] + .io_s3_meta_ssp (s3_meta_ssp), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_sctr (s3_meta_sctr), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_TOSW_flag (s3_meta_TOSW_flag), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_TOSW_value (s3_meta_TOSW_value), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_TOSR_flag (s3_meta_TOSR_flag), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_TOSR_value (s3_meta_TOSR_value), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_NOS_flag (s3_meta_NOS_flag), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_meta_NOS_value (s3_meta_NOS_value), // @[src/main/scala/xiangshan/frontend/newRAS.scala:603:26] + .io_s3_missed_pop (s3_pop & ~s3_popped_in_s2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:515:44, src/main/scala/xiangshan/frontend/newRAS.scala:593:34, :606:{33,36}] + .io_s3_missed_push (s3_push & ~s3_pushed_in_s2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:514:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :607:{35,38}] + .io_s3_pushAddr (s3_spec_new_addr), // @[src/main/scala/xiangshan/frontend/newRAS.scala:575:35] .io_spec_pop_addr (_RASStack_io_spec_pop_addr), .io_commit_push_valid (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken - & io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:643:42 + & io_update_bits_cfi_idx_valid & _GEN_1), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:658:77, src/main/scala/xiangshan/frontend/newRAS.scala:643:42] .io_commit_pop_valid (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken - & io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:644:41 - .io_commit_meta_TOSW_flag (io_update_bits_meta[17]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 - .io_commit_meta_TOSW_value (io_update_bits_meta[16:12]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 - .io_commit_meta_ssp (io_update_bits_meta[24:21]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 - .io_redirect_valid (redirect_valid), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + & io_update_bits_cfi_idx_valid & _GEN_1), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:658:77, src/main/scala/xiangshan/frontend/newRAS.scala:644:41] + .io_commit_meta_TOSW_flag (io_update_bits_meta[17]), // @[src/main/scala/xiangshan/frontend/newRAS.scala:640:48] + .io_commit_meta_TOSW_value (io_update_bits_meta[16:12]), // @[src/main/scala/xiangshan/frontend/newRAS.scala:640:48] + .io_commit_meta_ssp (io_update_bits_meta[24:21]), // @[src/main/scala/xiangshan/frontend/newRAS.scala:640:48] + .io_redirect_valid (redirect_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .io_redirect_isCall - (redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:56, :626:64 + (redirect_next_valid_last_r & ~redirect_next_bits_r_level + & redirect_next_bits_r_cfiUpdate_pd_isCall), // @[src/main/scala/xiangshan/frontend/newRAS.scala:625:56, :626:64, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .io_redirect_isRet - (redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:{56,64} - .io_redirect_meta_ssp (redirect_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_sctr ({1'h0, redirect_bits_cfiUpdate_sctr}), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :621:25, :633:28 - .io_redirect_meta_TOSW_flag (redirect_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_TOSW_value (redirect_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_TOSR_flag (redirect_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_TOSR_value (redirect_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_NOS_flag (redirect_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 - .io_redirect_meta_NOS_value (redirect_bits_cfiUpdate_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + (redirect_next_valid_last_r & ~redirect_next_bits_r_level + & redirect_next_bits_r_cfiUpdate_pd_isRet), // @[src/main/scala/xiangshan/frontend/newRAS.scala:625:{56,64}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .io_redirect_meta_ssp (redirect_next_bits_r_cfiUpdate_ssp), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_sctr ({1'h0, redirect_next_bits_r_cfiUpdate_sctr}), // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, src/main/scala/xiangshan/frontend/newRAS.scala:633:28, utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_TOSW_flag (redirect_next_bits_r_cfiUpdate_TOSW_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_TOSW_value (redirect_next_bits_r_cfiUpdate_TOSW_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_TOSR_flag (redirect_next_bits_r_cfiUpdate_TOSR_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_TOSR_value (redirect_next_bits_r_cfiUpdate_TOSR_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_NOS_flag (redirect_next_bits_r_cfiUpdate_NOS_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_redirect_meta_NOS_value (redirect_next_bits_r_cfiUpdate_NOS_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_callAddr - (39'(redirect_bits_cfiUpdate_pc - + {36'h0, redirect_bits_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :637:{45,50} + (41'(redirect_next_bits_r_cfiUpdate_pc + + {38'h0, redirect_next_bits_r_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})), // @[src/main/scala/xiangshan/frontend/newRAS.scala:637:{45,50}, utility/src/main/scala/utility/BitUtils.scala:33:27] .io_ssp (_RASStack_io_ssp), .io_sctr (_RASStack_io_sctr), .io_TOSR_flag (_RASStack_io_TOSR_flag), @@ -631,188 +642,188 @@ module RAS( // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 .io_NOS_flag (_RASStack_io_NOS_flag), .io_NOS_value (_RASStack_io_NOS_value) ); - assign io_out_s2_pc_0 = s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_pc_1 = s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_pc_2 = s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_pc_3 = s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_pc_0 = s2_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_pc_1 = s2_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_pc_2 = s2_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_pc_3 = s2_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr ? (_GEN ? _RASStack_io_spec_pop_addr : io_in_bits_resp_in_0_s2_full_pred_0_jalr_target) - : io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 - assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + : io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26] + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_0_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr ? (_GEN ? _RASStack_io_spec_pop_addr : io_in_bits_resp_in_0_s2_full_pred_1_jalr_target) - : io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 - assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + : io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26] + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_1_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr ? (_GEN ? _RASStack_io_spec_pop_addr : io_in_bits_resp_in_0_s2_full_pred_2_jalr_target) - : io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 - assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + : io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26] + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_2_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_br_taken_mask_0 = - io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_br_taken_mask_1 = - io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_slot_valids_0 = - io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_slot_valids_1 = - io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr ? (_GEN ? _RASStack_io_spec_pop_addr : io_in_bits_resp_in_0_s2_full_pred_3_jalr_target) - : io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 - assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + : io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26] + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_fallThroughAddr = - io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_fallThroughErr = - io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s2_full_pred_3_is_br_sharing = - io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_pc_0 = s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_pc_1 = s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_pc_2 = s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_pc_3 = s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_pc_0 = s3_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_pc_1 = s3_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_pc_2 = s3_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_pc_3 = s3_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:189:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target) - : io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + : io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26] assign io_out_s3_full_pred_0_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_0_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target) - : io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + : io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26] assign io_out_s3_full_pred_1_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_1_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target) - : io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + : io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26] assign io_out_s3_full_pred_2_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_2_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_br_taken_mask_0 = - io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_br_taken_mask_1 = - io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_slot_valids_0 = - io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_slot_valids_1 = - io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target) - : io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 - assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + : io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26] + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_fallThroughAddr = - io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_fallThroughErr = - io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_s3_full_pred_3_is_br_sharing = - io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 - assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_meta = - {194'h0, + {198'h0, s3_meta_ssp, s3_meta_sctr, s3_meta_TOSW_flag, @@ -820,53 +831,53 @@ module RAS( // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 s3_meta_TOSR_flag, s3_meta_TOSR_value, s3_meta_NOS_flag, - s3_meta_NOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :618:26 - assign io_out_last_stage_spec_info_ssp = s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :612:37 - assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 - assign io_out_last_stage_spec_info_topAddr = s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25 + s3_meta_NOS_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :618:26] + assign io_out_last_stage_spec_info_ssp = s3_meta_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :612:37] + assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26] + assign io_out_last_stage_spec_info_topAddr = s3_top; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25] assign io_out_last_stage_ftb_entry_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_brSlots_0_offset = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_brSlots_0_lower = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_brSlots_0_sharing = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_brSlots_0_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_tailSlot_offset = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_tailSlot_lower = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_tailSlot_tarStat = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_tailSlot_sharing = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_tailSlot_valid = - io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_pftAddr = - io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_carry = - io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_isCall = - io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_isRet = - io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_isJalr = - io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = - io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_always_taken_0 = - io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] assign io_out_last_stage_ftb_entry_always_taken_1 = - io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:75:7] endmodule diff --git a/rtl/RAS/RASStack.sv b/rtl/RAS/RASStack.sv index 50652e1..d396a7c 100644 --- a/rtl/RAS/RASStack.sv +++ b/rtl/RAS/RASStack.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,234 +55,234 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - input clock, - input reset, - input io_spec_push_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_spec_pop_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [38:0] io_spec_push_addr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s2_fire, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_fire, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_cancel, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [3:0] io_s3_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [2:0] io_s3_meta_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_s3_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_meta_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_s3_meta_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_meta_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_s3_meta_NOS_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_missed_pop, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_s3_missed_push, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [38:0] io_s3_pushAddr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [38:0] io_spec_pop_addr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_commit_push_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_commit_pop_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_commit_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_commit_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [3:0] io_commit_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_isCall, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_isRet, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [3:0] io_redirect_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [2:0] io_redirect_meta_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_redirect_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_meta_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_redirect_meta_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input io_redirect_meta_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [4:0] io_redirect_meta_NOS_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - input [38:0] io_redirect_callAddr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [3:0] io_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [2:0] io_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output io_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [4:0] io_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output io_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [4:0] io_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output io_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - output [4:0] io_NOS_value // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 +module RASStack( // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + input clock, // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + input reset, // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + input io_spec_push_valid, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_spec_pop_valid, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [40:0] io_spec_push_addr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s2_fire, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_fire, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_cancel, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [3:0] io_s3_meta_ssp, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [2:0] io_s3_meta_sctr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_meta_TOSW_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_s3_meta_TOSW_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_meta_TOSR_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_s3_meta_TOSR_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_meta_NOS_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_s3_meta_NOS_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_missed_pop, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_s3_missed_push, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [40:0] io_s3_pushAddr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [40:0] io_spec_pop_addr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_commit_push_valid, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_commit_pop_valid, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_commit_meta_TOSW_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_commit_meta_TOSW_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [3:0] io_commit_meta_ssp, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_valid, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_isCall, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_isRet, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [3:0] io_redirect_meta_ssp, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [2:0] io_redirect_meta_sctr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_meta_TOSW_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_redirect_meta_TOSW_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_meta_TOSR_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_redirect_meta_TOSR_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input io_redirect_meta_NOS_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [4:0] io_redirect_meta_NOS_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + input [40:0] io_redirect_callAddr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [3:0] io_ssp, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [2:0] io_sctr, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output io_TOSR_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [4:0] io_TOSR_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output io_TOSW_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [4:0] io_TOSW_value, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output io_NOS_flag, // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + output [4:0] io_NOS_value // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] ); - reg [38:0] commit_stack_0_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_0_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_1_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_1_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_2_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_2_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_3_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_3_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_4_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_4_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_5_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_5_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_6_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_6_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_7_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_7_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_8_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_8_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_9_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_9_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_10_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_10_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_11_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_11_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_12_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_12_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_13_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_13_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_14_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_14_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] commit_stack_15_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [7:0] commit_stack_15_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 - reg [38:0] spec_queue_0_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_0_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_1_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_1_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_2_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_2_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_3_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_3_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_4_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_4_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_5_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_5_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_6_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_6_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_7_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_7_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_8_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_8_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_9_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_9_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_10_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_10_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_11_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_11_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_12_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_12_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_13_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_13_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_14_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_14_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_15_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_15_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_16_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_16_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_17_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_17_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_18_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_18_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_19_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_19_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_20_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_20_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_21_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_21_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_22_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_22_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_23_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_23_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_24_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_24_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_25_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_25_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_26_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_26_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_27_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_27_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_28_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_28_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_29_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_29_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_30_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_30_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [38:0] spec_queue_31_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg [7:0] spec_queue_31_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 - reg spec_nos_0_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_0_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_1_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_1_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_2_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_2_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_3_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_3_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_4_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_4_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_5_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_5_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_6_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_6_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_7_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_7_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_8_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_8_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_9_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_9_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_10_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_10_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_11_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_11_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_12_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_12_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_13_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_13_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_14_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_14_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_15_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_15_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_16_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_16_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_17_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_17_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_18_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_18_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_19_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_19_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_20_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_20_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_21_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_21_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_22_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_22_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_23_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_23_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_24_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_24_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_25_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_25_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_26_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_26_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_27_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_27_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_28_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_28_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_29_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_29_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_30_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_30_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg spec_nos_31_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [4:0] spec_nos_31_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 - reg [3:0] nsp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 - reg [3:0] ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22 - reg [2:0] sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 - reg TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23 - reg [4:0] TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23 - reg TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23 - reg [4:0] TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23 - reg BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22 - reg [4:0] BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22 - reg spec_overflowed; // src/main/scala/xiangshan/frontend/newRAS.scala:146:34 - reg [38:0] writeBypassEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31 - reg [7:0] writeBypassEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31 - reg writeBypassNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29 - reg [4:0] writeBypassNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29 - reg writeBypassValid; // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 - wire _realPush_T_4 = io_redirect_valid & io_redirect_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29 - wire _GEN = TOSR_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + reg [40:0] commit_stack_0_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_0_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_1_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_1_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_2_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_2_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_3_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_3_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_4_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_4_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_5_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_5_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_6_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_6_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_7_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_7_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_8_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_8_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_9_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_9_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_10_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_10_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_11_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_11_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_12_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_12_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_13_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_13_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_14_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_14_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] commit_stack_15_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [7:0] commit_stack_15_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31] + reg [40:0] spec_queue_0_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_0_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_1_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_1_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_2_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_2_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_3_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_3_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_4_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_4_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_5_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_5_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_6_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_6_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_7_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_7_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_8_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_8_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_9_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_9_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_10_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_10_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_11_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_11_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_12_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_12_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_13_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_13_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_14_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_14_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_15_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_15_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_16_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_16_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_17_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_17_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_18_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_18_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_19_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_19_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_20_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_20_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_21_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_21_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_22_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_22_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_23_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_23_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_24_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_24_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_25_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_25_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_26_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_26_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_27_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_27_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_28_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_28_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_29_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_29_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_30_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_30_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [40:0] spec_queue_31_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg [7:0] spec_queue_31_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29] + reg spec_nos_0_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_0_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_1_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_1_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_2_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_2_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_3_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_3_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_4_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_4_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_5_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_5_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_6_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_6_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_7_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_7_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_8_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_8_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_9_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_9_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_10_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_10_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_11_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_11_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_12_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_12_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_13_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_13_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_14_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_14_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_15_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_15_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_16_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_16_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_17_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_17_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_18_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_18_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_19_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_19_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_20_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_20_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_21_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_21_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_22_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_22_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_23_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_23_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_24_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_24_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_25_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_25_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_26_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_26_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_27_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_27_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_28_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_28_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_29_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_29_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_30_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_30_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg spec_nos_31_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [4:0] spec_nos_31_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27] + reg [3:0] nsp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22] + reg [3:0] ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22] + reg [2:0] sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23] + reg TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23] + reg [4:0] TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23] + reg TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23] + reg [4:0] TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23] + reg BOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22] + reg [4:0] BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22] + reg spec_overflowed; // @[src/main/scala/xiangshan/frontend/newRAS.scala:146:34] + reg [40:0] writeBypassEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:148:31] + reg [7:0] writeBypassEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:148:31] + reg writeBypassNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:149:29] + reg [4:0] writeBypassNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:149:29] + reg writeBypassValid; // @[src/main/scala/xiangshan/frontend/newRAS.scala:151:35] + wire _realPush_T_4 = io_redirect_valid & io_redirect_isCall; // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29] + wire _GEN = TOSR_value >= BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] wire topEntry_inflightValid = - (TOSR_flag ^ BOS_flag ^ _GEN) & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 - wire [31:0][38:0] _GEN_0 = + (TOSR_flag ^ BOS_flag ^ _GEN) & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value); // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19] + wire [31:0][40:0] _GEN_0 = {{spec_queue_31_retAddr}, {spec_queue_30_retAddr}, {spec_queue_29_retAddr}, @@ -314,8 +314,8 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {spec_queue_3_retAddr}, {spec_queue_2_retAddr}, {spec_queue_1_retAddr}, - {spec_queue_0_retAddr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15 - wire [38:0] _GEN_1 = _GEN_0[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :187:15 + {spec_queue_0_retAddr}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15] + wire [40:0] _GEN_1 = _GEN_0[TOSR_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :187:15] wire [31:0][7:0] _GEN_2 = {{spec_queue_31_ctr}, {spec_queue_30_ctr}, @@ -348,8 +348,8 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {spec_queue_3_ctr}, {spec_queue_2_ctr}, {spec_queue_1_ctr}, - {spec_queue_0_ctr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15 - wire [15:0][38:0] _GEN_3 = + {spec_queue_0_ctr}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15] + wire [15:0][40:0] _GEN_3 = {{commit_stack_15_retAddr}, {commit_stack_14_retAddr}, {commit_stack_13_retAddr}, @@ -365,8 +365,8 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {commit_stack_3_retAddr}, {commit_stack_2_retAddr}, {commit_stack_1_retAddr}, - {commit_stack_0_retAddr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15 - wire [38:0] _GEN_4 = _GEN_3[ssp]; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :189:15 + {commit_stack_0_retAddr}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15] + wire [40:0] _GEN_4 = _GEN_3[ssp]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :189:15] wire [15:0][7:0] _GEN_5 = {{commit_stack_15_ctr}, {commit_stack_14_ctr}, @@ -383,7 +383,7 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {commit_stack_3_ctr}, {commit_stack_2_ctr}, {commit_stack_1_ctr}, - {commit_stack_0_ctr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15 + {commit_stack_0_ctr}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15] wire [31:0] _GEN_6 = {{spec_nos_31_flag}, {spec_nos_30_flag}, @@ -416,7 +416,7 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {spec_nos_3_flag}, {spec_nos_2_flag}, {spec_nos_1_flag}, - {spec_nos_0_flag}}; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15 + {spec_nos_0_flag}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15] wire [31:0][4:0] _GEN_7 = {{spec_nos_31_value}, {spec_nos_30_value}, @@ -449,72 +449,72 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 {spec_nos_3_value}, {spec_nos_2_value}, {spec_nos_1_value}, - {spec_nos_0_value}}; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15 - wire [4:0] _GEN_8 = _GEN_7[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15 + {spec_nos_0_value}}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15] + wire [4:0] _GEN_8 = _GEN_7[TOSR_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15] wire topNos_flag = - writeBypassValid ? writeBypassNos_flag : _GEN_6[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :151:35, :170:33, :171:15, :173:15 - wire [4:0] topNos_value = writeBypassValid ? writeBypassNos_value : _GEN_8; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29, :151:35, :170:33, :171:15, :173:15 - wire differentFlag_15 = io_redirect_meta_TOSR_flag ^ BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 - wire compare_15 = io_redirect_meta_TOSR_value < BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + writeBypassValid ? writeBypassNos_flag : _GEN_6[TOSR_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :151:35, :170:33, :171:15, :173:15] + wire [4:0] topNos_value = writeBypassValid ? writeBypassNos_value : _GEN_8; // @[src/main/scala/xiangshan/frontend/newRAS.scala:149:29, :151:35, :170:33, :171:15, :173:15] + wire differentFlag_15 = io_redirect_meta_TOSR_flag ^ BOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35] + wire compare_15 = io_redirect_meta_TOSR_value < BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] wire differentFlag_16 = - io_redirect_meta_TOSR_flag ^ io_redirect_meta_TOSW_flag; // utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 + io_redirect_meta_TOSR_flag ^ io_redirect_meta_TOSW_flag; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:72:35] wire compare_16 = - io_redirect_meta_TOSR_value < io_redirect_meta_TOSW_value; // utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + io_redirect_meta_TOSR_value < io_redirect_meta_TOSW_value; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] wire redirectTopEntry_inflightValid = - (differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 - wire [38:0] writeEntry_retAddr = - _realPush_T_4 ? io_redirect_callAddr : io_spec_push_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :244:30 + (differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19] + wire [40:0] writeEntry_retAddr = + _realPush_T_4 ? io_redirect_callAddr : io_spec_push_addr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :244:30] wire _writeEntry_ctr_T_1 = (redirectTopEntry_inflightValid ? _GEN_0[io_redirect_meta_TOSR_value] - : _GEN_3[io_redirect_meta_ssp]) == io_redirect_callAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:36 - wire [2:0] _sctr_T_12 = 3'(io_redirect_meta_sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:246:117, :478:38 + : _GEN_3[io_redirect_meta_ssp]) == io_redirect_callAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:36] + wire [2:0] _sctr_T_12 = 3'(io_redirect_meta_sctr + 3'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:246:117, :478:38] wire _writeEntry_ctr_T_7 = (writeBypassValid ? writeBypassEntry_retAddr - : topEntry_inflightValid ? _GEN_1 : _GEN_4) == io_spec_push_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :247:28 - wire [2:0] _sctr_T = 3'(sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81, :478:38 - reg [38:0] timingTop_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:259:28 - reg [38:0] realWriteEntry_next_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40 - reg [7:0] realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40 - wire _GEN_9 = io_redirect_isCall | ~io_s3_missed_push; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - wire [38:0] realWriteEntry_retAddr = - _GEN_9 ? realWriteEntry_next_retAddr : io_s3_pushAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40, :373:26 - reg [4:0] realWriteAddr_next_value; // src/main/scala/xiangshan/frontend/newRAS.scala:377:39 - reg realNos_next_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:381:33 - reg [4:0] realNos_next_value; // src/main/scala/xiangshan/frontend/newRAS.scala:381:33 - reg realPush_r; // src/main/scala/xiangshan/frontend/newRAS.scala:386:59 - reg realPush_REG; // src/main/scala/xiangshan/frontend/newRAS.scala:386:125 + : topEntry_inflightValid ? _GEN_1 : _GEN_4) == io_spec_push_addr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :247:28] + wire [2:0] _sctr_T = 3'(sctr + 3'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81, :478:38] + reg [40:0] timingTop_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:259:28] + reg [40:0] realWriteEntry_next_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:361:40] + reg [7:0] realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:361:40] + wire _GEN_9 = io_redirect_isCall | ~io_s3_missed_push; // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + wire [40:0] realWriteEntry_retAddr = + _GEN_9 ? realWriteEntry_next_retAddr : io_s3_pushAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:361:40, :373:26] + reg [4:0] realWriteAddr_next_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:377:39] + reg realNos_next_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:381:33] + reg [4:0] realNos_next_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:381:33] + reg realPush_r; // @[src/main/scala/xiangshan/frontend/newRAS.scala:386:59] + reg realPush_REG; // @[src/main/scala/xiangshan/frontend/newRAS.scala:386:125] wire realPush = - io_s3_fire & (~io_s3_cancel & realPush_r | io_s3_missed_push) | realPush_REG; // src/main/scala/xiangshan/frontend/newRAS.scala:386:{29,33,47,59,92,115,125} - wire _GEN_10 = _writeEntry_ctr_T_1 & io_redirect_meta_sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:246:{36,85}, :397:{42,57} + io_s3_fire & (~io_s3_cancel & realPush_r | io_s3_missed_push) | realPush_REG; // @[src/main/scala/xiangshan/frontend/newRAS.scala:386:{29,33,47,59,92,115,125}] + wire _GEN_10 = _writeEntry_ctr_T_1 & io_redirect_meta_sctr != 3'h7; // @[src/main/scala/xiangshan/frontend/newRAS.scala:246:{36,85}, :397:{42,57}] wire _GEN_11 = io_redirect_isRet & (differentFlag_15 ^ ~compare_15) - & (differentFlag_16 ^ compare_16); // src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :523:33, :526:32, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 - wire [3:0] _sctr_T_16 = 4'(io_redirect_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:206:33 - wire [3:0] _sctr_T_8 = 4'(io_s3_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:206:33 - wire _GEN_12 = _writeEntry_ctr_T_7 & sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :246:85, :247:28, :397:{42,57} - wire [3:0] _sctr_T_4 = 4'(ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 + & (differentFlag_16 ^ compare_16); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :523:33, :526:32, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19] + wire [3:0] _sctr_T_16 = 4'(io_redirect_meta_ssp - 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:206:33] + wire [3:0] _sctr_T_8 = 4'(io_s3_meta_ssp - 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:206:33] + wire _GEN_12 = _writeEntry_ctr_T_7 & sctr != 3'h7; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :246:85, :247:28, :397:{42,57}] + wire [3:0] _sctr_T_4 = 4'(ssp - 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33] wire writeBypassValidWire = _realPush_T_4 | ~io_redirect_valid - & (io_s2_fire ? io_spec_push_valid : ~io_s3_fire & writeBypassValid); // src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:{29,52}, :218:24, :219:37, :222:24, :223:30, :225:24, :226:30, :228:24 - wire differentFlag_10 = io_s3_meta_TOSR_flag ^ BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 - wire compare_10 = io_s3_meta_TOSR_value < BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire differentFlag_11 = io_s3_meta_TOSR_flag ^ io_s3_meta_TOSW_flag; // utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 - wire compare_11 = io_s3_meta_TOSR_value < io_s3_meta_TOSW_value; // utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + & (io_s2_fire ? io_spec_push_valid : ~io_s3_fire & writeBypassValid); // @[src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:{29,52}, :218:24, :219:37, :222:24, :223:30, :225:24, :226:30, :228:24] + wire differentFlag_10 = io_s3_meta_TOSR_flag ^ BOS_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35] + wire compare_10 = io_s3_meta_TOSR_value < BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire differentFlag_11 = io_s3_meta_TOSR_flag ^ io_s3_meta_TOSW_flag; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:72:35] + wire compare_11 = io_s3_meta_TOSR_value < io_s3_meta_TOSW_value; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] wire s3TopEntry_inflightValid = - (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 - wire _GEN_13 = io_redirect_meta_NOS_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire _GEN_14 = io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire _GEN_15 = topNos_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire _GEN_16 = topNos_flag ^ BOS_flag ^ _GEN_15; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire _GEN_17 = io_s3_meta_NOS_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 - wire _GEN_18 = io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19] + wire _GEN_13 = io_redirect_meta_NOS_value >= BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire _GEN_14 = io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire _GEN_15 = topNos_value >= BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire _GEN_16 = topNos_flag ^ BOS_flag ^ _GEN_15; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire _GEN_17 = io_s3_meta_NOS_value >= BOS_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] + wire _GEN_18 = io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30] wire _s3_missPushEntry_ctr_T = (s3TopEntry_inflightValid ? _GEN_0[io_s3_meta_TOSR_value] - : _GEN_3[io_s3_meta_ssp]) == io_s3_pushAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :367:52 - wire [2:0] _sctr_T_10 = 3'(io_s3_meta_sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:367:115, :478:38 + : _GEN_3[io_s3_meta_ssp]) == io_s3_pushAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :367:52] + wire [2:0] _sctr_T_10 = 3'(io_s3_meta_sctr + 3'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:367:115, :478:38] wire [7:0] s3_missPushEntry_ctr = {5'h0, _s3_missPushEntry_ctr_T @@ -522,809 +522,808 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 ? _GEN_2[io_s3_meta_TOSR_value] : _GEN_5[io_s3_meta_ssp]) < 8'h7 ? _sctr_T_10 - : 3'h0}; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:85, :260:41, :367:{26,32,52,71,89,115} + : 3'h0}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:85, :260:41, :367:{26,32,52,71,89,115}] wire [4:0] realWriteAddr_value = - _GEN_9 ? realWriteAddr_next_value : io_s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :377:39, :378:28 - wire realNos_flag = _GEN_9 ? realNos_next_flag : io_s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22 - wire [4:0] realNos_value = _GEN_9 ? realNos_next_value : io_s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22 - wire [5:0] _GEN_19 = {TOSW_flag, TOSW_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _GEN_20 = {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_9 ? realWriteAddr_next_value : io_s3_meta_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :377:39, :378:28] + wire realNos_flag = _GEN_9 ? realNos_next_flag : io_s3_meta_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22] + wire [4:0] realNos_value = _GEN_9 ? realNos_next_value : io_s3_meta_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22] + wire [5:0] _GEN_19 = {TOSW_flag, TOSW_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _GEN_20 = {BOS_flag, BOS_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire _GEN_21 = - io_spec_push_valid & 6'(_GEN_19 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} - wire [5:0] _GEN_22 = {io_s3_meta_TOSW_flag, io_s3_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire _GEN_23 = 6'(_GEN_22 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} - wire [7:0] _GEN_24 = _GEN_5[nsp]; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :189:15, :477:27 - wire [7:0] _commit_stack_ctr_T = 8'(_GEN_24 - 8'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55 - wire _GEN_25 = io_commit_meta_ssp == 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :478:38 - wire _GEN_26 = io_commit_pop_valid & (|_GEN_24) & _GEN_25; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_27 = io_commit_meta_ssp == 4'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_28 = io_commit_pop_valid & (|_GEN_24) & _GEN_27; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_29 = io_commit_meta_ssp == 4'h2; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_30 = io_commit_pop_valid & (|_GEN_24) & _GEN_29; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_31 = io_commit_meta_ssp == 4'h3; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_32 = io_commit_pop_valid & (|_GEN_24) & _GEN_31; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_33 = io_commit_meta_ssp == 4'h4; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_34 = io_commit_pop_valid & (|_GEN_24) & _GEN_33; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_35 = io_commit_meta_ssp == 4'h5; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_36 = io_commit_pop_valid & (|_GEN_24) & _GEN_35; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_37 = io_commit_meta_ssp == 4'h6; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_38 = io_commit_pop_valid & (|_GEN_24) & _GEN_37; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_39 = io_commit_meta_ssp == 4'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_40 = io_commit_pop_valid & (|_GEN_24) & _GEN_39; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_41 = io_commit_meta_ssp == 4'h8; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_42 = io_commit_pop_valid & (|_GEN_24) & _GEN_41; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_43 = io_commit_meta_ssp == 4'h9; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_44 = io_commit_pop_valid & (|_GEN_24) & _GEN_43; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_45 = io_commit_meta_ssp == 4'hA; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_46 = io_commit_pop_valid & (|_GEN_24) & _GEN_45; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_47 = io_commit_meta_ssp == 4'hB; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_48 = io_commit_pop_valid & (|_GEN_24) & _GEN_47; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_49 = io_commit_meta_ssp == 4'hC; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_50 = io_commit_pop_valid & (|_GEN_24) & _GEN_49; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_51 = io_commit_meta_ssp == 4'hD; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_52 = io_commit_pop_valid & (|_GEN_24) & _GEN_51; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_53 = io_commit_meta_ssp == 4'hE; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - wire _GEN_54 = io_commit_pop_valid & (|_GEN_24) & _GEN_53; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 - wire _GEN_55 = io_commit_pop_valid & (|_GEN_24) & (&io_commit_meta_ssp); // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + io_spec_push_valid & 6'(_GEN_19 + 6'h1) == {BOS_flag, BOS_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56}] + wire [5:0] _GEN_22 = {io_s3_meta_TOSW_flag, io_s3_meta_TOSW_value}; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire _GEN_23 = 6'(_GEN_22 + 6'h1) == {BOS_flag, BOS_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56}] + wire [7:0] _GEN_24 = _GEN_5[nsp]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :189:15, :477:27] + wire [7:0] _commit_stack_ctr_T = 8'(_GEN_24 - 8'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55] + wire _GEN_25 = io_commit_meta_ssp == 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :478:38] + wire _GEN_26 = io_commit_pop_valid & (|_GEN_24) & _GEN_25; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_27 = io_commit_meta_ssp == 4'h1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_28 = io_commit_pop_valid & (|_GEN_24) & _GEN_27; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_29 = io_commit_meta_ssp == 4'h2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_30 = io_commit_pop_valid & (|_GEN_24) & _GEN_29; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_31 = io_commit_meta_ssp == 4'h3; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_32 = io_commit_pop_valid & (|_GEN_24) & _GEN_31; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_33 = io_commit_meta_ssp == 4'h4; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_34 = io_commit_pop_valid & (|_GEN_24) & _GEN_33; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_35 = io_commit_meta_ssp == 4'h5; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_36 = io_commit_pop_valid & (|_GEN_24) & _GEN_35; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_37 = io_commit_meta_ssp == 4'h6; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_38 = io_commit_pop_valid & (|_GEN_24) & _GEN_37; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_39 = io_commit_meta_ssp == 4'h7; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_40 = io_commit_pop_valid & (|_GEN_24) & _GEN_39; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_41 = io_commit_meta_ssp == 4'h8; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_42 = io_commit_pop_valid & (|_GEN_24) & _GEN_41; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_43 = io_commit_meta_ssp == 4'h9; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_44 = io_commit_pop_valid & (|_GEN_24) & _GEN_43; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_45 = io_commit_meta_ssp == 4'hA; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_46 = io_commit_pop_valid & (|_GEN_24) & _GEN_45; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_47 = io_commit_meta_ssp == 4'hB; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_48 = io_commit_pop_valid & (|_GEN_24) & _GEN_47; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_49 = io_commit_meta_ssp == 4'hC; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_50 = io_commit_pop_valid & (|_GEN_24) & _GEN_49; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_51 = io_commit_meta_ssp == 4'hD; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_52 = io_commit_pop_valid & (|_GEN_24) & _GEN_51; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_53 = io_commit_meta_ssp == 4'hE; // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + wire _GEN_54 = io_commit_pop_valid & (|_GEN_24) & _GEN_53; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] + wire _GEN_55 = io_commit_pop_valid & (|_GEN_24) & (&io_commit_meta_ssp); // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38] wire _GEN_56 = - _GEN_24 < 8'h7 & _GEN_3[nsp] == _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :187:15, :189:15, :246:85, :477:27, :499:{27,36,57} - wire [3:0] _nsp_T_2 = 4'(io_commit_meta_ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38 - wire _GEN_57 = _nsp_T_2 == 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33, :504:50 - wire _GEN_58 = _nsp_T_2 == 4'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_59 = _nsp_T_2 == 4'h2; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_60 = _nsp_T_2 == 4'h3; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_61 = _nsp_T_2 == 4'h4; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_62 = _nsp_T_2 == 4'h5; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_63 = _nsp_T_2 == 4'h6; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_64 = _nsp_T_2 == 4'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_65 = _nsp_T_2 == 4'h8; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_66 = _nsp_T_2 == 4'h9; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_67 = _nsp_T_2 == 4'hA; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_68 = _nsp_T_2 == 4'hB; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_69 = _nsp_T_2 == 4'hC; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_70 = _nsp_T_2 == 4'hD; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire _GEN_71 = _nsp_T_2 == 4'hE; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 - wire [5:0] _GEN_72 = {io_commit_meta_TOSW_flag, io_commit_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _new_ptr_WIRE_5 = 6'(_GEN_72 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_24 < 8'h7 & _GEN_3[nsp] == _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :187:15, :189:15, :246:85, :477:27, :499:{27,36,57}] + wire [3:0] _nsp_T_2 = 4'(io_commit_meta_ssp + 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38] + wire _GEN_57 = _nsp_T_2 == 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33, :504:50] + wire _GEN_58 = _nsp_T_2 == 4'h1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_59 = _nsp_T_2 == 4'h2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_60 = _nsp_T_2 == 4'h3; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_61 = _nsp_T_2 == 4'h4; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_62 = _nsp_T_2 == 4'h5; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_63 = _nsp_T_2 == 4'h6; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_64 = _nsp_T_2 == 4'h7; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_65 = _nsp_T_2 == 4'h8; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_66 = _nsp_T_2 == 4'h9; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_67 = _nsp_T_2 == 4'hA; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_68 = _nsp_T_2 == 4'hB; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_69 = _nsp_T_2 == 4'hC; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_70 = _nsp_T_2 == 4'hD; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire _GEN_71 = _nsp_T_2 == 4'hE; // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50] + wire [5:0] _GEN_72 = {io_commit_meta_TOSW_flag, io_commit_meta_TOSW_value}; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _new_ptr_T_11 = 6'(_GEN_72 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire _GEN_73 = io_commit_push_valid - & (~spec_overflowed | _new_ptr_WIRE_5[5] ^ BOS_flag - ^ _new_ptr_WIRE_5[4:0] > BOS_value); // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :447:25, :490:33, :508:{13,30,80}, :509:13, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :67:30, :68:19 - wire [5:0] _GEN_74 = {io_redirect_meta_TOSW_flag, io_redirect_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + & (~spec_overflowed | _new_ptr_T_11[5] ^ BOS_flag ^ _new_ptr_T_11[4:0] > BOS_value); // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :447:25, :490:33, :508:{13,30,80}, :509:13, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :67:30, :68:19] + wire [5:0] _GEN_74 = {io_redirect_meta_TOSW_flag, io_redirect_meta_TOSW_value}; // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire _GEN_75 = - io_redirect_valid & io_redirect_isCall & 6'(_GEN_74 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :490:33, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} - wire [7:0] _commit_stack_ctr_T_2 = 8'(_GEN_24 + 8'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55, :500:55 - wire [5:0] _GEN_76 = 6'(_GEN_74 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + io_redirect_valid & io_redirect_isCall & 6'(_GEN_74 + 6'h1) == {BOS_flag, BOS_value}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :490:33, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56}] + wire [7:0] _commit_stack_ctr_T_2 = 8'(_GEN_24 + 8'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55, :500:55] + wire [5:0] _GEN_76 = 6'(_GEN_74 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire inflightValid_8 = _GEN_14 & (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag - ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19] wire _GEN_77 = - io_s3_missed_pop & (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :449:12, :455:31, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + io_s3_missed_pop & (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :449:12, :455:31, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19] wire inflightValid_6 = _GEN_18 & (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag - ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 - wire [5:0] _GEN_78 = 6'(_GEN_22 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire _GEN_79 = _s3_missPushEntry_ctr_T & io_s3_meta_sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:246:85, :367:52, :397:{42,57} + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value); // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19] + wire [5:0] _GEN_78 = 6'(_GEN_22 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire _GEN_79 = _s3_missPushEntry_ctr_T & io_s3_meta_sctr != 3'h7; // @[src/main/scala/xiangshan/frontend/newRAS.scala:246:85, :367:52, :397:{42,57}] wire inflightValid_4 = - _GEN_16 & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :157:{13,41}, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 - wire [5:0] _GEN_80 = 6'(_GEN_19 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _BOS_new_ptr_WIRE_7 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _BOS_new_ptr_WIRE_5 = 6'(_GEN_72 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _BOS_new_ptr_WIRE_3 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [5:0] _BOS_new_ptr_WIRE_1 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - always @(posedge clock or posedge reset) begin - if (reset) begin - commit_stack_0_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_1_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_2_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_3_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_4_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_5_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_6_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_7_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_8_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_9_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_10_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_11_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_12_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_13_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_14_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_15_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - spec_queue_0_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_1_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_2_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_3_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_4_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_5_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_6_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_7_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_8_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_9_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_10_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_11_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_12_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_13_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_14_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_15_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_16_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_16_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_17_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_17_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_18_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_18_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_19_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_19_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_20_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_20_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_21_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_21_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_22_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_22_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_23_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_23_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_24_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_24_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_25_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_25_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_26_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_26_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_27_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_27_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_28_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_28_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_29_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_29_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_30_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_30_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_31_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_31_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_nos_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_0_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_1_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_2_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_3_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_4_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_4_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_5_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_5_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_6_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_6_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_7_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_7_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_8_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_8_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_9_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_9_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_10_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_10_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_11_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_11_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_12_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_12_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_13_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_13_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_14_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_14_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_15_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_15_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_16_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_16_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_17_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_17_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_18_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_18_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_19_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_19_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_20_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_20_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_21_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_21_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_22_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_22_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_23_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_23_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_24_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_24_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_25_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_25_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_26_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_26_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_27_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_27_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_28_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_28_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_29_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_29_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_30_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_30_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_31_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_31_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - nsp <= 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 - ssp <= 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22 - sctr <= 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 - TOSR_flag <= 1'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23 - TOSR_value <= 5'h1F; // src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23 - TOSW_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23 - TOSW_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41 - BOS_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22 - BOS_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41 - spec_overflowed <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34 - writeBypassValid <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35 - timingTop_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41} + _GEN_16 & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value); // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :157:{13,41}, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19] + wire [5:0] _GEN_80 = 6'(_GEN_19 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _BOS_new_ptr_T_16 = 6'(_GEN_20 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _BOS_new_ptr_T_11 = 6'(_GEN_72 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _BOS_new_ptr_T_6 = 6'(_GEN_20 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [5:0] _BOS_new_ptr_T_1 = 6'(_GEN_20 + 6'h1); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + if (reset) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + commit_stack_0_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_0_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_1_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_1_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_2_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_2_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_3_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_3_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_4_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_4_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_5_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_5_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_6_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_6_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_7_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_7_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_8_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_8_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_9_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_9_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_10_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_10_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_11_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_11_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_12_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_12_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_13_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_13_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_14_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_14_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_15_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_15_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + spec_queue_0_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_0_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_1_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_1_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_2_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_2_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_3_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_3_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_4_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_4_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_5_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_5_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_6_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_6_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_7_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_7_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_8_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_8_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_9_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_9_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_10_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_10_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_11_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_11_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_12_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_12_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_13_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_13_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_14_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_14_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_15_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_15_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_16_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_16_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_17_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_17_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_18_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_18_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_19_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_19_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_20_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_20_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_21_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_21_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_22_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_22_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_23_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_23_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_24_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_24_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_25_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_25_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_26_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_26_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_27_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_27_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_28_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_28_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_29_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_29_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_30_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_30_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_31_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_31_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_nos_0_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_0_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_1_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_1_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_2_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_2_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_3_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_3_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_4_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_4_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_5_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_5_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_6_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_6_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_7_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_7_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_8_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_8_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_9_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_9_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_10_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_10_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_11_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_11_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_12_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_12_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_13_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_13_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_14_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_14_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_15_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_15_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_16_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_16_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_17_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_17_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_18_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_18_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_19_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_19_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_20_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_20_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_21_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_21_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_22_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_22_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_23_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_23_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_24_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_24_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_25_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_25_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_26_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_26_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_27_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_27_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_28_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_28_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_29_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_29_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_30_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_30_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_31_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_31_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + nsp <= 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22] + ssp <= 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22] + sctr <= 3'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23] + TOSR_flag <= 1'h1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23] + TOSR_value <= 5'h1F; // @[src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23] + TOSW_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23] + TOSW_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41] + BOS_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22] + BOS_value <= 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41] + spec_overflowed <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34] + writeBypassValid <= 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35] + timingTop_retAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41}] end - else begin - if (~io_commit_push_valid | _GEN_56 | ~_GEN_57) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_57) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_0_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (io_commit_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (_GEN_56) begin // src/main/scala/xiangshan/frontend/newRAS.scala:499:36 - if (_GEN_25) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_0_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_27) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_1_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_29) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_2_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_31) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_3_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_33) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_4_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_35) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_5_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_37) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_6_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_39) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_7_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_41) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_8_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_43) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_9_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_45) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_10_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_47) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_11_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_49) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_12_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_51) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_13_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_53) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_14_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (&io_commit_meta_ssp) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 - commit_stack_15_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 - else if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - nsp <= io_commit_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_0_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (io_commit_push_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (_GEN_56) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:499:36] + if (_GEN_25) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_0_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_26) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_0_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_27) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_1_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_28) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_1_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_29) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_2_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_30) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_2_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_31) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_3_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_32) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_3_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_33) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_4_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_34) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_4_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_35) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_5_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_36) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_5_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_37) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_6_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_38) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_6_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_39) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_7_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_40) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_7_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_41) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_8_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_42) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_8_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_43) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_9_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_44) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_9_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_45) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_10_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_46) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_10_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_47) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_11_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_48) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_11_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_49) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_12_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_50) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_12_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_51) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_13_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_52) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_13_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_53) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_14_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_54) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_14_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (&io_commit_meta_ssp) // @[src/main/scala/xiangshan/frontend/newRAS.scala:478:38] + commit_stack_15_ctr <= _commit_stack_ctr_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55] + else if (_GEN_55) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_15_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + nsp <= io_commit_meta_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22] end - else begin // src/main/scala/xiangshan/frontend/newRAS.scala:499:36 - if (_GEN_57) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_58) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_59) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_60) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_61) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_62) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_63) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_64) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_65) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_66) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_67) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_68) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_69) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_70) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_71) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 - commit_stack_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (&_nsp_T_2) // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :504:50 - commit_stack_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - else if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - nsp <= _nsp_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33 + else begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:499:36] + if (_GEN_57) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_0_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_26) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_0_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_58) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_1_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_28) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_1_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_59) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_2_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_30) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_2_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_60) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_3_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_32) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_3_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_61) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_4_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_34) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_4_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_62) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_5_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_36) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_5_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_63) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_6_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_38) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_6_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_64) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_7_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_40) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_7_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_65) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_8_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_42) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_8_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_66) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_9_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_44) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_9_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_67) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_10_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_46) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_10_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_68) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_11_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_48) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_11_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_69) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_12_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_50) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_12_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_70) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_13_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_52) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_13_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_71) // @[src/main/scala/xiangshan/frontend/newRAS.scala:504:50] + commit_stack_14_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_54) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_14_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (&_nsp_T_2) // @[src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :504:50] + commit_stack_15_ctr <= 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + else if (_GEN_55) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_15_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + nsp <= _nsp_T_2; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33] end end - else begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 - commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 - if (io_commit_pop_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (|_GEN_24) // src/main/scala/xiangshan/frontend/newRAS.scala:477:27 - nsp <= io_commit_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 - else // src/main/scala/xiangshan/frontend/newRAS.scala:477:27 - nsp <= 4'(io_commit_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :206:33 + else begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (_GEN_26) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_0_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_28) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_1_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_30) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_2_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_32) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_3_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_34) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_4_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_36) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_5_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_38) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_6_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_40) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_7_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_42) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_8_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_44) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_9_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_46) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_10_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_48) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_11_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_50) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_12_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_52) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_13_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_54) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_14_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (_GEN_55) // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38] + commit_stack_15_ctr <= _commit_stack_ctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55] + if (io_commit_pop_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (|_GEN_24) // @[src/main/scala/xiangshan/frontend/newRAS.scala:477:27] + nsp <= io_commit_meta_ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:477:27] + nsp <= 4'(io_commit_meta_ssp - 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :206:33] end end - if (~io_commit_push_valid | _GEN_56 | ~_GEN_58) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_58) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_1_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_59) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_1_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_59) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_2_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_60) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_2_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_60) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_3_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_61) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_3_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_61) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_4_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_62) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_4_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_62) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_5_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_63) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_5_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_63) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_6_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_64) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_6_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_64) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_7_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_65) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_7_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_65) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_8_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_66) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_8_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_66) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_9_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_67) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_9_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_67) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_10_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_68) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_10_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_68) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_11_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_69) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_11_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_69) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_12_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_70) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_12_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_70) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_13_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~_GEN_71) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_13_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~_GEN_71) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_14_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (~io_commit_push_valid | _GEN_56 | ~(&_nsp_T_2)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :205:33, :490:33, :499:{36,79}, :504:50 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_14_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (~io_commit_push_valid | _GEN_56 | ~(&_nsp_T_2)) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :205:33, :490:33, :499:{36,79}, :504:50] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 - commit_stack_15_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 - if (realPush & realWriteAddr_value == 5'h0) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :260:41, :378:28, :386:115, :388:21, :389:39 - spec_queue_0_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_0_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_0_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_0_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_0_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79] + commit_stack_15_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57] + if (realPush & realWriteAddr_value == 5'h0) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :260:41, :378:28, :386:115, :388:21, :389:39] + spec_queue_0_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_0_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_0_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_0_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_0_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_1_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_1_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_1_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_1_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_1_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_1_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_1_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_1_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_1_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_1_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h2) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_2_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_2_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_2_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_2_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_2_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h2) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_2_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_2_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_2_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_2_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_2_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h3) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_3_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_3_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_3_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_3_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_3_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h3) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_3_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_3_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_3_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_3_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_3_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_4_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_4_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_4_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_4_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_4_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h4) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_4_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_4_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_4_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_4_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_4_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h5) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_5_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_5_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_5_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_5_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_5_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h5) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_5_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_5_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_5_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_5_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_5_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h6) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_6_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_6_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_6_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_6_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_6_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h6) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_6_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_6_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_6_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_6_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_6_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h7) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_7_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_7_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_7_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_7_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_7_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h7) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_7_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_7_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_7_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_7_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_7_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h8) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_8_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_8_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_8_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_8_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_8_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h8) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_8_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_8_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_8_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_8_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_8_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h9) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_9_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_9_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_9_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_9_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_9_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h9) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_9_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_9_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_9_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_9_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_9_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hA) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_10_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_10_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_10_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_10_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_10_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hA) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_10_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_10_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_10_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_10_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_10_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hB) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_11_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_11_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_11_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_11_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_11_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hB) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_11_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_11_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_11_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_11_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_11_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hC) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_12_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_12_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_12_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_12_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_12_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hC) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_12_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_12_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_12_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_12_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_12_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hD) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_13_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_13_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_13_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_13_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_13_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hD) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_13_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_13_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_13_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_13_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_13_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hE) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_14_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_14_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_14_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_14_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_14_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hE) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_14_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_14_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_14_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_14_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_14_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'hF) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_15_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_15_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_15_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_15_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_15_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'hF) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_15_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_15_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_15_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_15_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_15_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h10) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_16_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_16_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_16_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_16_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_16_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h10) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_16_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_16_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_16_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_16_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_16_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h11) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_17_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_17_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_17_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_17_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_17_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h11) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_17_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_17_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_17_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_17_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_17_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h12) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_18_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_18_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_18_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_18_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_18_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h12) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_18_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_18_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_18_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_18_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_18_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h13) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_19_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_19_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_19_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_19_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_19_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h13) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_19_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_19_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_19_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_19_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_19_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h14) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_20_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_20_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_20_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_20_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_20_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h14) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_20_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_20_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_20_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_20_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_20_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h15) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_21_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_21_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_21_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_21_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_21_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h15) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_21_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_21_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_21_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_21_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_21_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h16) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_22_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_22_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_22_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_22_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_22_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h16) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_22_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_22_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_22_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_22_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_22_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h17) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_23_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_23_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_23_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_23_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_23_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h17) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_23_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_23_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_23_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_23_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_23_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h18) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_24_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_24_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_24_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_24_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_24_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h18) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_24_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_24_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_24_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_24_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_24_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h19) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_25_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_25_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_25_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_25_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_25_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h19) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_25_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_25_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_25_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_25_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_25_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1A) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_26_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_26_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_26_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_26_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_26_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1A) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_26_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_26_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_26_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_26_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_26_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1B) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_27_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_27_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_27_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_27_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_27_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1B) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_27_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_27_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_27_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_27_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_27_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1C) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_28_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_28_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_28_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_28_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_28_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1C) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_28_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_28_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_28_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_28_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_28_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1D) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_29_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_29_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_29_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_29_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_29_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1D) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_29_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_29_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_29_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_29_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_29_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & realWriteAddr_value == 5'h1E) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_30_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_30_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_30_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_30_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_30_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & realWriteAddr_value == 5'h1E) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_30_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_30_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_30_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_30_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_30_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (realPush & (&realWriteAddr_value)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 - spec_queue_31_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 - if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_31_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 - else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 - spec_queue_31_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 - spec_nos_31_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 - spec_nos_31_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + if (realPush & (&realWriteAddr_value)) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39] + spec_queue_31_retAddr <= realWriteEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26] + if (_GEN_9) // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_31_ctr <= realWriteEntry_next_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:373:26] + spec_queue_31_ctr <= s3_missPushEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26] + spec_nos_31_flag <= realNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] + spec_nos_31_value <= realNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22] end - if (io_redirect_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (io_redirect_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] ssp <= ~io_redirect_isRet | (|io_redirect_meta_sctr) ? (~io_redirect_isCall | _GEN_10 ? io_redirect_meta_ssp : 4'(io_redirect_meta_ssp + 4'h1)) - : inflightValid_8 ? 4'(io_redirect_meta_ssp - 4'h1) : _sctr_T_16; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :278:35, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :478:38, :520:11, :523:33, :526:32 + : inflightValid_8 ? 4'(io_redirect_meta_ssp - 4'h1) : _sctr_T_16; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :278:35, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :478:38, :520:11, :523:33, :526:32] sctr <= io_redirect_isRet ? ((|io_redirect_meta_sctr) @@ -1332,29 +1331,29 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 : inflightValid_8 ? _GEN_2[io_redirect_meta_NOS_value][2:0] : _GEN_5[_sctr_T_16][2:0]) - : io_redirect_isCall ? (_GEN_10 ? _sctr_T_12 : 3'h0) : io_redirect_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :246:117, :278:35, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :521:12, :523:33, :526:32 + : io_redirect_isCall ? (_GEN_10 ? _sctr_T_12 : 3'h0) : io_redirect_meta_sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :246:117, :278:35, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :521:12, :523:33, :526:32] TOSR_flag <= _GEN_11 ? io_redirect_meta_NOS_flag : io_redirect_isCall ? io_redirect_meta_TOSW_flag - : io_redirect_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32 + : io_redirect_meta_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32] TOSR_value <= _GEN_11 ? io_redirect_meta_NOS_value : io_redirect_isCall ? io_redirect_meta_TOSW_value - : io_redirect_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32 - TOSW_flag <= io_redirect_isCall ? _GEN_76[5] : io_redirect_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - TOSW_value <= io_redirect_isCall ? _GEN_76[4:0] : io_redirect_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + : io_redirect_meta_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32] + TOSW_flag <= io_redirect_isCall ? _GEN_76[5] : io_redirect_meta_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + TOSW_value <= io_redirect_isCall ? _GEN_76[4:0] : io_redirect_meta_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end - else if (io_s3_cancel) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + else if (io_s3_cancel) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] ssp <= ~io_s3_missed_push | _GEN_79 ? (~io_s3_missed_pop | (|io_s3_meta_sctr) ? io_s3_meta_ssp : inflightValid_6 ? 4'(io_s3_meta_ssp - 4'h1) : _sctr_T_8) - : 4'(io_s3_meta_ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :335:31, :373:26, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :451:11, :455:31, :458:32, :478:38 + : 4'(io_s3_meta_ssp + 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :335:31, :373:26, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :451:11, :455:31, :458:32, :478:38] sctr <= io_s3_missed_push ? (_GEN_79 ? _sctr_T_10 : 3'h0) @@ -1364,80 +1363,80 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 : inflightValid_6 ? _GEN_2[io_s3_meta_NOS_value][2:0] : _GEN_5[_sctr_T_8][2:0]) - : io_s3_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :335:31, :367:115, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :452:12, :455:31, :458:32 + : io_s3_meta_sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :335:31, :367:115, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :452:12, :455:31, :458:32] TOSR_flag <= io_s3_missed_push ? io_s3_meta_TOSW_flag - : _GEN_77 ? io_s3_meta_NOS_flag : io_s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32 + : _GEN_77 ? io_s3_meta_NOS_flag : io_s3_meta_TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32] TOSR_value <= io_s3_missed_push ? io_s3_meta_TOSW_value - : _GEN_77 ? io_s3_meta_NOS_value : io_s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32 - TOSW_flag <= io_s3_missed_push ? _GEN_78[5] : io_s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - TOSW_value <= io_s3_missed_push ? _GEN_78[4:0] : io_s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + : _GEN_77 ? io_s3_meta_NOS_value : io_s3_meta_TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32] + TOSW_flag <= io_s3_missed_push ? _GEN_78[5] : io_s3_meta_TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + TOSW_value <= io_s3_missed_push ? _GEN_78[4:0] : io_s3_meta_TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end - else begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (~io_spec_pop_valid | (|sctr)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18, :410:31, :419:32, :432:30 - if (~io_spec_push_valid | _GEN_12) begin // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:{42,67}, :410:31 + else begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (~io_spec_pop_valid | (|sctr)) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18, :410:31, :419:32, :432:30] + if (~io_spec_push_valid | _GEN_12) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:{42,67}, :410:31] end - else // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:67, :410:31 - ssp <= 4'(ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :205:33, :478:38 + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:67, :410:31] + ssp <= 4'(ssp + 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :205:33, :478:38] end - else if (inflightValid_4) // src/main/scala/xiangshan/frontend/newRAS.scala:157:41 - ssp <= 4'(ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 - else // src/main/scala/xiangshan/frontend/newRAS.scala:157:41 - ssp <= _sctr_T_4; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 - if (io_spec_pop_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (|sctr) // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18 - sctr <= 3'(sctr - 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :420:29 - else // src/main/scala/xiangshan/frontend/newRAS.scala:306:18 - sctr <= inflightValid_4 ? _GEN_2[topNos_value][2:0] : _GEN_5[_sctr_T_4][2:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :170:33, :171:15, :173:15, :187:15, :189:15, :206:33, :421:61, :424:14, :428:14 + else if (inflightValid_4) // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:41] + ssp <= 4'(ssp - 4'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:157:41] + ssp <= _sctr_T_4; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33] + if (io_spec_pop_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (|sctr) // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18] + sctr <= 3'(sctr - 3'h1); // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :420:29] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:306:18] + sctr <= inflightValid_4 ? _GEN_2[topNos_value][2:0] : _GEN_5[_sctr_T_4][2:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :170:33, :171:15, :173:15, :187:15, :189:15, :206:33, :421:61, :424:14, :428:14] end - else if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - if (_GEN_12) // src/main/scala/xiangshan/frontend/newRAS.scala:397:42 - sctr <= _sctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81 - else // src/main/scala/xiangshan/frontend/newRAS.scala:397:42 - sctr <= 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 + else if (io_spec_push_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + if (_GEN_12) // @[src/main/scala/xiangshan/frontend/newRAS.scala:397:42] + sctr <= _sctr_T; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:397:42] + sctr <= 3'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23] end if (io_spec_pop_valid & (TOSR_flag ^ BOS_flag ^ _GEN) - & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:13, :410:31, :415:52, :416:14, :432:30, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 - TOSR_flag <= topNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :170:33, :171:15, :173:15 - if (writeBypassValid) // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 - TOSR_value <= writeBypassNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29 - else // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 - TOSR_value <= _GEN_8; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15 + & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value)) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:13, :410:31, :415:52, :416:14, :432:30, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19] + TOSR_flag <= topNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :170:33, :171:15, :173:15] + if (writeBypassValid) // @[src/main/scala/xiangshan/frontend/newRAS.scala:151:35] + TOSR_value <= writeBypassNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29] + else // @[src/main/scala/xiangshan/frontend/newRAS.scala:151:35] + TOSR_value <= _GEN_8; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15] end - else if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - TOSR_flag <= TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23 - TOSR_value <= TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23 + else if (io_spec_push_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + TOSR_flag <= TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23] + TOSR_value <= TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23] end - if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - TOSW_flag <= _GEN_80[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - TOSW_value <= _GEN_80[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + if (io_spec_push_valid) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + TOSW_flag <= _GEN_80[5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + TOSW_value <= _GEN_80[4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end end - if (_GEN_75) begin // src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :490:33, :517:30, :523:33 - BOS_flag <= _BOS_new_ptr_WIRE_7[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - BOS_value <= _BOS_new_ptr_WIRE_7[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + if (_GEN_75) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :490:33, :517:30, :523:33] + BOS_flag <= _BOS_new_ptr_T_16[5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + BOS_value <= _BOS_new_ptr_T_16[4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end - else if (_GEN_73) begin // src/main/scala/xiangshan/frontend/newRAS.scala:447:25, :490:33, :508:80, :509:13 - BOS_flag <= _BOS_new_ptr_WIRE_5[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - BOS_value <= _BOS_new_ptr_WIRE_5[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + else if (_GEN_73) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:447:25, :490:33, :508:80, :509:13] + BOS_flag <= _BOS_new_ptr_T_11[5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + BOS_value <= _BOS_new_ptr_T_11[4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end - else if (io_s3_cancel & io_s3_missed_push & _GEN_23) begin // src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :410:31, :447:25, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47 - BOS_flag <= _BOS_new_ptr_WIRE_3[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - BOS_value <= _BOS_new_ptr_WIRE_3[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + else if (io_s3_cancel & io_s3_missed_push & _GEN_23) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :410:31, :447:25, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47] + BOS_flag <= _BOS_new_ptr_T_6[5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + BOS_value <= _BOS_new_ptr_T_6[4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end - else if (_GEN_21) begin // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31 - BOS_flag <= _BOS_new_ptr_WIRE_1[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - BOS_value <= _BOS_new_ptr_WIRE_1[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + else if (_GEN_21) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31] + BOS_flag <= _BOS_new_ptr_T_1[5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + BOS_value <= _BOS_new_ptr_T_1[4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] end spec_overflowed <= _GEN_75 | ~_GEN_73 & (io_s3_cancel & io_s3_missed_push ? _GEN_23 | _GEN_21 | spec_overflowed - : _GEN_21 | spec_overflowed); // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :404:46, :405:13, :406:25, :410:31, :447:25, :458:32, :490:33, :508:80, :509:13, :510:25, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47 - writeBypassValid <= writeBypassValidWire; // src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:52, :218:24, :219:37 + : _GEN_21 | spec_overflowed); // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :404:46, :405:13, :406:25, :410:31, :447:25, :458:32, :490:33, :508:80, :509:13, :510:25, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47] + writeBypassValid <= writeBypassValidWire; // @[src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:52, :218:24, :219:37] timingTop_retAddr <= writeBypassValidWire ? (_realPush_T_4 | io_spec_push_valid @@ -1495,7 +1494,7 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 : (TOSR_flag ^ BOS_flag ^ _GEN) & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value) ? _GEN_1 - : _GEN_4; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :143:23, :144:22, :148:31, :157:{13,41}, :170:33, :171:15, :173:15, :187:15, :189:15, :192:54, :193:15, :195:15, :206:33, :216:{29,52}, :218:24, :219:37, :244:30, :259:28, :262:33, :263:{55,78}, :264:19, :267:19, :271:{36,58}, :278:{35,42}, :280:19, :281:51, :282:19, :285:19, :289:17, :290:37, :297:17, :299:37, :306:{18,25}, :308:16, :309:48, :310:16, :313:16, :317:17, :318:28, :320:17, :321:32, :323:17, :324:32, :326:19, :329:38, :335:{31,38}, :337:24, :338:65, :339:24, :342:24, :346:19, :354:17, :373:26, :386:115, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + : _GEN_4; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :143:23, :144:22, :148:31, :157:{13,41}, :170:33, :171:15, :173:15, :187:15, :189:15, :192:54, :193:15, :195:15, :206:33, :216:{29,52}, :218:24, :219:37, :244:30, :259:28, :262:33, :263:{55,78}, :264:19, :267:19, :271:{36,58}, :278:{35,42}, :280:19, :281:51, :282:19, :285:19, :289:17, :290:37, :297:17, :299:37, :306:{18,25}, :308:16, :309:48, :310:16, :313:16, :317:17, :318:28, :320:17, :321:32, :323:17, :324:32, :326:19, :329:38, :335:{31,38}, :337:24, :338:65, :339:24, :342:24, :346:19, :354:17, :373:26, :386:115, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19] end end // always @(posedge, posedge) wire [7:0] writeEntry_ctr = @@ -1512,420 +1511,424 @@ module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 ? writeBypassEntry_ctr : topEntry_inflightValid ? _GEN_2[TOSR_value] : _GEN_5[ssp]) < 8'h7 ? _sctr_T - : 3'h0}; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :192:54, :193:15, :195:15, :216:29, :245:{20,26}, :246:{10,36,61,85,117}, :247:{10,28,50,66,81}, :260:41 - always @(posedge clock) begin - if (io_spec_push_valid | _realPush_T_4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :252:30 - writeBypassEntry_retAddr <= writeEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :244:30 - writeBypassEntry_ctr <= writeEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :245:20 - writeBypassNos_flag <= _realPush_T_4 ? io_redirect_meta_NOS_flag : TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20 - writeBypassNos_value <= _realPush_T_4 ? io_redirect_meta_NOS_value : TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20 + : 3'h0}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :192:54, :193:15, :195:15, :216:29, :245:{20,26}, :246:{10,36,61,85,117}, :247:{10,28,50,66,81}, :260:41] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + if (io_spec_push_valid | _realPush_T_4) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :252:30] + writeBypassEntry_retAddr <= writeEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :244:30] + writeBypassEntry_ctr <= writeEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :245:20] + writeBypassNos_flag <= _realPush_T_4 ? io_redirect_meta_NOS_flag : TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20] + writeBypassNos_value <= _realPush_T_4 ? io_redirect_meta_NOS_value : TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20] end - if (io_s2_fire | io_redirect_isCall) begin // src/main/scala/xiangshan/frontend/newRAS.scala:361:64 - realWriteEntry_next_retAddr <= writeEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:244:30, :361:40 - realWriteEntry_next_ctr <= writeEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:245:20, :361:40 + if (io_s2_fire | io_redirect_isCall) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:361:64] + realWriteEntry_next_retAddr <= writeEntry_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:244:30, :361:40] + realWriteEntry_next_ctr <= writeEntry_ctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:245:20, :361:40] end - if (io_s2_fire | _realPush_T_4) // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :377:126 + if (io_s2_fire | _realPush_T_4) // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :377:126] realWriteAddr_next_value <= - _realPush_T_4 ? io_redirect_meta_TOSW_value : TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :216:29, :377:{39,43} - if (io_s2_fire | _realPush_T_4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :381:120 - realNos_next_flag <= _realPush_T_4 ? io_redirect_meta_TOSR_flag : TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37} - realNos_next_value <= _realPush_T_4 ? io_redirect_meta_TOSR_value : TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37} + _realPush_T_4 ? io_redirect_meta_TOSW_value : TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :216:29, :377:{39,43}] + if (io_s2_fire | _realPush_T_4) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :381:120] + realNos_next_flag <= _realPush_T_4 ? io_redirect_meta_TOSR_flag : TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37}] + realNos_next_value <= _realPush_T_4 ? io_redirect_meta_TOSR_value : TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37}] end - if (io_s2_fire) // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 - realPush_r <= io_spec_push_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:386:59 - realPush_REG <= _realPush_T_4; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :386:125 + if (io_s2_fire) // @[src/main/scala/xiangshan/frontend/newRAS.scala:89:16] + realPush_r <= io_spec_push_valid; // @[src/main/scala/xiangshan/frontend/newRAS.scala:386:59] + realPush_REG <= _realPush_T_4; // @[src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :386:125] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:82]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - initial begin // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + logic [31:0] _RANDOM[0:85]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + initial begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - for (logic [6:0] i = 7'h0; i < 7'h53; i += 7'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - end // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - commit_stack_0_retAddr = {_RANDOM[7'h0], _RANDOM[7'h1][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_0_ctr = _RANDOM[7'h1][14:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_1_retAddr = {_RANDOM[7'h1][31:15], _RANDOM[7'h2][21:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_1_ctr = _RANDOM[7'h2][29:22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_2_retAddr = - {_RANDOM[7'h2][31:30], _RANDOM[7'h3], _RANDOM[7'h4][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_2_ctr = _RANDOM[7'h4][12:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_3_retAddr = {_RANDOM[7'h4][31:13], _RANDOM[7'h5][19:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_3_ctr = _RANDOM[7'h5][27:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_4_retAddr = - {_RANDOM[7'h5][31:28], _RANDOM[7'h6], _RANDOM[7'h7][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_4_ctr = _RANDOM[7'h7][10:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_5_retAddr = {_RANDOM[7'h7][31:11], _RANDOM[7'h8][17:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_5_ctr = _RANDOM[7'h8][25:18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_6_retAddr = {_RANDOM[7'h8][31:26], _RANDOM[7'h9], _RANDOM[7'hA][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_6_ctr = _RANDOM[7'hA][8:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_7_retAddr = {_RANDOM[7'hA][31:9], _RANDOM[7'hB][15:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_7_ctr = _RANDOM[7'hB][23:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_8_retAddr = {_RANDOM[7'hB][31:24], _RANDOM[7'hC][30:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_8_ctr = {_RANDOM[7'hC][31], _RANDOM[7'hD][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_9_retAddr = {_RANDOM[7'hD][31:7], _RANDOM[7'hE][13:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_9_ctr = _RANDOM[7'hE][21:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_10_retAddr = {_RANDOM[7'hE][31:22], _RANDOM[7'hF][28:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_10_ctr = {_RANDOM[7'hF][31:29], _RANDOM[7'h10][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_11_retAddr = {_RANDOM[7'h10][31:5], _RANDOM[7'h11][11:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_11_ctr = _RANDOM[7'h11][19:12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_12_retAddr = {_RANDOM[7'h11][31:20], _RANDOM[7'h12][26:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_12_ctr = {_RANDOM[7'h12][31:27], _RANDOM[7'h13][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_13_retAddr = {_RANDOM[7'h13][31:3], _RANDOM[7'h14][9:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_13_ctr = _RANDOM[7'h14][17:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_14_retAddr = {_RANDOM[7'h14][31:18], _RANDOM[7'h15][24:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_14_ctr = {_RANDOM[7'h15][31:25], _RANDOM[7'h16][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_15_retAddr = {_RANDOM[7'h16][31:1], _RANDOM[7'h17][7:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - commit_stack_15_ctr = _RANDOM[7'h17][15:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 - spec_queue_0_retAddr = {_RANDOM[7'h17][31:16], _RANDOM[7'h18][22:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31, :135:29 - spec_queue_0_ctr = _RANDOM[7'h18][30:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_1_retAddr = {_RANDOM[7'h18][31], _RANDOM[7'h19], _RANDOM[7'h1A][5:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_1_ctr = _RANDOM[7'h1A][13:6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_2_retAddr = {_RANDOM[7'h1A][31:14], _RANDOM[7'h1B][20:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_2_ctr = _RANDOM[7'h1B][28:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_3_retAddr = - {_RANDOM[7'h1B][31:29], _RANDOM[7'h1C], _RANDOM[7'h1D][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_3_ctr = _RANDOM[7'h1D][11:4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_4_retAddr = {_RANDOM[7'h1D][31:12], _RANDOM[7'h1E][18:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_4_ctr = _RANDOM[7'h1E][26:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_5_retAddr = - {_RANDOM[7'h1E][31:27], _RANDOM[7'h1F], _RANDOM[7'h20][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_5_ctr = _RANDOM[7'h20][9:2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_6_retAddr = {_RANDOM[7'h20][31:10], _RANDOM[7'h21][16:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_6_ctr = _RANDOM[7'h21][24:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_7_retAddr = {_RANDOM[7'h21][31:25], _RANDOM[7'h22]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_7_ctr = _RANDOM[7'h23][7:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_8_retAddr = {_RANDOM[7'h23][31:8], _RANDOM[7'h24][14:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_8_ctr = _RANDOM[7'h24][22:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_9_retAddr = {_RANDOM[7'h24][31:23], _RANDOM[7'h25][29:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_9_ctr = {_RANDOM[7'h25][31:30], _RANDOM[7'h26][5:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_10_retAddr = {_RANDOM[7'h26][31:6], _RANDOM[7'h27][12:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_10_ctr = _RANDOM[7'h27][20:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_11_retAddr = {_RANDOM[7'h27][31:21], _RANDOM[7'h28][27:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_11_ctr = {_RANDOM[7'h28][31:28], _RANDOM[7'h29][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_12_retAddr = {_RANDOM[7'h29][31:4], _RANDOM[7'h2A][10:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_12_ctr = _RANDOM[7'h2A][18:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_13_retAddr = {_RANDOM[7'h2A][31:19], _RANDOM[7'h2B][25:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_13_ctr = {_RANDOM[7'h2B][31:26], _RANDOM[7'h2C][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_14_retAddr = {_RANDOM[7'h2C][31:2], _RANDOM[7'h2D][8:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_14_ctr = _RANDOM[7'h2D][16:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_15_retAddr = {_RANDOM[7'h2D][31:17], _RANDOM[7'h2E][23:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_15_ctr = _RANDOM[7'h2E][31:24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_16_retAddr = {_RANDOM[7'h2F], _RANDOM[7'h30][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_16_ctr = _RANDOM[7'h30][14:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_17_retAddr = {_RANDOM[7'h30][31:15], _RANDOM[7'h31][21:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_17_ctr = _RANDOM[7'h31][29:22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_18_retAddr = - {_RANDOM[7'h31][31:30], _RANDOM[7'h32], _RANDOM[7'h33][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_18_ctr = _RANDOM[7'h33][12:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_19_retAddr = {_RANDOM[7'h33][31:13], _RANDOM[7'h34][19:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_19_ctr = _RANDOM[7'h34][27:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_20_retAddr = - {_RANDOM[7'h34][31:28], _RANDOM[7'h35], _RANDOM[7'h36][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_20_ctr = _RANDOM[7'h36][10:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_21_retAddr = {_RANDOM[7'h36][31:11], _RANDOM[7'h37][17:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_21_ctr = _RANDOM[7'h37][25:18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_22_retAddr = - {_RANDOM[7'h37][31:26], _RANDOM[7'h38], _RANDOM[7'h39][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_22_ctr = _RANDOM[7'h39][8:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_23_retAddr = {_RANDOM[7'h39][31:9], _RANDOM[7'h3A][15:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_23_ctr = _RANDOM[7'h3A][23:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_24_retAddr = {_RANDOM[7'h3A][31:24], _RANDOM[7'h3B][30:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_24_ctr = {_RANDOM[7'h3B][31], _RANDOM[7'h3C][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_25_retAddr = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][13:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_25_ctr = _RANDOM[7'h3D][21:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_26_retAddr = {_RANDOM[7'h3D][31:22], _RANDOM[7'h3E][28:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_26_ctr = {_RANDOM[7'h3E][31:29], _RANDOM[7'h3F][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_27_retAddr = {_RANDOM[7'h3F][31:5], _RANDOM[7'h40][11:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_27_ctr = _RANDOM[7'h40][19:12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_28_retAddr = {_RANDOM[7'h40][31:20], _RANDOM[7'h41][26:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_28_ctr = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_29_retAddr = {_RANDOM[7'h42][31:3], _RANDOM[7'h43][9:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_29_ctr = _RANDOM[7'h43][17:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_30_retAddr = {_RANDOM[7'h43][31:18], _RANDOM[7'h44][24:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_30_ctr = {_RANDOM[7'h44][31:25], _RANDOM[7'h45][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_31_retAddr = {_RANDOM[7'h45][31:1], _RANDOM[7'h46][7:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_queue_31_ctr = _RANDOM[7'h46][15:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 - spec_nos_0_flag = _RANDOM[7'h46][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_0_value = _RANDOM[7'h46][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_1_flag = _RANDOM[7'h46][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_1_value = _RANDOM[7'h46][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_2_flag = _RANDOM[7'h46][28]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_2_value = {_RANDOM[7'h46][31:29], _RANDOM[7'h47][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 - spec_nos_3_flag = _RANDOM[7'h47][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_3_value = _RANDOM[7'h47][7:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_4_flag = _RANDOM[7'h47][8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_4_value = _RANDOM[7'h47][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_5_flag = _RANDOM[7'h47][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_5_value = _RANDOM[7'h47][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_6_flag = _RANDOM[7'h47][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_6_value = _RANDOM[7'h47][25:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_7_flag = _RANDOM[7'h47][26]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_7_value = _RANDOM[7'h47][31:27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_8_flag = _RANDOM[7'h48][0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_8_value = _RANDOM[7'h48][5:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_9_flag = _RANDOM[7'h48][6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_9_value = _RANDOM[7'h48][11:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_10_flag = _RANDOM[7'h48][12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_10_value = _RANDOM[7'h48][17:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_11_flag = _RANDOM[7'h48][18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_11_value = _RANDOM[7'h48][23:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_12_flag = _RANDOM[7'h48][24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_12_value = _RANDOM[7'h48][29:25]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_13_flag = _RANDOM[7'h48][30]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_13_value = {_RANDOM[7'h48][31], _RANDOM[7'h49][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_14_flag = _RANDOM[7'h49][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_14_value = _RANDOM[7'h49][9:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_15_flag = _RANDOM[7'h49][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_15_value = _RANDOM[7'h49][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_16_flag = _RANDOM[7'h49][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_16_value = _RANDOM[7'h49][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_17_flag = _RANDOM[7'h49][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_17_value = _RANDOM[7'h49][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_18_flag = _RANDOM[7'h49][28]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_18_value = {_RANDOM[7'h49][31:29], _RANDOM[7'h4A][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_19_flag = _RANDOM[7'h4A][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_19_value = _RANDOM[7'h4A][7:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_20_flag = _RANDOM[7'h4A][8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_20_value = _RANDOM[7'h4A][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_21_flag = _RANDOM[7'h4A][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_21_value = _RANDOM[7'h4A][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_22_flag = _RANDOM[7'h4A][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_22_value = _RANDOM[7'h4A][25:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_23_flag = _RANDOM[7'h4A][26]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_23_value = _RANDOM[7'h4A][31:27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_24_flag = _RANDOM[7'h4B][0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_24_value = _RANDOM[7'h4B][5:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_25_flag = _RANDOM[7'h4B][6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_25_value = _RANDOM[7'h4B][11:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_26_flag = _RANDOM[7'h4B][12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_26_value = _RANDOM[7'h4B][17:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_27_flag = _RANDOM[7'h4B][18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_27_value = _RANDOM[7'h4B][23:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_28_flag = _RANDOM[7'h4B][24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_28_value = _RANDOM[7'h4B][29:25]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_29_flag = _RANDOM[7'h4B][30]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_29_value = {_RANDOM[7'h4B][31], _RANDOM[7'h4C][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_30_flag = _RANDOM[7'h4C][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_30_value = _RANDOM[7'h4C][9:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_31_flag = _RANDOM[7'h4C][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - spec_nos_31_value = _RANDOM[7'h4C][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 - nsp = _RANDOM[7'h4C][19:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :138:22 - ssp = _RANDOM[7'h4C][23:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :139:22 - sctr = _RANDOM[7'h4C][26:24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :141:23 - TOSR_flag = _RANDOM[7'h4C][27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23 - TOSR_value = {_RANDOM[7'h4C][31:28], _RANDOM[7'h4D][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23 - TOSW_flag = _RANDOM[7'h4D][1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23 - TOSW_value = _RANDOM[7'h4D][6:2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23 - BOS_flag = _RANDOM[7'h4D][7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22 - BOS_value = _RANDOM[7'h4D][12:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22 - spec_overflowed = _RANDOM[7'h4D][13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :146:34 - writeBypassEntry_retAddr = {_RANDOM[7'h4D][31:14], _RANDOM[7'h4E][20:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :148:31 - writeBypassEntry_ctr = _RANDOM[7'h4E][28:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31 - writeBypassNos_flag = _RANDOM[7'h4E][29]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31, :149:29 - writeBypassNos_value = {_RANDOM[7'h4E][31:30], _RANDOM[7'h4F][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31, :149:29 - writeBypassValid = _RANDOM[7'h4F][3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :151:35 - timingTop_retAddr = {_RANDOM[7'h4F][31:4], _RANDOM[7'h50][10:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :259:28 - realWriteEntry_next_retAddr = {_RANDOM[7'h50][31:25], _RANDOM[7'h51]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28, :361:40 - realWriteEntry_next_ctr = _RANDOM[7'h52][7:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40 - realWriteAddr_next_value = _RANDOM[7'h52][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :377:39 - realNos_next_flag = _RANDOM[7'h52][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33 - realNos_next_value = _RANDOM[7'h52][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33 - realPush_r = _RANDOM[7'h52][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:59 - realPush_REG = _RANDOM[7'h52][21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:125 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + for (logic [6:0] i = 7'h0; i < 7'h56; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + end // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + commit_stack_0_retAddr = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_0_ctr = _RANDOM[7'h1][16:9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_1_retAddr = {_RANDOM[7'h1][31:17], _RANDOM[7'h2][25:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_1_ctr = {_RANDOM[7'h2][31:26], _RANDOM[7'h3][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_2_retAddr = {_RANDOM[7'h3][31:2], _RANDOM[7'h4][10:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_2_ctr = _RANDOM[7'h4][18:11]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_3_retAddr = {_RANDOM[7'h4][31:19], _RANDOM[7'h5][27:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_3_ctr = {_RANDOM[7'h5][31:28], _RANDOM[7'h6][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_4_retAddr = {_RANDOM[7'h6][31:4], _RANDOM[7'h7][12:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_4_ctr = _RANDOM[7'h7][20:13]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_5_retAddr = {_RANDOM[7'h7][31:21], _RANDOM[7'h8][29:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_5_ctr = {_RANDOM[7'h8][31:30], _RANDOM[7'h9][5:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_6_retAddr = {_RANDOM[7'h9][31:6], _RANDOM[7'hA][14:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_6_ctr = _RANDOM[7'hA][22:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_7_retAddr = {_RANDOM[7'hA][31:23], _RANDOM[7'hB]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_7_ctr = _RANDOM[7'hC][7:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_8_retAddr = {_RANDOM[7'hC][31:8], _RANDOM[7'hD][16:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_8_ctr = _RANDOM[7'hD][24:17]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_9_retAddr = + {_RANDOM[7'hD][31:25], _RANDOM[7'hE], _RANDOM[7'hF][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_9_ctr = _RANDOM[7'hF][9:2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_10_retAddr = {_RANDOM[7'hF][31:10], _RANDOM[7'h10][18:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_10_ctr = _RANDOM[7'h10][26:19]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_11_retAddr = + {_RANDOM[7'h10][31:27], _RANDOM[7'h11], _RANDOM[7'h12][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_11_ctr = _RANDOM[7'h12][11:4]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_12_retAddr = {_RANDOM[7'h12][31:12], _RANDOM[7'h13][20:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_12_ctr = _RANDOM[7'h13][28:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_13_retAddr = + {_RANDOM[7'h13][31:29], _RANDOM[7'h14], _RANDOM[7'h15][5:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_13_ctr = _RANDOM[7'h15][13:6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_14_retAddr = {_RANDOM[7'h15][31:14], _RANDOM[7'h16][22:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_14_ctr = _RANDOM[7'h16][30:23]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_15_retAddr = + {_RANDOM[7'h16][31], _RANDOM[7'h17], _RANDOM[7'h18][7:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + commit_stack_15_ctr = _RANDOM[7'h18][15:8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31] + spec_queue_0_retAddr = {_RANDOM[7'h18][31:16], _RANDOM[7'h19][24:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31, :135:29] + spec_queue_0_ctr = {_RANDOM[7'h19][31:25], _RANDOM[7'h1A][0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_1_retAddr = {_RANDOM[7'h1A][31:1], _RANDOM[7'h1B][9:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_1_ctr = _RANDOM[7'h1B][17:10]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_2_retAddr = {_RANDOM[7'h1B][31:18], _RANDOM[7'h1C][26:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_2_ctr = {_RANDOM[7'h1C][31:27], _RANDOM[7'h1D][2:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_3_retAddr = {_RANDOM[7'h1D][31:3], _RANDOM[7'h1E][11:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_3_ctr = _RANDOM[7'h1E][19:12]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_4_retAddr = {_RANDOM[7'h1E][31:20], _RANDOM[7'h1F][28:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_4_ctr = {_RANDOM[7'h1F][31:29], _RANDOM[7'h20][4:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_5_retAddr = {_RANDOM[7'h20][31:5], _RANDOM[7'h21][13:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_5_ctr = _RANDOM[7'h21][21:14]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_6_retAddr = {_RANDOM[7'h21][31:22], _RANDOM[7'h22][30:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_6_ctr = {_RANDOM[7'h22][31], _RANDOM[7'h23][6:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_7_retAddr = {_RANDOM[7'h23][31:7], _RANDOM[7'h24][15:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_7_ctr = _RANDOM[7'h24][23:16]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_8_retAddr = {_RANDOM[7'h24][31:24], _RANDOM[7'h25], _RANDOM[7'h26][0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_8_ctr = _RANDOM[7'h26][8:1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_9_retAddr = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][17:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_9_ctr = _RANDOM[7'h27][25:18]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_10_retAddr = + {_RANDOM[7'h27][31:26], _RANDOM[7'h28], _RANDOM[7'h29][2:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_10_ctr = _RANDOM[7'h29][10:3]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_11_retAddr = {_RANDOM[7'h29][31:11], _RANDOM[7'h2A][19:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_11_ctr = _RANDOM[7'h2A][27:20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_12_retAddr = + {_RANDOM[7'h2A][31:28], _RANDOM[7'h2B], _RANDOM[7'h2C][4:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_12_ctr = _RANDOM[7'h2C][12:5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_13_retAddr = {_RANDOM[7'h2C][31:13], _RANDOM[7'h2D][21:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_13_ctr = _RANDOM[7'h2D][29:22]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_14_retAddr = + {_RANDOM[7'h2D][31:30], _RANDOM[7'h2E], _RANDOM[7'h2F][6:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_14_ctr = _RANDOM[7'h2F][14:7]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_15_retAddr = {_RANDOM[7'h2F][31:15], _RANDOM[7'h30][23:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_15_ctr = _RANDOM[7'h30][31:24]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_16_retAddr = {_RANDOM[7'h31], _RANDOM[7'h32][8:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_16_ctr = _RANDOM[7'h32][16:9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_17_retAddr = {_RANDOM[7'h32][31:17], _RANDOM[7'h33][25:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_17_ctr = {_RANDOM[7'h33][31:26], _RANDOM[7'h34][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_18_retAddr = {_RANDOM[7'h34][31:2], _RANDOM[7'h35][10:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_18_ctr = _RANDOM[7'h35][18:11]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_19_retAddr = {_RANDOM[7'h35][31:19], _RANDOM[7'h36][27:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_19_ctr = {_RANDOM[7'h36][31:28], _RANDOM[7'h37][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_20_retAddr = {_RANDOM[7'h37][31:4], _RANDOM[7'h38][12:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_20_ctr = _RANDOM[7'h38][20:13]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_21_retAddr = {_RANDOM[7'h38][31:21], _RANDOM[7'h39][29:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_21_ctr = {_RANDOM[7'h39][31:30], _RANDOM[7'h3A][5:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_22_retAddr = {_RANDOM[7'h3A][31:6], _RANDOM[7'h3B][14:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_22_ctr = _RANDOM[7'h3B][22:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_23_retAddr = {_RANDOM[7'h3B][31:23], _RANDOM[7'h3C]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_23_ctr = _RANDOM[7'h3D][7:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_24_retAddr = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][16:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_24_ctr = _RANDOM[7'h3E][24:17]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_25_retAddr = + {_RANDOM[7'h3E][31:25], _RANDOM[7'h3F], _RANDOM[7'h40][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_25_ctr = _RANDOM[7'h40][9:2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_26_retAddr = {_RANDOM[7'h40][31:10], _RANDOM[7'h41][18:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_26_ctr = _RANDOM[7'h41][26:19]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_27_retAddr = + {_RANDOM[7'h41][31:27], _RANDOM[7'h42], _RANDOM[7'h43][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_27_ctr = _RANDOM[7'h43][11:4]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_28_retAddr = {_RANDOM[7'h43][31:12], _RANDOM[7'h44][20:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_28_ctr = _RANDOM[7'h44][28:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_29_retAddr = + {_RANDOM[7'h44][31:29], _RANDOM[7'h45], _RANDOM[7'h46][5:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_29_ctr = _RANDOM[7'h46][13:6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_30_retAddr = {_RANDOM[7'h46][31:14], _RANDOM[7'h47][22:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_30_ctr = _RANDOM[7'h47][30:23]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_31_retAddr = {_RANDOM[7'h47][31], _RANDOM[7'h48], _RANDOM[7'h49][7:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_queue_31_ctr = _RANDOM[7'h49][15:8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29] + spec_nos_0_flag = _RANDOM[7'h49][16]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_0_value = _RANDOM[7'h49][21:17]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_1_flag = _RANDOM[7'h49][22]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_1_value = _RANDOM[7'h49][27:23]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_2_flag = _RANDOM[7'h49][28]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_2_value = {_RANDOM[7'h49][31:29], _RANDOM[7'h4A][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27] + spec_nos_3_flag = _RANDOM[7'h4A][2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_3_value = _RANDOM[7'h4A][7:3]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_4_flag = _RANDOM[7'h4A][8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_4_value = _RANDOM[7'h4A][13:9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_5_flag = _RANDOM[7'h4A][14]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_5_value = _RANDOM[7'h4A][19:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_6_flag = _RANDOM[7'h4A][20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_6_value = _RANDOM[7'h4A][25:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_7_flag = _RANDOM[7'h4A][26]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_7_value = _RANDOM[7'h4A][31:27]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_8_flag = _RANDOM[7'h4B][0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_8_value = _RANDOM[7'h4B][5:1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_9_flag = _RANDOM[7'h4B][6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_9_value = _RANDOM[7'h4B][11:7]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_10_flag = _RANDOM[7'h4B][12]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_10_value = _RANDOM[7'h4B][17:13]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_11_flag = _RANDOM[7'h4B][18]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_11_value = _RANDOM[7'h4B][23:19]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_12_flag = _RANDOM[7'h4B][24]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_12_value = _RANDOM[7'h4B][29:25]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_13_flag = _RANDOM[7'h4B][30]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_13_value = {_RANDOM[7'h4B][31], _RANDOM[7'h4C][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_14_flag = _RANDOM[7'h4C][4]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_14_value = _RANDOM[7'h4C][9:5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_15_flag = _RANDOM[7'h4C][10]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_15_value = _RANDOM[7'h4C][15:11]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_16_flag = _RANDOM[7'h4C][16]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_16_value = _RANDOM[7'h4C][21:17]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_17_flag = _RANDOM[7'h4C][22]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_17_value = _RANDOM[7'h4C][27:23]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_18_flag = _RANDOM[7'h4C][28]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_18_value = {_RANDOM[7'h4C][31:29], _RANDOM[7'h4D][1:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_19_flag = _RANDOM[7'h4D][2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_19_value = _RANDOM[7'h4D][7:3]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_20_flag = _RANDOM[7'h4D][8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_20_value = _RANDOM[7'h4D][13:9]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_21_flag = _RANDOM[7'h4D][14]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_21_value = _RANDOM[7'h4D][19:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_22_flag = _RANDOM[7'h4D][20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_22_value = _RANDOM[7'h4D][25:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_23_flag = _RANDOM[7'h4D][26]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_23_value = _RANDOM[7'h4D][31:27]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_24_flag = _RANDOM[7'h4E][0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_24_value = _RANDOM[7'h4E][5:1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_25_flag = _RANDOM[7'h4E][6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_25_value = _RANDOM[7'h4E][11:7]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_26_flag = _RANDOM[7'h4E][12]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_26_value = _RANDOM[7'h4E][17:13]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_27_flag = _RANDOM[7'h4E][18]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_27_value = _RANDOM[7'h4E][23:19]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_28_flag = _RANDOM[7'h4E][24]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_28_value = _RANDOM[7'h4E][29:25]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_29_flag = _RANDOM[7'h4E][30]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_29_value = {_RANDOM[7'h4E][31], _RANDOM[7'h4F][3:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_30_flag = _RANDOM[7'h4F][4]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_30_value = _RANDOM[7'h4F][9:5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_31_flag = _RANDOM[7'h4F][10]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + spec_nos_31_value = _RANDOM[7'h4F][15:11]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27] + nsp = _RANDOM[7'h4F][19:16]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :138:22] + ssp = _RANDOM[7'h4F][23:20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :139:22] + sctr = _RANDOM[7'h4F][26:24]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :141:23] + TOSR_flag = _RANDOM[7'h4F][27]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23] + TOSR_value = {_RANDOM[7'h4F][31:28], _RANDOM[7'h50][0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23] + TOSW_flag = _RANDOM[7'h50][1]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23] + TOSW_value = _RANDOM[7'h50][6:2]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23] + BOS_flag = _RANDOM[7'h50][7]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22] + BOS_value = _RANDOM[7'h50][12:8]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22] + spec_overflowed = _RANDOM[7'h50][13]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :146:34] + writeBypassEntry_retAddr = {_RANDOM[7'h50][31:14], _RANDOM[7'h51][22:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :148:31] + writeBypassEntry_ctr = _RANDOM[7'h51][30:23]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31] + writeBypassNos_flag = _RANDOM[7'h51][31]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31, :149:29] + writeBypassNos_value = _RANDOM[7'h52][4:0]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29] + writeBypassValid = _RANDOM[7'h52][5]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :151:35] + timingTop_retAddr = {_RANDOM[7'h52][31:6], _RANDOM[7'h53][14:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :259:28] + realWriteEntry_next_retAddr = + {_RANDOM[7'h53][31:29], _RANDOM[7'h54], _RANDOM[7'h55][5:0]}; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28, :361:40] + realWriteEntry_next_ctr = _RANDOM[7'h55][13:6]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40] + realWriteAddr_next_value = _RANDOM[7'h55][19:15]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :377:39] + realNos_next_flag = _RANDOM[7'h55][20]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33] + realNos_next_value = _RANDOM[7'h55][25:21]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33] + realPush_r = _RANDOM[7'h55][26]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:59] + realPush_REG = _RANDOM[7'h55][27]; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:125] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - commit_stack_0_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_0_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_1_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_1_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_2_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_2_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_3_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_3_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_4_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_4_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_5_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_5_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_6_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_6_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_7_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_7_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_8_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_8_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_9_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_9_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_10_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_10_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_11_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_11_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_12_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_12_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_13_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_13_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_14_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_14_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_15_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - commit_stack_15_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 - spec_queue_0_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_0_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_1_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_1_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_2_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_2_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_3_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_3_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_4_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_4_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_5_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_5_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_6_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_6_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_7_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_7_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_8_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_8_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_9_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_9_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_10_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_10_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_11_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_11_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_12_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_12_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_13_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_13_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_14_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_14_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_15_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_15_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_16_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_16_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_17_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_17_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_18_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_18_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_19_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_19_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_20_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_20_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_21_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_21_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_22_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_22_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_23_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_23_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_24_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_24_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_25_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_25_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_26_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_26_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_27_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_27_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_28_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_28_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_29_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_29_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_30_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_30_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_31_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_queue_31_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 - spec_nos_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_0_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_1_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_2_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_3_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_4_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_4_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_5_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_5_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_6_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_6_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_7_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_7_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_8_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_8_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_9_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_9_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_10_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_10_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_11_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_11_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_12_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_12_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_13_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_13_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_14_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_14_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_15_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_15_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_16_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_16_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_17_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_17_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_18_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_18_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_19_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_19_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_20_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_20_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_21_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_21_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_22_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_22_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_23_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_23_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_24_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_24_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_25_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_25_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_26_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_26_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_27_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_27_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_28_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_28_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_29_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_29_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_30_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_30_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - spec_nos_31_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 - spec_nos_31_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 - nsp = 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 - ssp = 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22 - sctr = 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 - TOSR_flag = 1'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23 - TOSR_value = 5'h1F; // src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23 - TOSW_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23 - TOSW_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41 - BOS_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22 - BOS_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41 - spec_overflowed = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34 - writeBypassValid = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35 - timingTop_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41} + if (reset) begin // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + commit_stack_0_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_0_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_1_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_1_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_2_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_2_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_3_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_3_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_4_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_4_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_5_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_5_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_6_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_6_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_7_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_7_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_8_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_8_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_9_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_9_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_10_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_10_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_11_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_11_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_12_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_12_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_13_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_13_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_14_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_14_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_15_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + commit_stack_15_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41] + spec_queue_0_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_0_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_1_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_1_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_2_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_2_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_3_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_3_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_4_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_4_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_5_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_5_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_6_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_6_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_7_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_7_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_8_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_8_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_9_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_9_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_10_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_10_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_11_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_11_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_12_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_12_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_13_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_13_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_14_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_14_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_15_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_15_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_16_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_16_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_17_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_17_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_18_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_18_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_19_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_19_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_20_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_20_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_21_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_21_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_22_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_22_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_23_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_23_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_24_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_24_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_25_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_25_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_26_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_26_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_27_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_27_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_28_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_28_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_29_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_29_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_30_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_30_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_31_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_queue_31_ctr = 8'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41] + spec_nos_0_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_0_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_1_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_1_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_2_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_2_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_3_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_3_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_4_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_4_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_5_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_5_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_6_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_6_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_7_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_7_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_8_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_8_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_9_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_9_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_10_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_10_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_11_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_11_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_12_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_12_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_13_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_13_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_14_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_14_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_15_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_15_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_16_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_16_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_17_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_17_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_18_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_18_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_19_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_19_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_20_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_20_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_21_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_21_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_22_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_22_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_23_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_23_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_24_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_24_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_25_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_25_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_26_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_26_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_27_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_27_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_28_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_28_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_29_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_29_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_30_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_30_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + spec_nos_31_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27] + spec_nos_31_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41] + nsp = 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22] + ssp = 4'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22] + sctr = 3'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:141:23] + TOSR_flag = 1'h1; // @[src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23] + TOSR_value = 5'h1F; // @[src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23] + TOSW_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23] + TOSW_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41] + BOS_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22] + BOS_value = 5'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41] + spec_overflowed = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34] + writeBypassValid = 1'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35] + timingTop_retAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41}] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_spec_pop_addr = timingTop_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28 - assign io_ssp = ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :139:22 - assign io_sctr = sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :141:23 - assign io_TOSR_flag = TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23 - assign io_TOSR_value = TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23 - assign io_TOSW_flag = TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23 - assign io_TOSW_value = TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23 - assign io_NOS_flag = topNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15 - assign io_NOS_value = topNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15 + assign io_spec_pop_addr = timingTop_retAddr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28] + assign io_ssp = ssp; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :139:22] + assign io_sctr = sctr; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :141:23] + assign io_TOSR_flag = TOSR_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23] + assign io_TOSR_value = TOSR_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23] + assign io_TOSW_flag = TOSW_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23] + assign io_TOSW_value = TOSW_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23] + assign io_NOS_flag = topNos_flag; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15] + assign io_NOS_value = topNos_value; // @[src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15] endmodule diff --git a/rtl/TageSC/CAMTemplate.sv b/rtl/TageSC/CAMTemplate.sv index 8b2a543..9536411 100644 --- a/rtl/TageSC/CAMTemplate.sv +++ b/rtl/TageSC/CAMTemplate.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,82 +55,82 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module CAMTemplate( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - input clock, - input [8:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [8:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +module CAMTemplate( // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input clock, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input [8:0] io_r_req_0_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_0, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_1, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_2, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_3, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_4, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_5, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_6, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_7, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input io_w_valid, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [8:0] io_w_bits_data_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [2:0] io_w_bits_index // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] ); - reg [8:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [8:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - always @(posedge clock) begin - if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [8:0] array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + always @(posedge clock) begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + if (io_w_valid & io_w_bits_index == 3'h0) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_0 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h1) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_1 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h2) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_2 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h3) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_3 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h4) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_4 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h5) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_5 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h6) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_6 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & (&io_w_bits_index)) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_7 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + logic [31:0] _RANDOM[0:2]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + initial begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - array_0 = _RANDOM[2'h0][8:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_1 = _RANDOM[2'h0][17:9]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_2 = _RANDOM[2'h0][26:18]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_4 = _RANDOM[2'h1][12:4]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_5 = _RANDOM[2'h1][21:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_6 = _RANDOM[2'h1][30:22]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + end // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + array_0 = _RANDOM[2'h0][8:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_1 = _RANDOM[2'h0][17:9]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_2 = _RANDOM[2'h0][26:18]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]}; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_4 = _RANDOM[2'h1][12:4]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_5 = _RANDOM[2'h1][21:13]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_6 = _RANDOM[2'h1][30:22]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]}; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] endmodule diff --git a/rtl/TageSC/CAMTemplate_32.sv b/rtl/TageSC/CAMTemplate_32.sv index 1cd4bc9..b989c73 100644 --- a/rtl/TageSC/CAMTemplate_32.sv +++ b/rtl/TageSC/CAMTemplate_32.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,82 +55,82 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module CAMTemplate_32( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - input clock, - input [10:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [10:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +module CAMTemplate_32( // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input clock, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input [10:0] io_r_req_0_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_0, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_1, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_2, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_3, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_4, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_5, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_6, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_7, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input io_w_valid, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [10:0] io_w_bits_data_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [2:0] io_w_bits_index // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] ); - reg [10:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [10:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - always @(posedge clock) begin - if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [10:0] array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + always @(posedge clock) begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + if (io_w_valid & io_w_bits_index == 3'h0) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_0 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h1) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_1 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h2) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_2 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h3) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_3 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h4) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_4 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h5) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_5 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 3'h6) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_6 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & (&io_w_bits_index)) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_7 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + logic [31:0] _RANDOM[0:2]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + initial begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - array_0 = _RANDOM[2'h0][10:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_1 = _RANDOM[2'h0][21:11]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_3 = _RANDOM[2'h1][11:1]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_4 = _RANDOM[2'h1][22:12]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_6 = _RANDOM[2'h2][12:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_7 = _RANDOM[2'h2][23:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + end // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + array_0 = _RANDOM[2'h0][10:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_1 = _RANDOM[2'h0][21:11]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]}; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_3 = _RANDOM[2'h1][11:1]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_4 = _RANDOM[2'h1][22:12]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]}; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_6 = _RANDOM[2'h2][12:2]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_7 = _RANDOM[2'h2][23:13]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] endmodule diff --git a/rtl/TageSC/CAMTemplate_33.sv b/rtl/TageSC/CAMTemplate_33.sv index 28a6605..8049149 100644 --- a/rtl/TageSC/CAMTemplate_33.sv +++ b/rtl/TageSC/CAMTemplate_33.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,130 +55,130 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module CAMTemplate_33( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - input clock, - input [7:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_8, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_9, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_10, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_11, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_12, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_13, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_14, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - output io_r_resp_0_15, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [7:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 - input [3:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +module CAMTemplate_33( // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input clock, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + input [7:0] io_r_req_0_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_0, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_1, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_2, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_3, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_4, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_5, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_6, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_7, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_8, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_9, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_10, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_11, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_12, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_13, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_14, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + output io_r_resp_0_15, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input io_w_valid, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [7:0] io_w_bits_data_idx, // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] + input [3:0] io_w_bits_index // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:149:14] ); - reg [7:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - reg [7:0] array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - always @(posedge clock) begin - if (io_w_valid & io_w_bits_index == 4'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h7) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h8) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_8 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'h9) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_9 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'hA) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_10 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'hB) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_11 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'hC) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_12 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'hD) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_13 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & io_w_bits_index == 4'hE) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_14 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 - if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 - array_15 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_8; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_9; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_10; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_11; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_12; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_13; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_14; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + reg [7:0] array_15; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + always @(posedge clock) begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + if (io_w_valid & io_w_bits_index == 4'h0) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_0 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h1) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_1 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h2) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_2 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h3) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_3 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h4) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_4 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h5) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_5 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h6) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_6 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h7) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_7 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h8) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_8 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'h9) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_9 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'hA) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_10 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'hB) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_11 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'hC) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_12 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'hD) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_13 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & io_w_bits_index == 4'hE) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_14 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] + if (io_w_valid & (&io_w_bits_index)) // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18, :170:21, :171:28] + array_15 <= io_w_bits_data_idx; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:164:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + logic [31:0] _RANDOM[0:3]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + initial begin // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - array_0 = _RANDOM[2'h0][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_1 = _RANDOM[2'h0][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_2 = _RANDOM[2'h0][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_3 = _RANDOM[2'h0][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_4 = _RANDOM[2'h1][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_5 = _RANDOM[2'h1][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_6 = _RANDOM[2'h1][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_7 = _RANDOM[2'h1][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_8 = _RANDOM[2'h2][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_9 = _RANDOM[2'h2][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_10 = _RANDOM[2'h2][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_11 = _RANDOM[2'h2][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_12 = _RANDOM[2'h3][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_13 = _RANDOM[2'h3][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_14 = _RANDOM[2'h3][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 - array_15 = _RANDOM[2'h3][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + _RANDOM[i[1:0]] = `RANDOM; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + end // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + array_0 = _RANDOM[2'h0][7:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_1 = _RANDOM[2'h0][15:8]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_2 = _RANDOM[2'h0][23:16]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_3 = _RANDOM[2'h0][31:24]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_4 = _RANDOM[2'h1][7:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_5 = _RANDOM[2'h1][15:8]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_6 = _RANDOM[2'h1][23:16]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_7 = _RANDOM[2'h1][31:24]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_8 = _RANDOM[2'h2][7:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_9 = _RANDOM[2'h2][15:8]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_10 = _RANDOM[2'h2][23:16]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_11 = _RANDOM[2'h2][31:24]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_12 = _RANDOM[2'h3][7:0]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_13 = _RANDOM[2'h3][15:8]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_14 = _RANDOM[2'h3][23:16]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] + array_15 = _RANDOM[2'h3][31:24]; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_8 = io_r_req_0_idx == array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_9 = io_r_req_0_idx == array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_10 = io_r_req_0_idx == array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_11 = io_r_req_0_idx == array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_12 = io_r_req_0_idx == array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_13 = io_r_req_0_idx == array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_14 = io_r_req_0_idx == array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 - assign io_r_resp_0_15 = io_r_req_0_idx == array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_8 = io_r_req_0_idx == array_8; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_9 = io_r_req_0_idx == array_9; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_10 = io_r_req_0_idx == array_10; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_11 = io_r_req_0_idx == array_11; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_12 = io_r_req_0_idx == array_12; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_13 = io_r_req_0_idx == array_13; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_14 = io_r_req_0_idx == array_14; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] + assign io_r_resp_0_15 = io_r_req_0_idx == array_15; // @[src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:148:7, :164:18, :167:39] endmodule diff --git a/rtl/TageSC/FoldedSRAMTemplate.sv b/rtl/TageSC/FoldedSRAMTemplate.sv index 98cd5b7..da0057d 100644 --- a/rtl/TageSC/FoldedSRAMTemplate.sv +++ b/rtl/TageSC/FoldedSRAMTemplate.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,89 +55,104 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - input clock, - input reset, - output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:169:44 +module FoldedSRAMTemplate( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [10:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [10:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_waymask, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input extra_reset // @[utility/src/main/scala/utility/SRAMTemplate.scala:237:44] ); - wire _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire _array_io_r_resp_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - reg [2:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21 - reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - reg [2:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [2:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 - reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - reg [2:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [2:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 - wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - always @(posedge clock) begin - ridx <= io_r_req_bits_setIdx[2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58} - holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 - holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + wire _array_io_r_resp_data_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_7; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_8; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_9; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_10; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_11; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_12; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_13; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_14; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire _array_io_r_resp_data_15; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + reg [2:0] ridx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + reg holdRidx_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [2:0] holdRidx_hold_data; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + reg holdRidx_last_r_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [2:0] holdRidx_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (io_r_req_valid) // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + ridx <= io_r_req_bits_setIdx[2:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:{23,60}] + if (holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + holdRidx_hold_data <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + if (holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + holdRidx_hold_data_1 <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r_1 <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (io_r_req_valid | holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + holdRidx_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + if (io_r_req_valid | holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + holdRidx_last_r_1 <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 - holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][3]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 - holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 - holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 - holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r_1 = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + end end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_10 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + SRAMTemplate_14 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] .clock (clock), .reset (reset), .io_r_req_ready (io_r_req_ready), .io_r_req_valid (io_r_req_valid), - .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36 + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:257:36] .io_r_resp_data_0 (_array_io_r_resp_data_0), .io_r_resp_data_1 (_array_io_r_resp_data_1), .io_r_resp_data_2 (_array_io_r_resp_data_2), @@ -155,7 +170,7 @@ module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala: .io_r_resp_data_14 (_array_io_r_resp_data_14), .io_r_resp_data_15 (_array_io_r_resp_data_15), .io_w_req_valid (io_w_req_valid), - .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36 + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:274:36] .io_w_req_bits_data_0 (io_w_req_bits_data_0), .io_w_req_bits_data_1 (io_w_req_bits_data_1), .io_w_req_bits_data_2 (io_w_req_bits_data_0), @@ -188,7 +203,7 @@ module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala: _wmask_T_9 & io_w_req_bits_waymask[1], _wmask_T_9 & io_w_req_bits_waymask[0], _wmask_T_3 & io_w_req_bits_waymask[1], - _wmask_T_3 & io_w_req_bits_waymask[0]}), // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122} + _wmask_T_3 & io_w_req_bits_waymask[0]}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:{69,82,110,122}] .extra_reset (extra_reset) ); assign io_r_resp_data_0 = @@ -197,13 +212,13 @@ module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala: | holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4 & _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10 | holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx) - & _array_io_r_resp_data_14; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + & _array_io_r_resp_data_14; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69] assign io_r_resp_data_1 = holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1 & _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5 | holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4 & _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11 | holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1) - & _array_io_r_resp_data_15; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + & _array_io_r_resp_data_15; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69] endmodule diff --git a/rtl/TageSC/FoldedSRAMTemplate_1.sv b/rtl/TageSC/FoldedSRAMTemplate_1.sv index fdde6f2..93031b4 100644 --- a/rtl/TageSC/FoldedSRAMTemplate_1.sv +++ b/rtl/TageSC/FoldedSRAMTemplate_1.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,28 +55,28 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FoldedSRAMTemplate_1( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - input clock, - input reset, - output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +module FoldedSRAMTemplate_1( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [8:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [7:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [2:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output io_r_resp_data_1_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [7:0] io_r_resp_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [2:0] io_r_resp_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [8:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [7:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [2:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [7:0] io_w_req_bits_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [2:0] io_w_req_bits_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] ); - SRAMTemplate_11 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + SRAMTemplate_15 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] .clock (clock), .reset (reset), .io_r_req_ready (io_r_req_ready), diff --git a/rtl/TageSC/FoldedSRAMTemplate_20.sv b/rtl/TageSC/FoldedSRAMTemplate_20.sv index 1fdea3c..7ec31ef 100644 --- a/rtl/TageSC/FoldedSRAMTemplate_20.sv +++ b/rtl/TageSC/FoldedSRAMTemplate_20.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,72 +55,89 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FoldedSRAMTemplate_20( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - input clock, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 - input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +module FoldedSRAMTemplate_20( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [10:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [1:0] io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + output [1:0] io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [10:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + input [1:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] ); - wire [1:0] _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - wire [1:0] _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 - reg [1:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21 - reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - reg [1:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [1:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 - reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - reg [1:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [1:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 - wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 - always @(posedge clock) begin - ridx <= io_r_req_bits_setIdx[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58} - holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 - holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 - holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + wire [1:0] _array_io_r_resp_data_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + wire [1:0] _array_io_r_resp_data_7; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] + reg [1:0] ridx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + reg holdRidx_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [1:0] holdRidx_hold_data; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [1:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + reg holdRidx_last_r_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [1:0] holdRidx_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [1:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69] + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (io_r_req_valid) // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14] + ridx <= io_r_req_bits_setIdx[1:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:{23,60}] + if (holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + holdRidx_hold_data <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] + if (holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + holdRidx_hold_data_1 <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r_1 <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + if (io_r_req_valid | holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + holdRidx_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + if (io_r_req_valid | holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + holdRidx_last_r_1 <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - ridx = _RANDOM[/*Zero width*/ 1'b0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 - holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][2]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 - holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 - holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 - holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + ridx = _RANDOM[/*Zero width*/ 1'b0][1:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][2]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23] `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + holdRidx_last_r_1 = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + end end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_30 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + SRAMTemplate_34 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21] .clock (clock), + .reset (reset), .io_r_req_valid (io_r_req_valid), - .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36 + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:257:36] .io_r_resp_data_0 (_array_io_r_resp_data_0), .io_r_resp_data_1 (_array_io_r_resp_data_1), .io_r_resp_data_2 (_array_io_r_resp_data_2), @@ -130,7 +147,7 @@ module FoldedSRAMTemplate_20( // utility/src/main/scala/utility/SRAMTemplate.sca .io_r_resp_data_6 (_array_io_r_resp_data_6), .io_r_resp_data_7 (_array_io_r_resp_data_7), .io_w_req_valid (io_w_req_valid), - .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36 + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:274:36] .io_w_req_bits_data_0 (io_w_req_bits_data_0), .io_w_req_bits_data_1 (io_w_req_bits_data_1), .io_w_req_bits_data_2 (io_w_req_bits_data_0), @@ -147,17 +164,17 @@ module FoldedSRAMTemplate_20( // utility/src/main/scala/utility/SRAMTemplate.sca _wmask_T_9 & io_w_req_bits_waymask[1], _wmask_T_9 & io_w_req_bits_waymask[0], _wmask_T_3 & io_w_req_bits_waymask[1], - _wmask_T_3 & io_w_req_bits_waymask[0]}) // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122} + _wmask_T_3 & io_w_req_bits_waymask[0]}) // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:{69,82,110,122}] ); assign io_r_resp_data_0 = (holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0) | (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0) | (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0) - | ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + | ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69] assign io_r_resp_data_1 = (holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0) | (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0) | (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0) - | ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + | ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69] endmodule diff --git a/rtl/TageSC/SCTable.sv b/rtl/TageSC/SCTable.sv index 9db7c8a..23baf45 100644 --- a/rtl/TageSC/SCTable.sv +++ b/rtl/TageSC/SCTable.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,55 +55,55 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +module SCTable( // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input clock, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input reset, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] ); - wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 - wire per_br_update_way_mask_0_0 = + wire _wrbypasses_1_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _table_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_2; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_3; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + reg [40:0] s1_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] + wire updateWayMask_0 = io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_0_1 = + & io_update_pc[1] & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_1 = io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_1_0 = + & io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_2 = io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire per_br_update_way_mask_1_1 = + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire updateWayMask_3 = io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] wire ctrPos = - ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire [5:0] oldCtr = (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) & (ctrPos @@ -117,15 +117,15 @@ module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) - | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire taken = - ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] per_br_update_wdata_packed_0_1 = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] update_wdata_0 = oldCtr == 6'h1F & taken ? 6'h1F - : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] wire ctrPos_1 = - io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire [5:0] oldCtr_1 = (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) & (ctrPos_1 @@ -139,98 +139,89 @@ module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) - | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire taken_1 = - io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 - wire [5:0] per_br_update_wdata_packed_1_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] + wire [5:0] update_wdata_1 = oldCtr_1 == 6'h1F & taken_1 ? 6'h1F : oldCtr_1 == 6'h20 & ~taken_1 ? 6'h20 - : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 - wire [5:0] _GEN = - (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) - | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] _GEN_0 = - (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) - | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - always @(posedge clock) begin - if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 - s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + if (io_req_valid) // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + s1_pc <= io_req_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + initial begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - end // src/main/scala/xiangshan/frontend/SC.scala:66:7 - s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + end // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + SRAMTemplate_35 table_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] .clock (clock), .reset (reset), .io_r_req_valid (io_req_valid), - .io_r_req_bits_setIdx (io_req_bits_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:{11,29} + .io_r_req_bits_setIdx (io_req_bits_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:{11,29}] .io_r_resp_data_0 (_table_io_r_resp_data_0), .io_r_resp_data_1 (_table_io_r_resp_data_1), .io_r_resp_data_2 (_table_io_r_resp_data_2), .io_r_resp_data_3 (_table_io_r_resp_data_3), - .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 - .io_w_req_bits_setIdx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 - .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // @[src/main/scala/xiangshan/frontend/SC.scala:130:36] + .io_w_req_bits_setIdx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42] + .io_w_req_bits_data_0 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_1 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_2 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_3 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] .io_w_req_bits_waymask - ({per_br_update_way_mask_1_1, - per_br_update_way_mask_1_0, - per_br_update_way_mask_0_1, - per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) // @[src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29] ); - WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_0), - .io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 - .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42] + .io_write_data_0 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_write_way_mask_1 - (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_hit (_wrbypasses_0_io_hit), .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) ); - WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_1), - .io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 - .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42] + .io_write_data_0 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_write_way_mask_1 - (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_hit (_wrbypasses_1_io_hit), .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), @@ -239,15 +230,15 @@ module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7 ); assign io_resp_ctrs_0_0 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) - | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_0_1 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) - | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_0 = (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_1 = (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] endmodule diff --git a/rtl/TageSC/SCTable_1.sv b/rtl/TageSC/SCTable_1.sv index 1442041..3a9e53d 100644 --- a/rtl/TageSC/SCTable_1.sv +++ b/rtl/TageSC/SCTable_1.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,59 +55,59 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +module SCTable_1( // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input clock, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input reset, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [3:0] io_update_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] ); - wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 - wire per_br_update_way_mask_0_0 = + wire _wrbypasses_1_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _table_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_2; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_3; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + reg [40:0] s1_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] + wire updateWayMask_0 = io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_0_1 = + & io_update_pc[1] & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_1 = io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_1_0 = + & io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_2 = io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire per_br_update_way_mask_1_1 = + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire updateWayMask_3 = io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] wire [7:0] update_idx = - {io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist}; // src/main/scala/xiangshan/frontend/SC.scala:86:{31,40}, :117:42 + {io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist}; // @[src/main/scala/xiangshan/frontend/SC.scala:86:{31,40}, :117:42] wire ctrPos = - ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire [5:0] oldCtr = (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) & (ctrPos @@ -121,15 +121,15 @@ module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) - | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire taken = - ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] per_br_update_wdata_packed_0_1 = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] update_wdata_0 = oldCtr == 6'h1F & taken ? 6'h1F - : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] wire ctrPos_1 = - io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire [5:0] oldCtr_1 = (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) & (ctrPos_1 @@ -143,100 +143,91 @@ module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) - | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire taken_1 = - io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 - wire [5:0] per_br_update_wdata_packed_1_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] + wire [5:0] update_wdata_1 = oldCtr_1 == 6'h1F & taken_1 ? 6'h1F : oldCtr_1 == 6'h20 & ~taken_1 ? 6'h20 - : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 - wire [5:0] _GEN = - (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) - | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] _GEN_0 = - (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) - | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - always @(posedge clock) begin - if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 - s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + if (io_req_valid) // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + s1_pc <= io_req_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + initial begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - end // src/main/scala/xiangshan/frontend/SC.scala:66:7 - s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + end // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + SRAMTemplate_35 table_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] .clock (clock), .reset (reset), .io_r_req_valid (io_req_valid), .io_r_req_bits_setIdx ({io_req_bits_pc[8:5], - io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31,40} + io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}), // @[src/main/scala/xiangshan/frontend/SC.scala:86:{12,31,40}] .io_r_resp_data_0 (_table_io_r_resp_data_0), .io_r_resp_data_1 (_table_io_r_resp_data_1), .io_r_resp_data_2 (_table_io_r_resp_data_2), .io_r_resp_data_3 (_table_io_r_resp_data_3), - .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 - .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // @[src/main/scala/xiangshan/frontend/SC.scala:130:36] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:40] + .io_w_req_bits_data_0 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_1 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_2 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_3 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] .io_w_req_bits_waymask - ({per_br_update_way_mask_1_1, - per_br_update_way_mask_1_0, - per_br_update_way_mask_0_1, - per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) // @[src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29] ); - WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_0), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 - .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:40] + .io_write_data_0 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_write_way_mask_1 - (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_hit (_wrbypasses_0_io_hit), .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) ); - WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_1), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 - .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:40] + .io_write_data_0 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_write_way_mask_1 - (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_hit (_wrbypasses_1_io_hit), .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), @@ -245,15 +236,15 @@ module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7 ); assign io_resp_ctrs_0_0 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) - | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_0_1 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) - | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_0 = (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_1 = (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] endmodule diff --git a/rtl/TageSC/SCTable_2.sv b/rtl/TageSC/SCTable_2.sv index 61ca86e..40af043 100644 --- a/rtl/TageSC/SCTable_2.sv +++ b/rtl/TageSC/SCTable_2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,58 +55,58 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [7:0] io_req_bits_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [7:0] io_update_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +module SCTable_2( // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input clock, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input reset, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [7:0] io_req_bits_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [7:0] io_update_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] ); - wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 - wire per_br_update_way_mask_0_0 = + wire _wrbypasses_1_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _table_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_2; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_3; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + reg [40:0] s1_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] + wire updateWayMask_0 = io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_0_1 = + & io_update_pc[1] & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_1 = io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_1_0 = + & io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_2 = io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire per_br_update_way_mask_1_1 = + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire updateWayMask_3 = io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42] wire ctrPos = - ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire [5:0] oldCtr = (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) & (ctrPos @@ -120,15 +120,15 @@ module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) - | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire taken = - ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] per_br_update_wdata_packed_0_1 = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] update_wdata_0 = oldCtr == 6'h1F & taken ? 6'h1F - : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] wire ctrPos_1 = - io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire [5:0] oldCtr_1 = (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) & (ctrPos_1 @@ -142,99 +142,90 @@ module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) - | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire taken_1 = - io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 - wire [5:0] per_br_update_wdata_packed_1_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] + wire [5:0] update_wdata_1 = oldCtr_1 == 6'h1F & taken_1 ? 6'h1F : oldCtr_1 == 6'h20 & ~taken_1 ? 6'h20 - : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 - wire [5:0] _GEN = - (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) - | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] _GEN_0 = - (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) - | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - always @(posedge clock) begin - if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 - s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + if (io_req_valid) // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + s1_pc <= io_req_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + initial begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - end // src/main/scala/xiangshan/frontend/SC.scala:66:7 - s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + end // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + SRAMTemplate_35 table_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] .clock (clock), .reset (reset), .io_r_req_valid (io_req_valid), .io_r_req_bits_setIdx - (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31} + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/SC.scala:86:{12,31}] .io_r_resp_data_0 (_table_io_r_resp_data_0), .io_r_resp_data_1 (_table_io_r_resp_data_1), .io_r_resp_data_2 (_table_io_r_resp_data_2), .io_r_resp_data_3 (_table_io_r_resp_data_3), - .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // @[src/main/scala/xiangshan/frontend/SC.scala:130:36] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_w_req_bits_data_0 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_1 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_2 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_3 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] .io_w_req_bits_waymask - ({per_br_update_way_mask_1_1, - per_br_update_way_mask_1_0, - per_br_update_way_mask_0_1, - per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) // @[src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29] ); - WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_0), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_write_data_0 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_write_way_mask_1 - (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_hit (_wrbypasses_0_io_hit), .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) ); - WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_1), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_write_data_0 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_write_way_mask_1 - (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_hit (_wrbypasses_1_io_hit), .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), @@ -243,15 +234,15 @@ module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7 ); assign io_resp_ctrs_0_0 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) - | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_0_1 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) - | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_0 = (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_1 = (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] endmodule diff --git a/rtl/TageSC/SCTable_3.sv b/rtl/TageSC/SCTable_3.sv index ed6b86a..45f09f8 100644 --- a/rtl/TageSC/SCTable_3.sv +++ b/rtl/TageSC/SCTable_3.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,58 +55,58 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7 - input clock, - input reset, - input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 - input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +module SCTable_3( // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input clock, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input reset, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_0_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + output [5:0] io_resp_ctrs_1_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [7:0] io_update_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input [5:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_tagePreds_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] ); - wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 - wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 - reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 - wire per_br_update_way_mask_0_0 = + wire _wrbypasses_1_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_1_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire _wrbypasses_0_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] + wire [5:0] _table_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_2; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + wire [5:0] _table_io_r_resp_data_3; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] + reg [40:0] s1_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] + wire updateWayMask_0 = io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_0_1 = + & io_update_pc[1] & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_1 = io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 - & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire per_br_update_way_mask_1_0 = + & io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire updateWayMask_2 = io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire per_br_update_way_mask_1_1 = + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire updateWayMask_3 = io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 - & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 - wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42] wire ctrPos = - ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire [5:0] oldCtr = (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) & (ctrPos @@ -120,15 +120,15 @@ module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) - | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42] wire taken = - ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] per_br_update_wdata_packed_0_1 = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] update_wdata_0 = oldCtr == 6'h1F & taken ? 6'h1F - : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] wire ctrPos_1 = - io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire [5:0] oldCtr_1 = (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) & (ctrPos_1 @@ -142,99 +142,90 @@ module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7 : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) - | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] wire taken_1 = - io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 - wire [5:0] per_br_update_wdata_packed_1_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92] + wire [5:0] update_wdata_1 = oldCtr_1 == 6'h1F & taken_1 ? 6'h1F : oldCtr_1 == 6'h20 & ~taken_1 ? 6'h20 - : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 - wire [5:0] _GEN = - (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) - | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - wire [5:0] _GEN_0 = - (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) - | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 - always @(posedge clock) begin - if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 - s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21] + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + if (io_req_valid) // @[src/main/scala/xiangshan/frontend/SC.scala:68:14] + s1_pc <= io_req_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + initial begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 - end // src/main/scala/xiangshan/frontend/SC.scala:66:7 - s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + end // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + SRAMTemplate_35 table_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:71:21] .clock (clock), .reset (reset), .io_r_req_valid (io_req_valid), .io_r_req_bits_setIdx - (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31} + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/SC.scala:86:{12,31}] .io_r_resp_data_0 (_table_io_r_resp_data_0), .io_r_resp_data_1 (_table_io_r_resp_data_1), .io_r_resp_data_2 (_table_io_r_resp_data_2), .io_r_resp_data_3 (_table_io_r_resp_data_3), - .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 - .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // @[src/main/scala/xiangshan/frontend/SC.scala:130:36] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_w_req_bits_data_0 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_1 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_2 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] + .io_w_req_bits_data_3 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8] .io_w_req_bits_waymask - ({per_br_update_way_mask_1_1, - per_br_update_way_mask_1_0, - per_br_update_way_mask_0_1, - per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) // @[src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29] ); - WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_0), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_write_data_0 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_write_way_mask_1 - (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42] .io_hit (_wrbypasses_0_io_hit), .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) ); - WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + WrBypass_33 wrbypasses_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42] .clock (clock), .reset (reset), .io_wen (io_update_mask_1), - .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 - .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 - .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_idx (update_idx), // @[src/main/scala/xiangshan/frontend/SC.scala:86:31] + .io_write_data_0 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] + .io_write_data_1 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73] .io_write_way_mask_0 - (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_write_way_mask_1 - (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) - & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92] .io_hit (_wrbypasses_1_io_hit), .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), @@ -243,15 +234,15 @@ module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7 ); assign io_resp_ctrs_0_0 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) - | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_0_1 = (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) - | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_0 = (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] assign io_resp_ctrs_1_1 = (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) - | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42] endmodule diff --git a/rtl/TageSC/SRAMTemplate_10.sv b/rtl/TageSC/SRAMTemplate_10.sv deleted file mode 100644 index ced545b..0000000 --- a/rtl/TageSC/SRAMTemplate_10.sv +++ /dev/null @@ -1,277 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_10( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_bits_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [15:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:102:44 -); - - wire wdata_15; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_14; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_13; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_12; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_11; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_10; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_9; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_8; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_7; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_6; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_5; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_4; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [7:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 - wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 - wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - wire [15:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} - assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - assign wdata_0 = ~_resetState & io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_1 = ~_resetState & io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_2 = ~_resetState & io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_3 = ~_resetState & io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_4 = ~_resetState & io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_5 = ~_resetState & io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_6 = ~_resetState & io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_7 = ~_resetState & io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_8 = ~_resetState & io_w_req_bits_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_9 = ~_resetState & io_w_req_bits_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_10 = ~_resetState & io_w_req_bits_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_11 = ~_resetState & io_w_req_bits_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_12 = ~_resetState & io_w_req_bits_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_13 = ~_resetState & io_w_req_bits_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_14 = ~_resetState & io_w_req_bits_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - assign wdata_15 = ~_resetState & io_w_req_bits_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82 - reg rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82 - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - else begin - _resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}, :113:30, :114:21 - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 - end - end // always @(posedge, posedge) - always @(posedge clock) begin - rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 - if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= _array_RW0_rdata[0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_1 <= _array_RW0_rdata[1]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_2 <= _array_RW0_rdata[2]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_3 <= _array_RW0_rdata[3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_4 <= _array_RW0_rdata[4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_5 <= _array_RW0_rdata[5]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_6 <= _array_RW0_rdata[6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_7 <= _array_RW0_rdata[7]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_8 <= _array_RW0_rdata[8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_9 <= _array_RW0_rdata[9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_10 <= _array_RW0_rdata[10]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_11 <= _array_RW0_rdata[11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_12 <= _array_RW0_rdata[12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_13 <= _array_RW0_rdata[13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_14 <= _array_RW0_rdata[14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_15 <= _array_RW0_rdata[15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - end - end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[6'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[6'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - rdata_REG = _RANDOM[6'h21][10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_0 = _RANDOM[6'h21][11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_1 = _RANDOM[6'h21][12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_2 = _RANDOM[6'h21][13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_3 = _RANDOM[6'h21][14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_4 = _RANDOM[6'h21][15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_5 = _RANDOM[6'h21][16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_6 = _RANDOM[6'h21][17]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_7 = _RANDOM[6'h21][18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_8 = _RANDOM[6'h21][19]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_9 = _RANDOM[6'h21][20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_10 = _RANDOM[6'h21][21]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_11 = _RANDOM[6'h21][22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_12 = _RANDOM[6'h21][23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_13 = _RANDOM[6'h21][24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_14 = _RANDOM[6'h21][25]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_15 = _RANDOM[6'h21][26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_4 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 - .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 - .RW0_clk (clock), - .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - .RW0_wdata - ({wdata_15, - wdata_14, - wdata_13, - wdata_12, - wdata_11, - wdata_10, - wdata_9, - wdata_8, - wdata_7, - wdata_6, - wdata_5, - wdata_4, - wdata_3, - wdata_2, - wdata_1, - wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 - .RW0_rdata (_array_RW0_rdata), - .RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} - ); - assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} - assign io_r_resp_data_0 = rdata_REG ? _array_RW0_rdata[0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_1 = rdata_REG ? _array_RW0_rdata[1] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_2 = rdata_REG ? _array_RW0_rdata[2] : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_3 = rdata_REG ? _array_RW0_rdata[3] : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_4 = rdata_REG ? _array_RW0_rdata[4] : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_5 = rdata_REG ? _array_RW0_rdata[5] : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_6 = rdata_REG ? _array_RW0_rdata[6] : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_7 = rdata_REG ? _array_RW0_rdata[7] : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_8 = rdata_REG ? _array_RW0_rdata[8] : rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_9 = rdata_REG ? _array_RW0_rdata[9] : rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_10 = rdata_REG ? _array_RW0_rdata[10] : rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_11 = rdata_REG ? _array_RW0_rdata[11] : rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_12 = rdata_REG ? _array_RW0_rdata[12] : rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_13 = rdata_REG ? _array_RW0_rdata[13] : rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_14 = rdata_REG ? _array_RW0_rdata[14] : rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 - assign io_r_resp_data_15 = rdata_REG ? _array_RW0_rdata[15] : rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 -endmodule - diff --git a/rtl/TageSC/SRAMTemplate_11.sv b/rtl/TageSC/SRAMTemplate_11.sv deleted file mode 100644 index 93e82bb..0000000 --- a/rtl/TageSC/SRAMTemplate_11.sv +++ /dev/null @@ -1,174 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_11( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 -); - - wire [2:0] _wdata_T_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [7:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_1_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26 - wire [2:0] _wdata_T_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [7:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire _wdata_T_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26 - wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 - wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 - wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - wire [23:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} - assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - assign _wdata_T_0_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26 - assign _wdata_T_0_tag = _resetState ? 8'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_0_ctr = _resetState ? 3'h0 : io_w_req_bits_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26 - assign _wdata_T_1_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26 - assign _wdata_T_1_tag = _resetState ? 8'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign _wdata_T_1_ctr = _resetState ? 3'h0 : io_w_req_bits_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26 - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg [11:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [11:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - wire [11:0] _rdata_WIRE = rdata_REG ? _array_RW0_rdata[11:0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 - wire [11:0] _rdata_WIRE_1 = rdata_REG ? _array_RW0_rdata[23:12] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30 - _resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - else begin - _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 - end - end // always @(posedge, posedge) - always @(posedge clock) begin - rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 - if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= _array_RW0_rdata[11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - rdata_hold_data_1 <= _array_RW0_rdata[23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - end - end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[3'h0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - rdata_REG = _RANDOM[3'h4][31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 - rdata_hold_data_0 = _RANDOM[3'h5][11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - rdata_hold_data_1 = _RANDOM[3'h5][23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30 - _resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_5 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 - .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 - .RW0_clk (clock), - .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 - .RW0_wdata - ({_wdata_T_1_valid, - _wdata_T_1_tag, - _wdata_T_1_ctr, - _wdata_T_0_valid, - _wdata_T_0_tag, - _wdata_T_0_ctr}), // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :105:26, :126:26 - .RW0_rdata (_array_RW0_rdata), - .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} - ); - assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} - assign io_r_resp_data_0_valid = _rdata_WIRE[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_tag = _rdata_WIRE[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_0_ctr = _rdata_WIRE[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_valid = _rdata_WIRE_1[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_tag = _rdata_WIRE_1[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 - assign io_r_resp_data_1_ctr = _rdata_WIRE_1[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 -endmodule - diff --git a/rtl/TageSC/SRAMTemplate_14.sv b/rtl/TageSC/SRAMTemplate_14.sv new file mode 100644 index 0000000..69ee4d3 --- /dev/null +++ b/rtl/TageSC/SRAMTemplate_14.sv @@ -0,0 +1,248 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_14( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_4, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_5, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_6, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_7, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_8, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_9, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_10, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_11, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_12, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_13, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_14, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_15, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_4, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_5, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_6, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_7, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_8, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_9, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_10, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_11, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_12, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_13, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_14, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_bits_data_15, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [15:0] io_w_req_bits_waymask, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input extra_reset // @[utility/src/main/scala/utility/SRAMTemplate.scala:148:44] +); + + wire [7:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19] + wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + wire [15:0] _array_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [7:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}] + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_2; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_3; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_4; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_5; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_6; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_7; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_8; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_9; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_10; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_11; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_12; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_13; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_14; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg rdata_hold_data_15; // @[utility/src/main/scala/utility/Hold.scala:24:82] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet <= 8'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}, :162:30, :163:21] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 8'(_resetSet + 8'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + if (realRen | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + rdata_last_r <= realRen; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + end + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (rdata_last_r) begin // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= _array_RW0_rdata[0]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_1 <= _array_RW0_rdata[1]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_2 <= _array_RW0_rdata[2]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_3 <= _array_RW0_rdata[3]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_4 <= _array_RW0_rdata[4]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_5 <= _array_RW0_rdata[5]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_6 <= _array_RW0_rdata[6]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_7 <= _array_RW0_rdata[7]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_8 <= _array_RW0_rdata[8]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_9 <= _array_RW0_rdata[9]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_10 <= _array_RW0_rdata[10]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_11 <= _array_RW0_rdata[11]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_12 <= _array_RW0_rdata[12]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_13 <= _array_RW0_rdata[13]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_14 <= _array_RW0_rdata[14]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_15 <= _array_RW0_rdata[15]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:33]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[6'h0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[6'h0][8:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + rdata_last_r = _RANDOM[6'h21][10]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_0 = _RANDOM[6'h21][11]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_1 = _RANDOM[6'h21][12]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_2 = _RANDOM[6'h21][13]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_3 = _RANDOM[6'h21][14]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_4 = _RANDOM[6'h21][15]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_5 = _RANDOM[6'h21][16]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_6 = _RANDOM[6'h21][17]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_7 = _RANDOM[6'h21][18]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_8 = _RANDOM[6'h21][19]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_9 = _RANDOM[6'h21][20]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_10 = _RANDOM[6'h21][21]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_11 = _RANDOM[6'h21][22]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_12 = _RANDOM[6'h21][23]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_13 = _RANDOM[6'h21][24]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_14 = _RANDOM[6'h21][25]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_15 = _RANDOM[6'h21][26]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = 8'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_4 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19] + .RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38] + .RW0_clk (clock), + .RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + .RW0_wdata + ({~_resetState & io_w_req_bits_data_15, + ~_resetState & io_w_req_bits_data_14, + ~_resetState & io_w_req_bits_data_13, + ~_resetState & io_w_req_bits_data_12, + ~_resetState & io_w_req_bits_data_11, + ~_resetState & io_w_req_bits_data_10, + ~_resetState & io_w_req_bits_data_9, + ~_resetState & io_w_req_bits_data_8, + ~_resetState & io_w_req_bits_data_7, + ~_resetState & io_w_req_bits_data_6, + ~_resetState & io_w_req_bits_data_5, + ~_resetState & io_w_req_bits_data_4, + ~_resetState & io_w_req_bits_data_3, + ~_resetState & io_w_req_bits_data_2, + ~_resetState & io_w_req_bits_data_1, + ~_resetState & io_w_req_bits_data_0}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :175:18, :176:13] + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}] + ); + assign io_r_req_ready = ~_resetState & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :171:52, :172:41, :222:{21,33}] + assign io_r_resp_data_0 = rdata_last_r ? _array_RW0_rdata[0] : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_1 = rdata_last_r ? _array_RW0_rdata[1] : rdata_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_2 = rdata_last_r ? _array_RW0_rdata[2] : rdata_hold_data_2; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_3 = rdata_last_r ? _array_RW0_rdata[3] : rdata_hold_data_3; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_4 = rdata_last_r ? _array_RW0_rdata[4] : rdata_hold_data_4; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_5 = rdata_last_r ? _array_RW0_rdata[5] : rdata_hold_data_5; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_6 = rdata_last_r ? _array_RW0_rdata[6] : rdata_hold_data_6; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_7 = rdata_last_r ? _array_RW0_rdata[7] : rdata_hold_data_7; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_8 = rdata_last_r ? _array_RW0_rdata[8] : rdata_hold_data_8; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_9 = rdata_last_r ? _array_RW0_rdata[9] : rdata_hold_data_9; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_10 = rdata_last_r ? _array_RW0_rdata[10] : rdata_hold_data_10; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_11 = rdata_last_r ? _array_RW0_rdata[11] : rdata_hold_data_11; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_12 = rdata_last_r ? _array_RW0_rdata[12] : rdata_hold_data_12; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_13 = rdata_last_r ? _array_RW0_rdata[13] : rdata_hold_data_13; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_14 = rdata_last_r ? _array_RW0_rdata[14] : rdata_hold_data_14; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] + assign io_r_resp_data_15 = rdata_last_r ? _array_RW0_rdata[15] : rdata_hold_data_15; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :192:69] +endmodule + diff --git a/rtl/TageSC/SRAMTemplate_15.sv b/rtl/TageSC/SRAMTemplate_15.sv new file mode 100644 index 0000000..2f56030 --- /dev/null +++ b/rtl/TageSC/SRAMTemplate_15.sv @@ -0,0 +1,165 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_15( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [7:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [2:0] io_r_resp_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output io_r_resp_data_1_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [7:0] io_r_resp_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [2:0] io_r_resp_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [2:0] io_w_req_bits_data_0_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_w_req_bits_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [2:0] io_w_req_bits_data_1_ctr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] +); + + wire [8:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19] + wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + wire [23:0] _array_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [8:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}] + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [11:0] rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [11:0] rdata_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + wire [11:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[11:0] : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + wire [11:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[23:12] : rdata_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet <= 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 9'(_resetSet + 9'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + if (realRen | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + rdata_last_r <= realRen; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:172:38] + end + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (rdata_last_r) begin // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= _array_RW0_rdata[11:0]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + rdata_hold_data_1 <= _array_RW0_rdata[23:12]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69] + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[3'h0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[3'h0][9:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + rdata_last_r = _RANDOM[3'h4][31]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_0 = _RANDOM[3'h5][11:0]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_1 = _RANDOM[3'h5][23:12]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14, :158:30] + _resetSet = 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_5 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19] + .RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38] + .RW0_clk (clock), + .RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52] + .RW0_wdata + ({~_resetState, + _resetState ? 8'h0 : io_w_req_bits_data_1_tag, + _resetState ? 3'h0 : io_w_req_bits_data_1_ctr, + ~_resetState, + _resetState ? 8'h0 : io_w_req_bits_data_0_tag, + _resetState ? 3'h0 : io_w_req_bits_data_0_ctr}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :144:14, :158:30, :175:{18,43}, :176:13] + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}] + ); + assign io_r_req_ready = ~_resetState & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :171:52, :172:41, :222:{21,33}] + assign io_r_resp_data_0_valid = _rdata_T_0[11]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_tag = _rdata_T_0[10:3]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_0_ctr = _rdata_T_0[2:0]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_valid = _rdata_T_1[11]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_tag = _rdata_T_1[10:3]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] + assign io_r_resp_data_1_ctr = _rdata_T_1[2:0]; // @[utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :219:45] +endmodule + diff --git a/rtl/TageSC/SRAMTemplate_30.sv b/rtl/TageSC/SRAMTemplate_30.sv deleted file mode 100644 index bdbb0de..0000000 --- a/rtl/TageSC/SRAMTemplate_30.sv +++ /dev/null @@ -1,209 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_30( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [1:0] io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [1:0] io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 -); - - wire [15:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg [1:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [1:0] bypass_wdata_REG_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29 - reg [8:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 - reg [8:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 - reg [7:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 - wire [7:0] bypass_mask = - {8{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} - & bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76} - wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_REG_4 : _array_R0_data[9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_REG_5 : _array_R0_data[11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_REG_6 : _array_R0_data[13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_REG_7 : _array_R0_data[15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg [1:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [1:0] rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82 - always @(posedge clock) begin - bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_4 <= io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_5 <= io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_6 <= io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_7 <= io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34} - bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 - bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 - bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 - rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_4 <= mem_rdata_4; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_5 <= mem_rdata_5; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_6 <= mem_rdata_6; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_7 <= mem_rdata_7; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - end - end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - bypass_wdata_REG_0 = _RANDOM[1'h0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_1 = _RANDOM[1'h0][3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_2 = _RANDOM[1'h0][5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_3 = _RANDOM[1'h0][7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_4 = _RANDOM[1'h0][9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_5 = _RANDOM[1'h0][11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_6 = _RANDOM[1'h0][13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_wdata_REG_7 = _RANDOM[1'h0][15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - bypass_mask_need_check = _RANDOM[1'h0][16]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54 - bypass_mask_waddr_reg = _RANDOM[1'h0][25:17]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54 - bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54 - bypass_mask_bypass_REG = _RANDOM[1'h1][10:3]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :139:76 - rdata_REG = _RANDOM[1'h1][11]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :153:59 - rdata_hold_data_0 = _RANDOM[1'h1][13:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_1 = _RANDOM[1'h1][15:14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_2 = _RANDOM[1'h1][17:16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_3 = _RANDOM[1'h1][19:18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_4 = _RANDOM[1'h1][21:20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_5 = _RANDOM[1'h1][23:22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_6 = _RANDOM[1'h1][25:24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - rdata_hold_data_7 = _RANDOM[1'h1][27:26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 - `endif // RANDOMIZE_REG_INIT - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_6 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .R0_addr (io_r_req_bits_setIdx), - .R0_en (io_r_req_valid), - .R0_clk (clock), - .R0_data (_array_R0_data), - .W0_addr (io_w_req_bits_setIdx), - .W0_en (io_w_req_valid), - .W0_clk (clock), - .W0_data - ({io_w_req_bits_data_7, - io_w_req_bits_data_6, - io_w_req_bits_data_5, - io_w_req_bits_data_4, - io_w_req_bits_data_3, - io_w_req_bits_data_2, - io_w_req_bits_data_1, - io_w_req_bits_data_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .W0_mask (io_w_req_bits_waymask) - ); - assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_4 = rdata_REG ? mem_rdata_4 : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_5 = rdata_REG ? mem_rdata_5 : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_6 = rdata_REG ? mem_rdata_6 : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_7 = rdata_REG ? mem_rdata_7 : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 -endmodule - diff --git a/rtl/TageSC/SRAMTemplate_31.sv b/rtl/TageSC/SRAMTemplate_31.sv deleted file mode 100644 index f975a8d..0000000 --- a/rtl/TageSC/SRAMTemplate_31.sv +++ /dev/null @@ -1,189 +0,0 @@ -// Generated by CIRCT firtool-1.61.0 -// Standard header to adapt well known macros for register randomization. -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ - -// Include register initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -module SRAMTemplate_31( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - input clock, - input reset, - input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [5:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [5:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [5:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - output [5:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [5:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [5:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [5:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [5:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 - input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 -); - - wire [5:0] wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [5:0] wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [5:0] wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [5:0] wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 - wire [23:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 - assign wdata_0 = _resetState ? 6'h0 : io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign wdata_1 = _resetState ? 6'h0 : io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign wdata_2 = _resetState ? 6'h0 : io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - assign wdata_3 = _resetState ? 6'h0 : io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} - reg [5:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [5:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [5:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg [5:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29 - reg [7:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 - reg [7:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 - reg [3:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 - wire [3:0] bypass_mask = - {4{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} - & bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76} - wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[5:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[11:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[17:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[23:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 - reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - reg [5:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [5:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [5:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 - reg [5:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 - always @(posedge clock or posedge reset) begin - if (reset) begin - _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - else begin - _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} - if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 - _resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 - end - end // always @(posedge, posedge) - always @(posedge clock) begin - bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 - bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34} - bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 - bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 - bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 - rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 - rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 - end - end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = _RANDOM[2'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = _RANDOM[2'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - bypass_wdata_REG_0 = _RANDOM[2'h0][14:9]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 - bypass_wdata_REG_1 = _RANDOM[2'h0][20:15]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 - bypass_wdata_REG_2 = _RANDOM[2'h0][26:21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 - bypass_wdata_REG_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 - bypass_mask_need_check = _RANDOM[2'h1][1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54 - bypass_mask_waddr_reg = _RANDOM[2'h1][9:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54 - bypass_mask_raddr_reg = _RANDOM[2'h1][17:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54 - bypass_mask_bypass_REG = _RANDOM[2'h1][21:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :139:76, :142:54 - rdata_REG = _RANDOM[2'h1][22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54, :153:59 - rdata_hold_data_0 = _RANDOM[2'h1][28:23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 - rdata_hold_data_2 = _RANDOM[2'h2][8:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - rdata_hold_data_3 = _RANDOM[2'h2][14:9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // RANDOMIZE_REG_INIT - if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 - _resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - array_7 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 - .R0_addr (io_r_req_bits_setIdx), - .R0_en (io_r_req_valid), - .R0_clk (clock), - .R0_data (_array_R0_data), - .W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx), // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 - .W0_en (io_w_req_valid | _resetState), // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 - .W0_clk (clock), - .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 - .W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} - ); - assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 - assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 -endmodule - diff --git a/rtl/TageSC/SRAMTemplate_34.sv b/rtl/TageSC/SRAMTemplate_34.sv new file mode 100644 index 0000000..4e64ecc --- /dev/null +++ b/rtl/TageSC/SRAMTemplate_34.sv @@ -0,0 +1,229 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_34( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_4, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_5, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_6, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [1:0] io_r_resp_data_7, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [8:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_4, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_5, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_6, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [1:0] io_w_req_bits_data_7, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] +); + + wire [15:0] _array_R0_data; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg [1:0] bypass_wdata_r_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [1:0] bypass_wdata_r_7; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid; // @[utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + reg bypass_mask_need_check_reg_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [8:0] bypass_mask_waddr_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:200:30] + reg [8:0] bypass_mask_raddr_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:201:30] + reg [7:0] bypass_mask_wmask_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:202:30] + wire [7:0] bypass_mask = + {8{bypass_mask_need_check_reg_last_r + & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:200:30, :201:30, :202:30, :204:{22,43,56,71}] + wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[1:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[3:2]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[5:4]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[7:6]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_r_4 : _array_R0_data[9:8]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_r_5 : _array_R0_data[11:10]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_r_6 : _array_R0_data[13:12]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_r_7 : _array_R0_data[15:14]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [1:0] rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_2; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_3; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_4; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_5; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_6; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [1:0] rdata_hold_data_7; // @[utility/src/main/scala/utility/Hold.scala:24:82] + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (io_w_req_valid & io_r_req_valid) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:92] + bypass_wdata_r_0 <= io_w_req_bits_data_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_1 <= io_w_req_bits_data_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_2 <= io_w_req_bits_data_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_3 <= io_w_req_bits_data_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_4 <= io_w_req_bits_data_4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_5 <= io_w_req_bits_data_5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_6 <= io_w_req_bits_data_6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_7 <= io_w_req_bits_data_7; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + end + if (bypass_mask_need_check) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:200:30] + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:201:30] + bypass_mask_wmask_reg <= io_w_req_bits_waymask; // @[utility/src/main/scala/utility/SRAMTemplate.scala:202:30] + end + if (rdata_last_r) begin // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= mem_rdata_0; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_1 <= mem_rdata_1; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_2 <= mem_rdata_2; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_3 <= mem_rdata_3; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_4 <= mem_rdata_4; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_5 <= mem_rdata_5; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_6 <= mem_rdata_6; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_7 <= mem_rdata_7; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + bypass_mask_need_check_reg_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + bypass_mask_need_check_reg_last_r <= bypass_mask_need_check; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + if (io_r_req_valid | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + rdata_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + bypass_wdata_r_0 = _RANDOM[1'h0][1:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_1 = _RANDOM[1'h0][3:2]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_2 = _RANDOM[1'h0][5:4]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_3 = _RANDOM[1'h0][7:6]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_4 = _RANDOM[1'h0][9:8]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_5 = _RANDOM[1'h0][11:10]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_6 = _RANDOM[1'h0][13:12]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_wdata_r_7 = _RANDOM[1'h0][15:14]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_mask_need_check_reg_last_r = _RANDOM[1'h0][16]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_mask_waddr_reg = _RANDOM[1'h0][25:17]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :200:30, :207:56] + bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]}; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30, :207:56] + bypass_mask_wmask_reg = _RANDOM[1'h1][10:3]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30, :202:30] + rdata_last_r = _RANDOM[1'h1][11]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_0 = _RANDOM[1'h1][13:12]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_1 = _RANDOM[1'h1][15:14]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_2 = _RANDOM[1'h1][17:16]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_3 = _RANDOM[1'h1][19:18]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_4 = _RANDOM[1'h1][21:20]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_5 = _RANDOM[1'h1][23:22]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_6 = _RANDOM[1'h1][25:24]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + rdata_hold_data_7 = _RANDOM[1'h1][27:26]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + bypass_mask_need_check_reg_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_6 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (io_w_req_bits_setIdx), + .W0_en (io_w_req_valid), + .W0_clk (clock), + .W0_data + ({io_w_req_bits_data_7, + io_w_req_bits_data_6, + io_w_req_bits_data_5, + io_w_req_bits_data_4, + io_w_req_bits_data_3, + io_w_req_bits_data_2, + io_w_req_bits_data_1, + io_w_req_bits_data_0}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:176:13] + .W0_mask (io_w_req_bits_waymask) + ); + assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_4 = rdata_last_r ? mem_rdata_4 : rdata_hold_data_4; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_5 = rdata_last_r ? mem_rdata_5 : rdata_hold_data_5; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_6 = rdata_last_r ? mem_rdata_6 : rdata_hold_data_6; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_7 = rdata_last_r ? mem_rdata_7 : rdata_hold_data_7; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] +endmodule + diff --git a/rtl/TageSC/SRAMTemplate_35.sv b/rtl/TageSC/SRAMTemplate_35.sv new file mode 100644 index 0000000..e9d4aa4 --- /dev/null +++ b/rtl/TageSC/SRAMTemplate_35.sv @@ -0,0 +1,196 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_35( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [5:0] io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [5:0] io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [5:0] io_r_resp_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + output [5:0] io_r_resp_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [7:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [5:0] io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [5:0] io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [5:0] io_w_req_bits_data_2, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [5:0] io_w_req_bits_data_3, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] + input [3:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14] +); + + wire [23:0] _array_R0_data; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + reg [7:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + reg [5:0] bypass_wdata_r_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [5:0] bypass_wdata_r_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [5:0] bypass_wdata_r_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + reg [5:0] bypass_wdata_r_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid; // @[utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + reg bypass_mask_need_check_reg_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [7:0] bypass_mask_waddr_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:200:30] + reg [7:0] bypass_mask_raddr_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:201:30] + reg [3:0] bypass_mask_wmask_reg; // @[utility/src/main/scala/utility/SRAMTemplate.scala:202:30] + wire [3:0] bypass_mask = + {4{bypass_mask_need_check_reg_last_r + & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:200:30, :201:30, :202:30, :204:{22,43,56,71}] + wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[5:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[11:6]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[17:12]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[23:18]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :192:69, :204:71, :207:56, :212:30, :213:30] + reg rdata_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg [5:0] rdata_hold_data_0; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [5:0] rdata_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [5:0] rdata_hold_data_2; // @[utility/src/main/scala/utility/Hold.scala:24:82] + reg [5:0] rdata_hold_data_3; // @[utility/src/main/scala/utility/Hold.scala:24:82] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet <= 8'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + bypass_mask_need_check_reg_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}] + if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30] + _resetSet <= 8'(_resetSet + 8'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24] + if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}, utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + bypass_mask_need_check_reg_last_r <= bypass_mask_need_check; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + if (io_r_req_valid | rdata_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + rdata_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + end + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + if (io_w_req_valid & io_r_req_valid) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:92] + bypass_wdata_r_0 <= io_w_req_bits_data_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_1 <= io_w_req_bits_data_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_2 <= io_w_req_bits_data_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + bypass_wdata_r_3 <= io_w_req_bits_data_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:207:56] + end + if (bypass_mask_need_check) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:198:26] + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:200:30] + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:201:30] + bypass_mask_wmask_reg <= io_w_req_bits_waymask; // @[utility/src/main/scala/utility/SRAMTemplate.scala:202:30] + end + if (rdata_last_r) begin // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + rdata_hold_data_0 <= mem_rdata_0; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_1 <= mem_rdata_1; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_2 <= mem_rdata_2; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + rdata_hold_data_3 <= mem_rdata_3; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:213:30] + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = _RANDOM[2'h0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = _RANDOM[2'h0][8:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + bypass_wdata_r_0 = _RANDOM[2'h0][14:9]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :207:56] + bypass_wdata_r_1 = _RANDOM[2'h0][20:15]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :207:56] + bypass_wdata_r_2 = _RANDOM[2'h0][26:21]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :207:56] + bypass_wdata_r_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]}; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :207:56] + bypass_mask_need_check_reg_last_r = _RANDOM[2'h1][1]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + bypass_mask_waddr_reg = _RANDOM[2'h1][9:2]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :200:30, :207:56] + bypass_mask_raddr_reg = _RANDOM[2'h1][17:10]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :201:30, :207:56] + bypass_mask_wmask_reg = _RANDOM[2'h1][21:18]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :202:30, :207:56] + rdata_last_r = _RANDOM[2'h1][22]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + rdata_hold_data_0 = _RANDOM[2'h1][28:23]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]}; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :207:56] + rdata_hold_data_2 = _RANDOM[2'h2][8:3]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_hold_data_3 = _RANDOM[2'h2][14:9]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // RANDOMIZE_REG_INIT + if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + _resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30] + _resetSet = 8'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40] + bypass_mask_need_check_reg_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + rdata_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_7 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx), // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19] + .W0_en (io_w_req_valid | _resetState), // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52] + .W0_clk (clock), + .W0_data + ({_resetState ? 6'h0 : io_w_req_bits_data_3, + _resetState ? 6'h0 : io_w_req_bits_data_2, + _resetState ? 6'h0 : io_w_req_bits_data_1, + _resetState ? 6'h0 : io_w_req_bits_data_0}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :175:{18,43}, :176:13] + .W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}] + ); + assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] + assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :213:30] +endmodule + diff --git a/rtl/TageSC/TageBTable.sv b/rtl/TageSC/TageBTable.sv index cfe0cef..5eaf85d 100644 --- a/rtl/TageSC/TageBTable.sv +++ b/rtl/TageSC/TageBTable.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,121 +55,122 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module TageBTable( // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - input clock, - input reset, - output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input [38:0] io_req_bits, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - output [1:0] io_s1_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - output [1:0] io_s1_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input [1:0] io_update_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input [1:0] io_update_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - input io_update_takens_1 // src/main/scala/xiangshan/frontend/Tage.scala:138:14 +module TageBTable( // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input [40:0] io_req_bits, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + output [1:0] io_s1_cnt_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + output [1:0] io_s1_cnt_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input [1:0] io_update_cnt_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input [1:0] io_update_cnt_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] ); - wire [1:0] newCtrs_1; // src/main/scala/xiangshan/frontend/Tage.scala:213:8 - wire [1:0] newCtrs_0; // src/main/scala/xiangshan/frontend/Tage.scala:213:8 - wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 - wire _wrbypass_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 - wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 - wire _wrbypass_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 - wire [1:0] _wrbypass_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 - wire [1:0] _bt_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:154:18 - wire [1:0] _bt_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:154:18 - reg doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28 - reg [10:0] resetRow; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 - reg [10:0] s1_idx; // src/main/scala/xiangshan/frontend/Tage.scala:181:25 - wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; // src/main/scala/xiangshan/frontend/Tage.scala:193:45 + wire [1:0] newCtrs_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:213:8] + wire [1:0] newCtrs_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:213:8] + wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] + wire _wrbypass_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] + wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] + wire _wrbypass_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] + wire [1:0] _wrbypass_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] + wire [1:0] _bt_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18] + wire [1:0] _bt_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18] + reg doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28] + reg [10:0] resetRow; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25] + reg [10:0] s1_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:181:25] + wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:193:45] wire [1:0] oldCtrs_0 = _wrbypass_io_hit & (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid) ? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits) - : io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27} + : io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}] wire [1:0] oldCtrs_1 = _wrbypass_io_hit & (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid) ? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits) - : io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27} - wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21 + : io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}] + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21] assign newCtrs_0 = (&oldCtrs_0) & _GEN ? 2'h3 : oldCtrs_0 == 2'h0 & ~_GEN ? 2'h0 - : _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36 - wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21 + : _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36] + wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21] assign newCtrs_1 = (&oldCtrs_1) & _GEN_0 ? 2'h3 : oldCtrs_1 == 2'h0 & ~_GEN_0 ? 2'h0 - : _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36 - always @(posedge clock or posedge reset) begin - if (reset) begin - doing_reset <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 - resetRow <= 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 + : _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + doing_reset <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28] + resetRow <= 11'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25] end - else begin - doing_reset <= resetRow != 11'h7FF & doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :169:{18,36,50} - resetRow <= 11'(resetRow + {10'h0, doing_reset}); // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :168:24 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + doing_reset <= resetRow != 11'h7FF & doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :169:{18,36,50}] + resetRow <= 11'(resetRow + {10'h0, doing_reset}); // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :168:24] end end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) // src/main/scala/xiangshan/frontend/Tage.scala:138:14 - s1_idx <= io_req_bits[11:1]; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:181:25 + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + if (io_req_valid) // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14] + s1_idx <= io_req_bits[11:1]; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65, src/main/scala/xiangshan/frontend/Tage.scala:181:25] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 - resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :167:25 - s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :181:25 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28] + resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :167:25] + s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :181:25] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - doing_reset = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 - resetRow = 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 + if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + doing_reset = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28] + resetRow = 11'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FoldedSRAMTemplate_20 bt ( // src/main/scala/xiangshan/frontend/Tage.scala:154:18 + FoldedSRAMTemplate_20 bt ( // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18] .clock (clock), + .reset (reset), .io_r_req_valid (io_req_valid), - .io_r_req_bits_setIdx (io_req_bits[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_r_req_bits_setIdx (io_req_bits[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] .io_r_resp_data_0 (_bt_io_r_resp_data_0), .io_r_resp_data_1 (_bt_io_r_resp_data_1), - .io_w_req_valid (_wrbypass_io_wen_T | doing_reset), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :193:45, :231:41 - .io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :233:17 - .io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36} - .io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36} + .io_w_req_valid (_wrbypass_io_wen_T | doing_reset), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :193:45, :231:41] + .io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65, src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :233:17] + .io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}] + .io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}] .io_w_req_bits_waymask (doing_reset ? 2'h3 : {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]), - io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :166:28, :211:27, :226:{26,55}, :227:15, :228:6, :234:18 + io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :166:28, :211:27, :226:{26,55}, :227:15, :228:6, :234:18] ); - WrBypass_32 wrbypass ( // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + WrBypass_32 wrbypass ( // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24] .clock (clock), .reset (reset), - .io_wen (_wrbypass_io_wen_T), // src/main/scala/xiangshan/frontend/Tage.scala:193:45 - .io_write_idx (io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 - .io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8 - .io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8 + .io_wen (_wrbypass_io_wen_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:193:45] + .io_write_idx (io_update_pc[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65] + .io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8] + .io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8] .io_write_way_mask_0 (io_update_mask_0), .io_write_way_mask_1 (io_update_mask_1), .io_hit (_wrbypass_io_hit), @@ -178,10 +179,10 @@ module TageBTable( // src/main/scala/xiangshan/frontend/Tage.scala:137:7 .io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid), .io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits) ); - assign io_req_ready = ~doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :172:19 + assign io_req_ready = ~doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :172:19] assign io_s1_cnt_0 = - (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36 + (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36] assign io_s1_cnt_1 = - (s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36 + (s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36] endmodule diff --git a/rtl/TageSC/TageTable.sv b/rtl/TageSC/TageTable.sv index d547c11..2ee0383 100644 --- a/rtl/TageSC/TageTable.sv +++ b/rtl/TageSC/TageTable.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,133 +55,134 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module TageTable( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - input clock, - input reset, - output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_req_bits_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_update_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +module TageTable( // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_req_bits_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_0_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_1_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_update_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_update_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] ); - wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 - wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 - reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - wire [2:0] _resp_selected_WIRE_1 = + wire per_bank_not_silent_update_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + reg powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:399:34] + wire _resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _bank_wrbypasses_3_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _table_banks_3_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _us_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82] + wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19] + wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + reg [39:0] s1_unhashed_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:330:34] + reg [7:0] s1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:332:25] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + wire [2:0] _resp_selected_T_6 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire [2:0] _resp_selected_WIRE_5 = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire [2:0] _resp_selected_T_27 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire _unconf_selected_WIRE = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire _unconf_selected_T_6 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 @@ -190,8 +191,8 @@ module TageTable( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _unconf_selected_WIRE_1 = + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _unconf_selected_T_13 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 @@ -200,563 +201,552 @@ module TageTable( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _hit_selected_WIRE = + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _hit_selected_T_6 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag - & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag - & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag - & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag - & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - wire _hit_selected_WIRE_1 = + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + wire _hit_selected_T_13 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag - & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag - & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag - & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag - & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - assign _resp_invalid_by_write_WIRE = + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + assign _resp_invalid_by_write_T_6 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 - | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 - wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire [7:0] per_bank_update_wdata_3_1_tag = - _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52} - wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48] + wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire [7:0] update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}] + wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] wire [1:0] per_bank_update_way_mask_0 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_0_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_0_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_1 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_1_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_1_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_2 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_2_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_2_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_3 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_3_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_3_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire _s1_bank_has_write_on_this_req_WIRE_0 = - (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_1 = - (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_2 = - (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_3 = - (|per_bank_update_way_mask_3) & (&(_GEN_0[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} - wire [2:0] _wrbypass_io_WIRE_2 = + (|per_bank_update_way_mask_3) & (&(_GEN_0[1:0])); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}] + wire [2:0] _wrbypass_io_T_6 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid = (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] & _bank_wrbypasses_0_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 - wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_3 = (|_GEN_2) | _GEN_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 - wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] + wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_3 = (|_GEN_2) | _GEN_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :98:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14] + wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_0_ctr = _GEN_4 ? (_GEN_1 ? 3'h4 : 3'h3) : wrbypass_data_valid - ? ((&_wrbypass_io_WIRE_2) & _GEN_1 + ? ((&_wrbypass_io_T_6) & _GEN_1 ? 3'h7 - : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1 + : _wrbypass_io_T_6 == 3'h0 & ~_GEN_1 ? 3'h0 - : _GEN_1 - ? 3'(_wrbypass_io_WIRE_2 + 3'h1) - : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) : (&_GEN_2) & _GEN_1 ? 3'h7 - : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_0 = (wrbypass_data_valid - ? ~((&_wrbypass_io_WIRE_2) & _GEN_1 | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1) - : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_11 = + ? ~((&_wrbypass_io_T_6) & _GEN_1 | _wrbypass_io_T_6 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_28 = (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_1 = (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_0_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 - wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] + wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_1_ctr = _GEN_7 ? (_GEN_5 ? 3'h4 : 3'h3) : wrbypass_data_valid_1 - ? ((&_wrbypass_io_WIRE_11) & _GEN_5 + ? ((&_wrbypass_io_T_28) & _GEN_5 ? 3'h7 - : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 - ? 3'(_wrbypass_io_WIRE_11 + 3'h1) - : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) : (&_GEN_6) & _GEN_5 ? 3'h7 : _GEN_6 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_1 = (wrbypass_data_valid_1 - ? ~((&_wrbypass_io_WIRE_11) & _GEN_5 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5) - : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_20 = + ? ~((&_wrbypass_io_T_28) & _GEN_5 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_50 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_2 = (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] & _bank_wrbypasses_1_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_0_ctr = _GEN_4 ? (_GEN_1 ? 3'h4 : 3'h3) : wrbypass_data_valid_2 - ? ((&_wrbypass_io_WIRE_20) & _GEN_1 + ? ((&_wrbypass_io_T_50) & _GEN_1 ? 3'h7 - : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1 + : _wrbypass_io_T_50 == 3'h0 & ~_GEN_1 ? 3'h0 - : _GEN_1 - ? 3'(_wrbypass_io_WIRE_20 + 3'h1) - : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) : (&_GEN_2) & _GEN_1 ? 3'h7 - : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_0 = (wrbypass_data_valid_2 - ? ~((&_wrbypass_io_WIRE_20) & _GEN_1 | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1) - : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_29 = + ? ~((&_wrbypass_io_T_50) & _GEN_1 | _wrbypass_io_T_50 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_72 = (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_3 = (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_1_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_1_ctr = _GEN_7 ? (_GEN_5 ? 3'h4 : 3'h3) : wrbypass_data_valid_3 - ? ((&_wrbypass_io_WIRE_29) & _GEN_5 + ? ((&_wrbypass_io_T_72) & _GEN_5 ? 3'h7 - : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 - ? 3'(_wrbypass_io_WIRE_29 + 3'h1) - : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) : (&_GEN_6) & _GEN_5 ? 3'h7 : _GEN_6 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_1 = (wrbypass_data_valid_3 - ? ~((&_wrbypass_io_WIRE_29) & _GEN_5 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5) - : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_38 = + ? ~((&_wrbypass_io_T_72) & _GEN_5 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_94 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_4 = (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] & _bank_wrbypasses_2_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_0_ctr = _GEN_4 ? (_GEN_1 ? 3'h4 : 3'h3) : wrbypass_data_valid_4 - ? ((&_wrbypass_io_WIRE_38) & _GEN_1 + ? ((&_wrbypass_io_T_94) & _GEN_1 ? 3'h7 - : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1 + : _wrbypass_io_T_94 == 3'h0 & ~_GEN_1 ? 3'h0 - : _GEN_1 - ? 3'(_wrbypass_io_WIRE_38 + 3'h1) - : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) : (&_GEN_2) & _GEN_1 ? 3'h7 - : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_0 = (wrbypass_data_valid_4 - ? ~((&_wrbypass_io_WIRE_38) & _GEN_1 | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1) - : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_47 = + ? ~((&_wrbypass_io_T_94) & _GEN_1 | _wrbypass_io_T_94 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_116 = (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_5 = (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_2_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_1_ctr = _GEN_7 ? (_GEN_5 ? 3'h4 : 3'h3) : wrbypass_data_valid_5 - ? ((&_wrbypass_io_WIRE_47) & _GEN_5 + ? ((&_wrbypass_io_T_116) & _GEN_5 ? 3'h7 - : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_5 ? 3'h0 : _GEN_5 - ? 3'(_wrbypass_io_WIRE_47 + 3'h1) - : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) : (&_GEN_6) & _GEN_5 ? 3'h7 : _GEN_6 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_1 = (wrbypass_data_valid_5 - ? ~((&_wrbypass_io_WIRE_47) & _GEN_5 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5) - : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_56 = + ? ~((&_wrbypass_io_T_116) & _GEN_5 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_138 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_6 = (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] & _bank_wrbypasses_3_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_0_ctr = _GEN_4 ? (_GEN_1 ? 3'h4 : 3'h3) : wrbypass_data_valid_6 - ? ((&_wrbypass_io_WIRE_56) & _GEN_1 + ? ((&_wrbypass_io_T_138) & _GEN_1 ? 3'h7 - : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1 + : _wrbypass_io_T_138 == 3'h0 & ~_GEN_1 ? 3'h0 : _GEN_1 - ? 3'(_wrbypass_io_WIRE_56 + 3'h1) - : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + ? 3'(_wrbypass_io_T_138 + 3'h1) + : 3'(_wrbypass_io_T_138 - 3'h1)) : (&_GEN_2) & _GEN_1 ? 3'h7 - : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_0 = (wrbypass_data_valid_6 - ? ~((&_wrbypass_io_WIRE_56) & _GEN_1 | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1) - : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_65 = + ? ~((&_wrbypass_io_T_138) & _GEN_1 | _wrbypass_io_T_138 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_160 = (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_7 = (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_3_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_1_ctr = _GEN_7 ? (_GEN_5 ? 3'h4 : 3'h3) : wrbypass_data_valid_7 - ? ((&_wrbypass_io_WIRE_65) & _GEN_5 + ? ((&_wrbypass_io_T_160) & _GEN_5 ? 3'h7 - : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_5 ? 3'h0 : _GEN_5 - ? 3'(_wrbypass_io_WIRE_65 + 3'h1) - : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) : (&_GEN_6) & _GEN_5 ? 3'h7 : _GEN_6 == 3'h0 & ~_GEN_5 ? 3'h0 - : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_1 = (wrbypass_data_valid_7 - ? ~((&_wrbypass_io_WIRE_65) & _GEN_5 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5) - : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - always @(posedge clock) begin - if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 - s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 - s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}, :332:25 - s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_3 <= &(_GEN[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + ? ~((&_wrbypass_io_T_160) & _GEN_5 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (_s1_bank_req_1h_T) begin // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + s1_unhashed_idx <= io_req_bits_pc[40:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34] + s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}, :332:25] + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_3 <= &(_GEN[1:0]); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33] end - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] end end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) - powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 - else + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] powerOnResetState <= ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready - & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + & _table_banks_3_io_r_req_ready) & powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23] end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + logic [31:0] _RANDOM[0:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 - s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 - s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + _RANDOM[i[1:0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + end // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34] + s1_tag = _RANDOM[2'h1][26:19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25] + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + powerOnResetState = _RANDOM[2'h3][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + FoldedSRAMTemplate us ( // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] .clock (clock), .reset (reset), .io_r_req_ready (_us_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 - .io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + .io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38}] .io_r_resp_data_0 (_us_io_r_resp_data_0), .io_r_resp_data_1 (_us_io_r_resp_data_1), - .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 - .io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38} + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82, :426:{45,72}] + .io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38}] .io_w_req_bits_data_0 - (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48] .io_w_req_bits_data_1 - (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43] .io_w_req_bits_waymask ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, - ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 - .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7] + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:311:{51,56,82}] ); - FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_0_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_1_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_2 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_2_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_3 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_3_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 - .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52] + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx_in_bank), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) ); - assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_req_ready = ~powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19] assign io_resps_0_valid = - ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_ctr = - (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) - | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_u = ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34] assign io_resps_0_bits_unconf = - ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_valid = - s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] assign io_resps_1_bits_ctr = - (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) - | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_bits_u = s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34] assign io_resps_1_bits_unconf = - s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] endmodule diff --git a/rtl/TageSC/TageTable_1.sv b/rtl/TageSC/TageTable_1.sv index 335fb19..05e02a3 100644 --- a/rtl/TageSC/TageTable_1.sv +++ b/rtl/TageSC/TageTable_1.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,134 +55,135 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module TageTable_1( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - input clock, - input reset, - output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_req_bits_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_req_bits_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_update_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_update_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +module TageTable_1( // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_req_bits_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_req_bits_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_0_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_1_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_update_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_update_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_update_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] ); - wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 - reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 - reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - wire [2:0] _resp_selected_WIRE_1 = + wire per_bank_not_silent_update_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + reg powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:399:34] + wire _resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _bank_wrbypasses_3_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _table_banks_3_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _us_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82] + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19] + reg [39:0] s1_unhashed_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:330:34] + reg [7:0] s1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:332:25] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + wire [2:0] _resp_selected_T_6 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire [2:0] _resp_selected_WIRE_5 = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire [2:0] _resp_selected_T_27 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire _unconf_selected_WIRE = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire _unconf_selected_T_6 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 @@ -191,8 +192,8 @@ module TageTable_1( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _unconf_selected_WIRE_1 = + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _unconf_selected_T_13 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 @@ -201,565 +202,553 @@ module TageTable_1( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _hit_selected_WIRE = + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _hit_selected_T_6 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag - & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag - & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag - & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag - & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - wire _hit_selected_WIRE_1 = + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + wire _hit_selected_T_13 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag - & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag - & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag - & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag - & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - assign _resp_invalid_by_write_WIRE = + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + assign _resp_invalid_by_write_T_6 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 - | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 - wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire [7:0] per_bank_update_wdata_3_1_tag = + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48] + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire [7:0] update_tag = io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist - ^ {io_update_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 - wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + ^ {io_update_folded_hist_hist_15_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43] + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] wire [1:0] per_bank_update_way_mask_0 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_0_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_0_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_1 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_1_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_1_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_2 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_2_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_2_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_3 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_3_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_3_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire _s1_bank_has_write_on_this_req_WIRE_0 = - (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_1 = - (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_2 = - (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_3 = - (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} - wire [2:0] _wrbypass_io_WIRE_2 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}] + wire [2:0] _wrbypass_io_T_6 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid = (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] & _bank_wrbypasses_0_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 - wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 - wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_1 = (|_GEN_0) | _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :98:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14] + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid - ? ((&_wrbypass_io_WIRE_2) & _GEN + ? ((&_wrbypass_io_T_6) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + : _wrbypass_io_T_6 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_2 + 3'h1) - : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_0 = (wrbypass_data_valid - ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_11 = + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_28 = (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_1 = (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_0_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 - wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_1 - ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? ((&_wrbypass_io_T_28) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_11 + 3'h1) - : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_1 = (wrbypass_data_valid_1 - ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_20 = + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_50 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_2 = (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] & _bank_wrbypasses_1_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_2 - ? ((&_wrbypass_io_WIRE_20) & _GEN + ? ((&_wrbypass_io_T_50) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + : _wrbypass_io_T_50 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_20 + 3'h1) - : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_0 = (wrbypass_data_valid_2 - ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_29 = + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_72 = (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_3 = (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_1_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_3 - ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_29 + 3'h1) - : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_1 = (wrbypass_data_valid_3 - ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_38 = + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_94 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_4 = (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] & _bank_wrbypasses_2_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_4 - ? ((&_wrbypass_io_WIRE_38) & _GEN + ? ((&_wrbypass_io_T_94) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + : _wrbypass_io_T_94 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_38 + 3'h1) - : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_0 = (wrbypass_data_valid_4 - ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_47 = + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_116 = (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_5 = (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_2_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_5 - ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? ((&_wrbypass_io_T_116) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_47 + 3'h1) - : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_1 = (wrbypass_data_valid_5 - ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_56 = + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_138 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_6 = (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] & _bank_wrbypasses_3_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_6 - ? ((&_wrbypass_io_WIRE_56) & _GEN + ? ((&_wrbypass_io_T_138) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + : _wrbypass_io_T_138 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_56 + 3'h1) - : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_0 = (wrbypass_data_valid_6 - ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_65 = + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_160 = (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_7 = (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_3_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_7 - ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? ((&_wrbypass_io_T_160) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_65 + 3'h1) - : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_1 = (wrbypass_data_valid_7 - ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - always @(posedge clock) begin - if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 - s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (_s1_bank_req_1h_T) begin // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + s1_unhashed_idx <= io_req_bits_pc[40:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34] s1_tag <= io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist - ^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 - s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + ^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25] + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33] end - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] end end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) - powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 - else + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] powerOnResetState <= ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready - & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + & _table_banks_3_io_r_req_ready) & powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23] end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + logic [31:0] _RANDOM[0:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 - s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 - s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + _RANDOM[i[1:0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + end // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34] + s1_tag = _RANDOM[2'h1][26:19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25] + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + powerOnResetState = _RANDOM[2'h3][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + FoldedSRAMTemplate us ( // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] .clock (clock), .reset (reset), .io_r_req_ready (_us_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 - .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_req_valid (_s1_bank_req_1h_T), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + .io_r_req_bits_setIdx (s0_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_r_resp_data_0 (_us_io_r_resp_data_0), .io_r_resp_data_1 (_us_io_r_resp_data_1), - .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82, :426:{45,72}] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_w_req_bits_data_0 - (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48] .io_w_req_bits_data_1 - (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43] .io_w_req_bits_waymask ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, - ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 - .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7] + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:311:{51,56,82}] ); - FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_0_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_1_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_2 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_2_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_3 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_3_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) ); - assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_req_ready = ~powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19] assign io_resps_0_valid = - ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_ctr = - (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) - | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_u = ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34] assign io_resps_0_bits_unconf = - ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_valid = - s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] assign io_resps_1_bits_ctr = - (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) - | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_bits_u = s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34] assign io_resps_1_bits_unconf = - s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] endmodule diff --git a/rtl/TageSC/TageTable_2.sv b/rtl/TageSC/TageTable_2.sv index 7e43a07..1dc0376 100644 --- a/rtl/TageSC/TageTable_2.sv +++ b/rtl/TageSC/TageTable_2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,134 +55,135 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module TageTable_2( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - input clock, - input reset, - output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_req_bits_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_req_bits_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_update_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_update_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +module TageTable_2( // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_req_bits_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_req_bits_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_0_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_1_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_update_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_update_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_update_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] ); - wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 - reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 - reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - wire [2:0] _resp_selected_WIRE_1 = + wire per_bank_not_silent_update_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + reg powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:399:34] + wire _resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _bank_wrbypasses_3_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _table_banks_3_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _us_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82] + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19] + reg [39:0] s1_unhashed_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:330:34] + reg [7:0] s1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:332:25] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + wire [2:0] _resp_selected_T_6 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire [2:0] _resp_selected_WIRE_5 = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire [2:0] _resp_selected_T_27 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire _unconf_selected_WIRE = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire _unconf_selected_T_6 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 @@ -191,8 +192,8 @@ module TageTable_2( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _unconf_selected_WIRE_1 = + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _unconf_selected_T_13 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 @@ -201,565 +202,553 @@ module TageTable_2( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _hit_selected_WIRE = + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _hit_selected_T_6 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag - & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag - & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag - & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag - & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - wire _hit_selected_WIRE_1 = + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + wire _hit_selected_T_13 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag - & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag - & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag - & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag - & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - assign _resp_invalid_by_write_WIRE = + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + assign _resp_invalid_by_write_T_6 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 - | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 - wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire [7:0] per_bank_update_wdata_3_1_tag = + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48] + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire [7:0] update_tag = io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist - ^ {io_update_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 - wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + ^ {io_update_folded_hist_hist_9_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43] + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] wire [1:0] per_bank_update_way_mask_0 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_0_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_0_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_1 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_1_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_1_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_2 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_2_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_2_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_3 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_3_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_3_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire _s1_bank_has_write_on_this_req_WIRE_0 = - (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_1 = - (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_2 = - (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_3 = - (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} - wire [2:0] _wrbypass_io_WIRE_2 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}] + wire [2:0] _wrbypass_io_T_6 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid = (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] & _bank_wrbypasses_0_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 - wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 - wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_1 = (|_GEN_0) | _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :98:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14] + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid - ? ((&_wrbypass_io_WIRE_2) & _GEN + ? ((&_wrbypass_io_T_6) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + : _wrbypass_io_T_6 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_2 + 3'h1) - : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_0 = (wrbypass_data_valid - ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_11 = + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_28 = (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_1 = (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_0_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 - wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_1 - ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? ((&_wrbypass_io_T_28) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_11 + 3'h1) - : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_1 = (wrbypass_data_valid_1 - ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_20 = + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_50 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_2 = (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] & _bank_wrbypasses_1_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_2 - ? ((&_wrbypass_io_WIRE_20) & _GEN + ? ((&_wrbypass_io_T_50) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + : _wrbypass_io_T_50 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_20 + 3'h1) - : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_0 = (wrbypass_data_valid_2 - ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_29 = + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_72 = (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_3 = (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_1_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_3 - ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_29 + 3'h1) - : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_1 = (wrbypass_data_valid_3 - ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_38 = + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_94 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_4 = (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] & _bank_wrbypasses_2_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_4 - ? ((&_wrbypass_io_WIRE_38) & _GEN + ? ((&_wrbypass_io_T_94) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + : _wrbypass_io_T_94 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_38 + 3'h1) - : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_0 = (wrbypass_data_valid_4 - ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_47 = + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_116 = (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_5 = (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_2_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_5 - ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? ((&_wrbypass_io_T_116) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_47 + 3'h1) - : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_1 = (wrbypass_data_valid_5 - ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_56 = + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_138 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_6 = (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] & _bank_wrbypasses_3_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_6 - ? ((&_wrbypass_io_WIRE_56) & _GEN + ? ((&_wrbypass_io_T_138) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + : _wrbypass_io_T_138 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_56 + 3'h1) - : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_0 = (wrbypass_data_valid_6 - ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_65 = + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_160 = (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_7 = (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_3_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_7 - ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? ((&_wrbypass_io_T_160) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_65 + 3'h1) - : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_1 = (wrbypass_data_valid_7 - ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - always @(posedge clock) begin - if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 - s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (_s1_bank_req_1h_T) begin // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + s1_unhashed_idx <= io_req_bits_pc[40:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34] s1_tag <= io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist - ^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 - s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + ^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25] + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33] end - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] end end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) - powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 - else + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] powerOnResetState <= ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready - & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + & _table_banks_3_io_r_req_ready) & powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23] end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + logic [31:0] _RANDOM[0:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 - s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 - s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + _RANDOM[i[1:0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + end // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34] + s1_tag = _RANDOM[2'h1][26:19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25] + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + powerOnResetState = _RANDOM[2'h3][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + FoldedSRAMTemplate us ( // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] .clock (clock), .reset (reset), .io_r_req_ready (_us_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 - .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_req_valid (_s1_bank_req_1h_T), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + .io_r_req_bits_setIdx (s0_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_r_resp_data_0 (_us_io_r_resp_data_0), .io_r_resp_data_1 (_us_io_r_resp_data_1), - .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82, :426:{45,72}] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_w_req_bits_data_0 - (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48] .io_w_req_bits_data_1 - (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43] .io_w_req_bits_waymask ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, - ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 - .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7] + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:311:{51,56,82}] ); - FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_0_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_1_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_2 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_2_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_3 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_3_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) ); - assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_req_ready = ~powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19] assign io_resps_0_valid = - ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_ctr = - (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) - | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_u = ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34] assign io_resps_0_bits_unconf = - ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_valid = - s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] assign io_resps_1_bits_ctr = - (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) - | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_bits_u = s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34] assign io_resps_1_bits_unconf = - s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] endmodule diff --git a/rtl/TageSC/TageTable_3.sv b/rtl/TageSC/TageTable_3.sv index f4f795f..c01b20c 100644 --- a/rtl/TageSC/TageTable_3.sv +++ b/rtl/TageSC/TageTable_3.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,134 +55,135 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module TageTable_3( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - input clock, - input reset, - output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_req_bits_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_req_bits_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_req_bits_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [10:0] io_update_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [7:0] io_update_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [6:0] io_update_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +module TageTable_3( // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_req_bits_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_req_bits_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_req_bits_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_0_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_0_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output [2:0] io_resps_1_bits_ctr, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_u, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + output io_resps_1_bits_unconf, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [10:0] io_update_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [7:0] io_update_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [6:0] io_update_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_takens_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_alloc_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input [2:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_uMask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_us_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + input io_update_reset_u_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] ); - wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 - reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 - wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 - wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 - wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 - wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 - reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 - reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 - reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 - reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 - wire [2:0] _resp_selected_WIRE_1 = + wire per_bank_not_silent_update_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + wire per_bank_not_silent_update_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:458:81] + reg powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:399:34] + wire _resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _bank_wrbypasses_3_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] + wire _table_banks_3_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_3_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_2_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_1_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _table_banks_0_io_r_resp_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] + wire _us_io_r_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82] + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19] + reg [39:0] s1_unhashed_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:330:34] + reg [7:0] s1_tag; // @[src/main/scala/xiangshan/frontend/Tage.scala:332:25] + reg s1_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_req_1h_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:334:33] + reg s1_bank_has_write_on_this_req_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + reg s1_bank_has_write_on_this_req_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48] + wire [2:0] _resp_selected_T_6 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire [2:0] _resp_selected_WIRE_5 = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire [2:0] _resp_selected_T_27 = (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) - | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 - wire _unconf_selected_WIRE = + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33] + wire _unconf_selected_T_6 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 @@ -191,8 +192,8 @@ module TageTable_3( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _unconf_selected_WIRE_1 = + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _unconf_selected_T_13 = s1_bank_req_1h_0 & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 @@ -201,565 +202,553 @@ module TageTable_3( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 - | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 - wire _hit_selected_WIRE = + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14] + wire _hit_selected_T_6 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag - & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag - & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag - & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag - & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - wire _hit_selected_WIRE_1 = + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + wire _hit_selected_T_13 = s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag - & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag - & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag - & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag - & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} - assign _resp_invalid_by_write_WIRE = + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}] + assign _resp_invalid_by_write_T_6 = s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 - | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 - wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 - wire [7:0] per_bank_update_wdata_3_1_tag = + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48] + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43] + wire [7:0] update_tag = io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist - ^ {io_update_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 - wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} - wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + ^ {io_update_folded_hist_hist_5_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43] + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}] wire [1:0] per_bank_update_way_mask_0 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_0_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_0_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_1 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_1_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_1_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_2 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_2_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_2_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire [1:0] per_bank_update_way_mask_3 = {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) & per_bank_not_silent_update_3_1, (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) - & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + & per_bank_not_silent_update_3_0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81] wire _s1_bank_has_write_on_this_req_WIRE_0 = - (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_1 = - (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_2 = - (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}] wire _s1_bank_has_write_on_this_req_WIRE_3 = - (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} - wire [2:0] _wrbypass_io_WIRE_2 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}] + wire [2:0] _wrbypass_io_T_6 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid = (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] & _bank_wrbypasses_0_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 - wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 - wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_1 = (|_GEN_0) | _GEN; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :98:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14] + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid - ? ((&_wrbypass_io_WIRE_2) & _GEN + ? ((&_wrbypass_io_T_6) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + : _wrbypass_io_T_6 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_2 + 3'h1) - : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_0 = (wrbypass_data_valid - ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_11 = + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_28 = (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_1 = (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_0_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 - wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 - wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 - wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14] + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43] + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12] wire [2:0] per_bank_update_wdata_0_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_1 - ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? ((&_wrbypass_io_T_28) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_11 + 3'h1) - : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_0_1 = (wrbypass_data_valid_1 - ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_20 = + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_50 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_2 = (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] & _bank_wrbypasses_1_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_2 - ? ((&_wrbypass_io_WIRE_20) & _GEN + ? ((&_wrbypass_io_T_50) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + : _wrbypass_io_T_50 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_20 + 3'h1) - : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_0 = (wrbypass_data_valid_2 - ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_29 = + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_72 = (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_3 = (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_1_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_1_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_3 - ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 - ? 3'(_wrbypass_io_WIRE_29 + 3'h1) - : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_1_1 = (wrbypass_data_valid_3 - ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_38 = + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_94 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_4 = (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] & _bank_wrbypasses_2_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_4 - ? ((&_wrbypass_io_WIRE_38) & _GEN + ? ((&_wrbypass_io_T_94) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + : _wrbypass_io_T_94 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_38 + 3'h1) - : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_0 = (wrbypass_data_valid_4 - ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_47 = + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_116 = (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_5 = (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_2_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_2_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_5 - ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? ((&_wrbypass_io_T_116) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_47 + 3'h1) - : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_2_1 = (wrbypass_data_valid_5 - ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_56 = + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_138 = (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) - | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_6 = (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] & _bank_wrbypasses_3_1_io_hit) & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_0_ctr = _GEN_2 ? (_GEN ? 3'h4 : 3'h3) : wrbypass_data_valid_6 - ? ((&_wrbypass_io_WIRE_56) & _GEN + ? ((&_wrbypass_io_T_138) & _GEN ? 3'h7 - : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + : _wrbypass_io_T_138 == 3'h0 & ~_GEN ? 3'h0 - : _GEN - ? 3'(_wrbypass_io_WIRE_56 + 3'h1) - : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) : (&_GEN_0) & _GEN ? 3'h7 - : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_0 = (wrbypass_data_valid_6 - ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) - : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - wire [2:0] _wrbypass_io_WIRE_65 = + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + wire [2:0] _wrbypass_io_T_160 = (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) - | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11] wire wrbypass_data_valid_7 = (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) & _bank_wrbypasses_3_1_io_hit) & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) - & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46] wire [2:0] per_bank_update_wdata_3_1_ctr = _GEN_5 ? (_GEN_3 ? 3'h4 : 3'h3) : wrbypass_data_valid_7 - ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? ((&_wrbypass_io_T_160) & _GEN_3 ? 3'h7 - : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 ? 3'h0 : _GEN_3 - ? 3'(_wrbypass_io_WIRE_65 + 3'h1) - : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) : (&_GEN_4) & _GEN_3 ? 3'h7 : _GEN_4 == 3'h0 & ~_GEN_3 ? 3'h0 - : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :96:30, :97:{8,21}, :98:{10,26,29}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14] assign per_bank_not_silent_update_3_1 = (wrbypass_data_valid_7 - ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) - : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} - always @(posedge clock) begin - if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 - s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :98:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (_s1_bank_req_1h_T) begin // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + s1_unhashed_idx <= io_req_bits_pc[40:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34] s1_tag <= io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist - ^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 - s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 - s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + ^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0}; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25] + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33] + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33] end - if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 - s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 - s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + if (io_req_valid) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:245:14] + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49] end end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) - powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 - else + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] powerOnResetState <= ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready - & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + & _table_banks_3_io_r_req_ready) & powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23] end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + logic [31:0] _RANDOM[0:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 - s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 - s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 - s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 - powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + _RANDOM[i[1:0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + end // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34] + s1_tag = _RANDOM[2'h1][26:19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25] + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33] + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48] + powerOnResetState = _RANDOM[2'h3][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + if (reset) // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + powerOnResetState = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + FoldedSRAMTemplate us ( // @[src/main/scala/xiangshan/frontend/Tage.scala:310:18] .clock (clock), .reset (reset), .io_r_req_ready (_us_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 - .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_req_valid (_s1_bank_req_1h_T), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35] + .io_r_req_bits_setIdx (s0_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_r_resp_data_0 (_us_io_r_resp_data_0), .io_r_resp_data_1 (_us_io_r_resp_data_1), - .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 - .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), // @[src/main/scala/xiangshan/frontend/Tage.scala:311:82, :426:{45,72}] + .io_w_req_bits_setIdx (update_idx), // @[src/main/scala/xiangshan/frontend/Tage.scala:290:29] .io_w_req_bits_data_0 - (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48] .io_w_req_bits_data_1 - (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43] .io_w_req_bits_waymask ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, - ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 - .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7] + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:311:{51,56,82}] ); - FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_0_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_1_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_2 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_2_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + FoldedSRAMTemplate_1 table_banks_3 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:315:11] .clock (clock), .reset (reset), .io_r_req_ready (_table_banks_3_io_r_req_ready), - .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 - .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // @[src/main/scala/chisel3/util/Decoupled.scala:51:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52] + .io_r_req_bits_setIdx (s0_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), - .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 - .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} - .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 - .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 - .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // @[src/main/scala/xiangshan/frontend/Tage.scala:391:49] + .io_w_req_bits_setIdx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] + .io_w_req_bits_data_0_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_data_1_tag (update_tag), // @[src/main/scala/xiangshan/frontend/Tage.scala:291:38] + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // @[src/main/scala/xiangshan/frontend/Tage.scala:448:12] + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // @[src/main/scala/xiangshan/frontend/Tage.scala:384:11] ); - WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_0_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_0_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_1_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_1_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_2_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_2_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) - | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_0_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) ); - WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + WrBypass bank_wrbypasses_3_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:434:11] .clock (clock), .reset (reset), - .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 - .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // @[src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45] + .io_write_idx (update_idx[10:2]), // @[src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}] .io_write_data_0 ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) - | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12] .io_hit (_bank_wrbypasses_3_1_io_hit), .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) ); - assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_req_ready = ~powerOnResetState; // @[src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19] assign io_resps_0_valid = - ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_ctr = - (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) - | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_0_bits_u = ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34] assign io_resps_0_bits_unconf = - ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_valid = - s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) - & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] assign io_resps_1_bits_ctr = - (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) - | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34] assign io_resps_1_bits_u = s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) - & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + & _us_io_r_resp_data_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34] assign io_resps_1_bits_unconf = - s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) - & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34] endmodule diff --git a/rtl/TageSC/Tage_SC.sv b/rtl/TageSC/Tage_SC.sv index a4932a3..64ac4b5 100644 --- a/rtl/TageSC/Tage_SC.sv +++ b/rtl/TageSC/Tage_SC.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,714 +55,723 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - input clock, - input reset, - input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [218:0] io_update_bits_meta // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module Tage_SC( // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_tage_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_sc_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_s1_ready, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [5:0] io_perf_0_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_1_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_2_value // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] ); - reg [5:0] r_1_3; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_1_2; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_1_1; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_1_0; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg resp_meta_scMeta_scPreds_1_r; // src/main/scala/xiangshan/frontend/SC.scala:298:40 - reg resp_meta_scMeta_scUsed_1_r; // src/main/scala/xiangshan/frontend/SC.scala:297:40 - reg resp_meta_scMeta_tageTakens_1_r; // src/main/scala/xiangshan/frontend/SC.scala:296:40 - reg [5:0] r_3; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_2; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_1; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg [5:0] r_0; // src/main/scala/xiangshan/frontend/SC.scala:299:40 - reg resp_meta_scMeta_scPreds_0_r; // src/main/scala/xiangshan/frontend/SC.scala:298:40 - reg resp_meta_scMeta_scUsed_0_r; // src/main/scala/xiangshan/frontend/SC.scala:297:40 - reg resp_meta_scMeta_tageTakens_0_r; // src/main/scala/xiangshan/frontend/SC.scala:296:40 - reg [1:0] resp_meta_basecnts_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:703:41 - reg resp_meta_takens_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:702:41 - reg resp_meta_altDiffers_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:700:41 - reg resp_meta_altUsed_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:699:41 - reg [3:0] resp_meta_allocates_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:686:40 - reg resp_meta_providerResps_1_r_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg resp_meta_providerResps_1_r_u; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg [2:0] resp_meta_providerResps_1_r_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg [1:0] resp_meta_providers_1_bits_r; // src/main/scala/xiangshan/frontend/Tage.scala:668:49 - reg resp_meta_providers_1_valid_r; // src/main/scala/xiangshan/frontend/Tage.scala:667:49 - reg [1:0] resp_meta_basecnts_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:703:41 - reg resp_meta_takens_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:702:41 - reg resp_meta_altDiffers_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:700:41 - reg resp_meta_altUsed_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:699:41 - reg [3:0] resp_meta_allocates_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:686:40 - reg resp_meta_providerResps_0_r_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg resp_meta_providerResps_0_r_u; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg [2:0] resp_meta_providerResps_0_r_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 - reg [1:0] resp_meta_providers_0_bits_r; // src/main/scala/xiangshan/frontend/Tage.scala:668:49 - reg resp_meta_providers_0_valid_r; // src/main/scala/xiangshan/frontend/Tage.scala:667:49 - wire [5:0] _scTables_3_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_3_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_3_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_3_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_2_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_2_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_2_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_2_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_1_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_1_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_1_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_1_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_0_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_0_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_0_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire [5:0] _scTables_0_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 - wire _bt_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 - wire [1:0] _bt_io_s1_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 - wire [1:0] _bt_io_s1_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 - wire _tables_3_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_3_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_3_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_3_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_2_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_2_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_2_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_1_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_1_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_1_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_0_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [2:0] _tables_0_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire _tables_0_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 - wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - reg [6:0] bankTickCtrDistanceToTops_0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - reg [6:0] bankTickCtrDistanceToTops_1; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - reg [6:0] bankTickCtrs_0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - reg [6:0] bankTickCtrs_1; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - reg [3:0] useAltOnNaCtrs_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_2; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_3; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_4; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_5; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_6; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_7; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_9; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_10; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_11; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_12; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_13; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_14; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_15; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_16; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_17; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_18; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_19; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_20; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_21; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_22; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_23; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_24; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_25; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_26; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_27; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_28; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_29; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_30; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_31; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_32; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_33; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_34; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_35; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_36; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_37; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_38; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_39; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_40; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_41; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_42; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_43; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_44; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_45; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_46; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_47; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_48; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_49; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_50; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_51; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_52; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_53; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_54; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_55; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_56; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_57; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_58; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_59; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_60; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_61; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_62; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_63; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_64; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_65; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_66; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_67; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_68; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_69; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_70; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_71; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_72; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_73; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_74; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_75; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_76; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_77; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_78; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_79; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_80; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_81; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_82; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_83; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_84; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_85; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_86; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_87; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_88; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_89; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_90; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_91; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_92; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_93; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_94; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_95; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_96; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_97; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_98; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_99; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_100; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_101; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_102; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_103; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_104; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_105; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_106; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_107; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_108; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_109; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_110; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_111; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_112; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_113; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_114; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_115; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_116; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_117; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_118; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_119; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_120; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_121; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_122; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_123; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_124; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_125; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_126; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_0_127; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_2; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_3; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_4; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_5; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_6; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_7; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_9; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_10; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_11; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_12; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_13; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_14; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_15; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_16; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_17; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_18; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_19; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_20; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_21; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_22; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_23; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_24; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_25; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_26; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_27; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_28; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_29; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_30; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_31; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_32; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_33; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_34; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_35; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_36; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_37; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_38; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_39; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_40; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_41; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_42; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_43; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_44; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_45; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_46; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_47; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_48; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_49; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_50; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_51; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_52; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_53; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_54; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_55; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_56; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_57; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_58; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_59; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_60; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_61; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_62; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_63; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_64; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_65; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_66; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_67; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_68; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_69; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_70; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_71; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_72; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_73; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_74; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_75; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_76; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_77; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_78; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_79; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_80; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_81; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_82; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_83; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_84; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_85; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_86; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_87; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_88; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_89; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_90; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_91; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_92; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_93; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_94; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_95; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_96; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_97; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_98; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_99; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_100; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_101; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_102; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_103; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_104; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_105; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_106; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_107; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_108; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_109; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_110; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_111; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_112; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_113; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_114; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_115; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_116; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_117; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_118; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_119; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_120; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_121; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_122; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_123; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_124; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_125; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_126; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg [3:0] useAltOnNaCtrs_1_127; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 - reg s2_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38 - reg s2_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38 - reg [1:0] s2_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38 - reg [1:0] s2_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38 - reg [2:0] s2_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg s2_providerResps_0_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg s2_providerResps_0_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg [2:0] s2_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg s2_providerResps_1_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg s2_providerResps_1_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 - reg s2_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38 - reg s2_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38 - reg s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 - reg s2_finalAltPreds_0; // src/main/scala/xiangshan/frontend/Tage.scala:601:38 - reg s2_finalAltPreds_1; // src/main/scala/xiangshan/frontend/Tage.scala:601:38 - reg [1:0] s2_basecnts_0; // src/main/scala/xiangshan/frontend/Tage.scala:602:38 - reg [1:0] s2_basecnts_1; // src/main/scala/xiangshan/frontend/Tage.scala:602:38 + reg [5:0] r_3_3; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_3_2; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_3_1; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_3_0; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg resp_meta_scMeta_scPreds_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:298:40] + reg resp_meta_scMeta_scUsed_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:297:40] + reg resp_meta_scMeta_tageTakens_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40] + reg [5:0] r_2_3; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_2_2; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_2_1; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg [5:0] r_2_0; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40] + reg resp_meta_scMeta_scPreds_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:298:40] + reg resp_meta_scMeta_scUsed_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:297:40] + reg resp_meta_scMeta_tageTakens_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40] + reg [1:0] resp_meta_basecnts_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:703:41] + reg resp_meta_takens_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:702:41] + reg resp_meta_altDiffers_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:700:41] + reg resp_meta_altUsed_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:699:41] + reg [3:0] resp_meta_allocates_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40] + reg resp_meta_providerResps_1_r_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg resp_meta_providerResps_1_r_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg [2:0] resp_meta_providerResps_1_r_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg [1:0] resp_meta_providers_1_bits_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49] + reg resp_meta_providers_1_valid_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:667:49] + reg [1:0] resp_meta_basecnts_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:703:41] + reg resp_meta_takens_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:702:41] + reg resp_meta_altDiffers_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:700:41] + reg resp_meta_altUsed_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:699:41] + reg [3:0] resp_meta_allocates_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40] + reg resp_meta_providerResps_0_r_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg resp_meta_providerResps_0_r_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg [2:0] resp_meta_providerResps_0_r_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49] + reg [1:0] resp_meta_providers_0_bits_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49] + reg resp_meta_providers_0_valid_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:667:49] + wire [5:0] _scTables_3_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_3_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_3_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_3_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_2_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_2_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_2_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_2_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_1_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_1_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_1_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_1_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_0_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_0_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_0_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire [5:0] _scTables_0_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] + wire _bt_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19] + wire [1:0] _bt_io_s1_cnt_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19] + wire [1:0] _bt_io_s1_cnt_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19] + wire _tables_3_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_3_io_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_0_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_3_io_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_3_io_resps_1_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_2_io_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_0_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_2_io_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_2_io_resps_1_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_1_io_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_0_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_1_io_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_1_io_resps_1_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_0_io_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_0_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [2:0] _tables_0_io_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire _tables_0_io_resps_1_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] + wire [35:0] _reset_vector_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + reg [40:0] s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + reg REG_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + reg [6:0] bankTickCtrDistanceToTops_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + reg [6:0] bankTickCtrDistanceToTops_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + reg [6:0] bankTickCtrs_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + reg [6:0] bankTickCtrs_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + reg [3:0] useAltOnNaCtrs_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_4; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_5; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_6; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_7; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_9; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_10; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_11; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_12; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_13; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_14; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_15; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_16; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_17; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_18; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_19; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_20; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_21; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_22; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_23; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_24; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_25; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_26; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_27; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_28; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_29; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_30; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_31; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_32; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_33; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_34; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_35; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_36; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_37; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_38; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_39; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_40; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_41; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_42; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_43; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_44; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_45; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_46; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_47; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_48; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_49; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_50; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_51; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_52; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_53; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_54; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_55; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_56; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_57; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_58; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_59; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_60; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_61; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_62; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_63; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_64; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_65; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_66; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_67; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_68; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_69; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_70; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_71; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_72; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_73; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_74; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_75; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_76; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_77; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_78; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_79; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_80; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_81; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_82; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_83; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_84; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_85; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_86; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_87; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_88; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_89; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_90; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_91; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_92; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_93; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_94; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_95; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_96; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_97; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_98; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_99; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_100; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_101; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_102; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_103; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_104; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_105; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_106; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_107; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_108; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_109; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_110; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_111; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_112; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_113; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_114; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_115; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_116; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_117; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_118; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_119; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_120; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_121; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_122; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_123; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_124; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_125; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_126; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_0_127; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_4; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_5; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_6; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_7; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_9; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_10; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_11; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_12; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_13; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_14; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_15; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_16; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_17; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_18; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_19; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_20; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_21; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_22; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_23; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_24; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_25; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_26; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_27; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_28; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_29; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_30; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_31; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_32; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_33; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_34; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_35; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_36; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_37; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_38; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_39; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_40; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_41; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_42; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_43; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_44; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_45; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_46; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_47; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_48; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_49; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_50; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_51; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_52; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_53; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_54; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_55; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_56; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_57; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_58; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_59; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_60; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_61; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_62; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_63; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_64; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_65; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_66; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_67; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_68; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_69; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_70; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_71; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_72; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_73; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_74; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_75; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_76; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_77; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_78; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_79; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_80; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_81; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_82; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_83; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_84; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_85; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_86; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_87; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_88; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_89; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_90; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_91; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_92; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_93; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_94; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_95; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_96; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_97; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_98; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_99; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_100; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_101; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_102; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_103; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_104; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_105; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_106; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_107; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_108; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_109; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_110; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_111; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_112; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_113; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_114; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_115; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_116; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_117; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_118; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_119; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_120; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_121; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_122; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_123; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_124; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_125; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_126; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg [3:0] useAltOnNaCtrs_1_127; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31] + reg s2_provideds_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38] + reg s2_provideds_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38] + reg [1:0] s2_providers_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38] + reg [1:0] s2_providers_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38] + reg [2:0] s2_providerResps_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg s2_providerResps_0_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg s2_providerResps_0_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg [2:0] s2_providerResps_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg s2_providerResps_1_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg s2_providerResps_1_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38] + reg s2_altUsed_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38] + reg s2_altUsed_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38] + reg s2_tageTakens_dup_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_tageTakens_dup_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58] + reg s2_finalAltPreds_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:601:38] + reg s2_finalAltPreds_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:601:38] + reg [1:0] s2_basecnts_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:602:38] + reg [1:0] s2_basecnts_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:602:38] wire updateValids_0 = io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid - & ~io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:{47,50} + & ~io_update_bits_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:{47,50}] wire updateValids_1 = io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_tailSlot_sharing & io_update_valid & ~io_update_bits_ftb_entry_always_taken_1 - & ~io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:{50,84}, :615:7 - reg [3:0] allocatableSlots; // src/main/scala/xiangshan/frontend/Tage.scala:679:16 - reg tage_enable_dup_REG; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 - wire bUpdateTakens_0 = updateValids_0 & io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :715:33 - wire updateProviderCorrect = io_update_bits_meta[76] == bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71} + & ~io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:{50,84}, :615:7] + reg [3:0] allocatableSlots; // @[src/main/scala/xiangshan/frontend/Tage.scala:679:16] + reg tage_enable_dup_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:705:38] + wire updateTaken = updateValids_0 & io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :715:33] + wire updateProviderCorrect = io_update_bits_meta[76] == updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71}] wire needToAllocate = updateValids_0 & io_update_bits_mispred_mask_0 - & ~(io_update_bits_meta[70] & updateProviderCorrect & io_update_bits_meta[84]); // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :720:71, :770:{53,56,96} - reg [63:0] allocLFSR_lfsr; // utility/src/main/scala/utility/LFSR64.scala:27:33 - wire [3:0] _longerHistoryTableMask_T_1 = 4'h1 << io_update_bits_meta[83:82]; // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - wire [2:0] _GEN = _longerHistoryTableMask_T_1[2:0] | _longerHistoryTableMask_T_1[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + & ~(io_update_bits_meta[70] & updateProviderCorrect & io_update_bits_meta[84]); // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :720:71, :770:{53,56,96}] + reg [63:0] allocLFSR_lfsr; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + wire [3:0] _longerHistoryTableMask_T_1 = 4'h1 << io_update_bits_meta[83:82]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + wire [2:0] _GEN = _longerHistoryTableMask_T_1[2:0] | _longerHistoryTableMask_T_1[3:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire [3:0] longerHistoryTableMask = ~({&(io_update_bits_meta[83:82]), _GEN[2], _GEN[1] | (&(io_update_bits_meta[83:82])), _GEN[0] | io_update_bits_meta[83:82] == 2'h2 | (&(io_update_bits_meta[83:82]))} - & {4{io_update_bits_meta[84]}}); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 - wire _firstEntry_T = io_update_bits_meta[56] & longerHistoryTableMask[0]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - wire _firstEntry_T_1 = io_update_bits_meta[57] & longerHistoryTableMask[1]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - wire _firstEntry_T_2 = io_update_bits_meta[58] & longerHistoryTableMask[2]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - reg [3:0] allocatableSlots_1; // src/main/scala/xiangshan/frontend/Tage.scala:679:16 - reg tage_enable_dup_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 - wire bUpdateTakens_1 = updateValids_1 & io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :715:33 - wire updateProviderCorrect_1 = io_update_bits_meta[81] == bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71} + & {4{io_update_bits_meta[84]}}); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] + wire _firstEntry_T = io_update_bits_meta[56] & longerHistoryTableMask[0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + wire _firstEntry_T_1 = io_update_bits_meta[57] & longerHistoryTableMask[1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + wire _firstEntry_T_2 = io_update_bits_meta[58] & longerHistoryTableMask[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + reg [3:0] allocatableSlots_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:679:16] + reg tage_enable_dup_REG_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:705:38] + wire updateTaken_1 = updateValids_1 & io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :715:33] + wire updateProviderCorrect_1 = io_update_bits_meta[81] == updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71}] wire needToAllocate_1 = updateValids_1 & io_update_bits_mispred_mask_1 - & ~(io_update_bits_meta[71] & updateProviderCorrect_1 & io_update_bits_meta[87]); // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :720:71, :770:{53,56,96} - reg [63:0] allocLFSR_lfsr_1; // utility/src/main/scala/utility/LFSR64.scala:27:33 - wire [3:0] _longerHistoryTableMask_T_11 = 4'h1 << io_update_bits_meta[86:85]; // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + & ~(io_update_bits_meta[71] & updateProviderCorrect_1 & io_update_bits_meta[87]); // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :720:71, :770:{53,56,96}] + reg [63:0] allocLFSR_lfsr_1; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + wire [3:0] _longerHistoryTableMask_T_11 = 4'h1 << io_update_bits_meta[86:85]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40] wire [2:0] _GEN_0 = - _longerHistoryTableMask_T_11[2:0] | _longerHistoryTableMask_T_11[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + _longerHistoryTableMask_T_11[2:0] | _longerHistoryTableMask_T_11[3:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire [3:0] longerHistoryTableMask_1 = ~({&(io_update_bits_meta[86:85]), _GEN_0[2], _GEN_0[1] | (&(io_update_bits_meta[86:85])), _GEN_0[0] | io_update_bits_meta[86:85] == 2'h2 | (&(io_update_bits_meta[86:85]))} - & {4{io_update_bits_meta[87]}}); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 - wire _firstEntry_T_6 = io_update_bits_meta[60] & longerHistoryTableMask_1[0]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - wire _firstEntry_T_7 = io_update_bits_meta[61] & longerHistoryTableMask_1[1]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - wire _firstEntry_T_8 = io_update_bits_meta[62] & longerHistoryTableMask_1[2]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - reg tables_0_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_0_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_0_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_0_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_0_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_0_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_0_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg tables_1_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_1_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_1_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_1_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_1_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_1_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_1_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg tables_2_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_2_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_2_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_2_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_2_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_2_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_2_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg tables_3_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_3_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_3_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_3_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_3_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_3_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_3_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg tables_0_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_0_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_0_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_0_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_0_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_0_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_0_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg [38:0] tables_0_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - reg [7:0] tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [6:0] tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg tables_1_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_1_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_1_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_1_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_1_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_1_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_1_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg [38:0] tables_1_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - reg [6:0] tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [7:0] tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [10:0] tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg tables_2_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_2_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_2_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_2_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_2_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_2_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_2_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg [38:0] tables_2_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - reg [10:0] tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [6:0] tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [7:0] tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg tables_3_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - reg tables_3_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - reg tables_3_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - reg [2:0] tables_3_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - reg tables_3_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - reg tables_3_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - reg tables_3_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - reg [38:0] tables_3_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - reg [10:0] tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [7:0] tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg [6:0] tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - reg REG_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:848:31 - reg REG_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:848:31 - reg [1:0] REG_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:849:30 - reg [1:0] REG_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:849:30 - reg [38:0] bt_io_update_pc_REG; // src/main/scala/xiangshan/frontend/Tage.scala:850:29 - reg REG_4_0; // src/main/scala/xiangshan/frontend/Tage.scala:851:33 - reg REG_4_1; // src/main/scala/xiangshan/frontend/Tage.scala:851:33 - reg [4:0] scThresholds_0_ctr; // src/main/scala/xiangshan/frontend/SC.scala:229:52 - reg [7:0] scThresholds_0_thres; // src/main/scala/xiangshan/frontend/SC.scala:229:52 - reg [4:0] scThresholds_1_ctr; // src/main/scala/xiangshan/frontend/SC.scala:229:52 - reg [7:0] scThresholds_1_thres; // src/main/scala/xiangshan/frontend/SC.scala:229:52 - reg [8:0] s2_scTableSums_0; // src/main/scala/xiangshan/frontend/SC.scala:277:37 - reg [8:0] s2_scTableSums_1; // src/main/scala/xiangshan/frontend/SC.scala:277:37 - reg [2:0] s2_tagePrvdCtrCentered_r; // src/main/scala/xiangshan/frontend/SC.scala:278:61 - reg [5:0] s2_scResps_r_0_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_0_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_2_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_2_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_3_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_3_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg s3_pred_dup_0; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_2; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_3; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg sc_enable_dup_REG; // src/main/scala/xiangshan/frontend/SC.scala:319:38 - wire _GEN_1 = updateValids_0 & io_update_bits_meta[50]; // src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40 + & {4{io_update_bits_meta[87]}}); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] + wire _firstEntry_T_6 = io_update_bits_meta[60] & longerHistoryTableMask_1[0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + wire _firstEntry_T_7 = io_update_bits_meta[61] & longerHistoryTableMask_1[1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + wire _firstEntry_T_8 = io_update_bits_meta[62] & longerHistoryTableMask_1[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + reg tables_0_io_update_reset_u_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_0_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_0_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_0_io_update_alloc_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_0_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_0_io_update_uMask_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_0_io_update_us_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg tables_1_io_update_reset_u_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_1_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_1_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_1_io_update_alloc_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_1_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_1_io_update_uMask_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_1_io_update_us_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg tables_2_io_update_reset_u_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_2_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_2_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_2_io_update_alloc_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_2_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_2_io_update_uMask_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_2_io_update_us_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg tables_3_io_update_reset_u_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_3_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_3_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_3_io_update_alloc_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_3_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_3_io_update_uMask_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_3_io_update_us_0_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg tables_0_io_update_reset_u_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_0_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_0_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_0_io_update_alloc_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_0_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_0_io_update_uMask_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_0_io_update_us_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg [40:0] tables_0_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + reg [7:0] tables_0_io_update_folded_hist_r_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [6:0] tables_0_io_update_folded_hist_r_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg tables_1_io_update_reset_u_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_1_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_1_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_1_io_update_alloc_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_1_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_1_io_update_uMask_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_1_io_update_us_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg [40:0] tables_1_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + reg [6:0] tables_1_io_update_folded_hist_r_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [7:0] tables_1_io_update_folded_hist_r_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [10:0] tables_1_io_update_folded_hist_r_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg tables_2_io_update_reset_u_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_2_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_2_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_2_io_update_alloc_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_2_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_2_io_update_uMask_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_2_io_update_us_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg [40:0] tables_2_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + reg [10:0] tables_2_io_update_folded_hist_r_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [6:0] tables_2_io_update_folded_hist_r_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [7:0] tables_2_io_update_folded_hist_r_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg tables_3_io_update_reset_u_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + reg tables_3_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + reg tables_3_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + reg tables_3_io_update_alloc_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + reg [2:0] tables_3_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + reg tables_3_io_update_uMask_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + reg tables_3_io_update_us_1_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + reg [40:0] tables_3_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + reg [10:0] tables_3_io_update_folded_hist_r_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [7:0] tables_3_io_update_folded_hist_r_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg [6:0] tables_3_io_update_folded_hist_r_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + reg REG_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31] + reg REG_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31] + reg [1:0] r_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:851:32] + reg [1:0] r_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:851:32] + reg [40:0] bt_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31] + reg r_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:853:35] + reg r_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:853:35] + reg [4:0] scThresholds_0_ctr; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52] + reg [7:0] scThresholds_0_thres; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52] + reg [4:0] scThresholds_1_ctr; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52] + reg [7:0] scThresholds_1_thres; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52] + reg [8:0] s2_scTableSums_0; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37] + reg [8:0] s2_scTableSums_1; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37] + reg [2:0] s2_tagePrvdCtrCentered_r; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61] + reg [5:0] s2_scResps_r_0_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_0_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_2_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_2_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_3_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_3_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg s3_pred_dup_0; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_2; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_3; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg sc_enable_dup_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:319:38] + wire _GEN_1 = updateValids_0 & io_update_bits_meta[50]; // @[src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40] wire [7:0] _sum_T_8 = 8'({io_update_bits_meta[5], io_update_bits_meta[5:0], 1'h1} - + {io_update_bits_meta[11], io_update_bits_meta[11:6], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {io_update_bits_meta[11], io_update_bits_meta[11:6], 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _sum_T_9 = 8'({io_update_bits_meta[17], io_update_bits_meta[17:12], 1'h1} - + {io_update_bits_meta[23], io_update_bits_meta[23:18], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 - wire [8:0] _sum_T_10 = 9'({_sum_T_8[7], _sum_T_8} + {_sum_T_9[7], _sum_T_9}); // utility/src/main/scala/utility/ParallelMux.scala:115:82 - wire [2:0] _sumAboveThreshold_T = io_update_bits_meta[76:74] ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40 + + {io_update_bits_meta[23], io_update_bits_meta[23:18], 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82] + wire [8:0] _sum_T_10 = 9'({_sum_T_8[7], _sum_T_8} + {_sum_T_9[7], _sum_T_9}); // @[utility/src/main/scala/utility/ParallelMux.scala:115:82] + wire [2:0] _sumAboveThreshold_T = io_update_bits_meta[76:74] ^ 3'h4; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40] wire [9:0] sum = 10'({_sum_T_10[8], _sum_T_10} - + {{3{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {{3{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire _update_on_mispred_0_T = - io_update_bits_meta[48] != io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - reg [8:0] s2_scTableSums_1_0; // src/main/scala/xiangshan/frontend/SC.scala:277:37 - reg [8:0] s2_scTableSums_1_1; // src/main/scala/xiangshan/frontend/SC.scala:277:37 - reg [2:0] s2_tagePrvdCtrCentered_r_1; // src/main/scala/xiangshan/frontend/SC.scala:278:61 - reg [5:0] s2_scResps_r_1_0_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_0_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_1_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_1_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_2_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_2_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_3_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg [5:0] s2_scResps_r_1_3_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 - reg s3_pred_dup_0_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_1_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_2_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg s3_pred_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 - reg sc_enable_dup_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:319:38 - wire _GEN_2 = updateValids_1 & io_update_bits_meta[51]; // src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40 + io_update_bits_meta[48] != io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + reg [8:0] s2_scTableSums_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37] + reg [8:0] s2_scTableSums_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37] + reg [2:0] s2_tagePrvdCtrCentered_r_1; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61] + reg [5:0] s2_scResps_r_1_0_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_0_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_1_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_1_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_2_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_2_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_3_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg [5:0] s2_scResps_r_1_3_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41] + reg s3_pred_dup_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_2_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg s3_pred_dup_3_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54] + reg sc_enable_dup_REG_1; // @[src/main/scala/xiangshan/frontend/SC.scala:319:38] + wire _GEN_2 = updateValids_1 & io_update_bits_meta[51]; // @[src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40] wire [7:0] _sum_T_22 = 8'({io_update_bits_meta[29], io_update_bits_meta[29:24], 1'h1} - + {io_update_bits_meta[35], io_update_bits_meta[35:30], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {io_update_bits_meta[35], io_update_bits_meta[35:30], 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _sum_T_23 = 8'({io_update_bits_meta[41], io_update_bits_meta[41:36], 1'h1} - + {io_update_bits_meta[47], io_update_bits_meta[47:42], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 - wire [8:0] _sum_T_24 = 9'({_sum_T_22[7], _sum_T_22} + {_sum_T_23[7], _sum_T_23}); // utility/src/main/scala/utility/ParallelMux.scala:115:82 - wire [2:0] _sumAboveThreshold_T_19 = io_update_bits_meta[81:79] ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40 + + {io_update_bits_meta[47], io_update_bits_meta[47:42], 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82] + wire [8:0] _sum_T_24 = 9'({_sum_T_22[7], _sum_T_22} + {_sum_T_23[7], _sum_T_23}); // @[utility/src/main/scala/utility/ParallelMux.scala:115:82] + wire [2:0] _sumAboveThreshold_T_19 = io_update_bits_meta[81:79] ^ 3'h4; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40] wire [9:0] sum_1 = 10'({_sum_T_24[8], _sum_T_24} - + {{3{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {{3{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire _update_on_mispred_1_T = - io_update_bits_meta[49] != io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - reg scTables_0_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_0_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_0_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_0_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg scTables_1_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_1_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_1_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_1_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg scTables_2_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_2_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_2_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_2_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg scTables_3_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_3_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_3_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_3_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg scTables_0_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_0_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_0_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_0_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg [38:0] scTables_0_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - reg scTables_1_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_1_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_1_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_1_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg [38:0] scTables_1_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - reg [3:0] scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 - reg scTables_2_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_2_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_2_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_2_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg [38:0] scTables_2_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - reg [7:0] scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 - reg scTables_3_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 - reg scTables_3_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 - reg scTables_3_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - reg [5:0] scTables_3_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 - reg [38:0] scTables_3_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - reg [7:0] scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + io_update_bits_meta[49] != io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + reg scTables_0_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_0_io_update_tagePreds_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_0_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_0_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg scTables_1_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_1_io_update_tagePreds_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_1_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_1_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg scTables_2_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_2_io_update_tagePreds_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_2_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_2_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg scTables_3_io_update_mask_0_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_3_io_update_tagePreds_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_3_io_update_takens_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_3_io_update_oldCtrs_0_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg scTables_0_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_0_io_update_tagePreds_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_0_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_0_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg [40:0] scTables_0_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + reg scTables_1_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_1_io_update_tagePreds_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_1_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_1_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg [40:0] scTables_1_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + reg [3:0] scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + reg scTables_2_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_2_io_update_tagePreds_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_2_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_2_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg [40:0] scTables_2_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + reg [7:0] scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + reg scTables_3_io_update_mask_1_REG; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + reg scTables_3_io_update_tagePreds_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + reg scTables_3_io_update_takens_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + reg [5:0] scTables_3_io_update_oldCtrs_1_r; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + reg [40:0] scTables_3_io_update_pc_r_1; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + reg [7:0] scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + reg [1:0] io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [1:0] io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [1:0] io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [1:0] io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [1:0] io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [1:0] io_perf_2_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] wire [7:0] _s1_scTableSums_T_8 = 8'({_scTables_0_io_resp_ctrs_0_0[5], _scTables_0_io_resp_ctrs_0_0, 1'h1} - + {_scTables_1_io_resp_ctrs_0_0[5], _scTables_1_io_resp_ctrs_0_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_1_io_resp_ctrs_0_0[5], _scTables_1_io_resp_ctrs_0_0, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_9 = 8'({_scTables_2_io_resp_ctrs_0_0[5], _scTables_2_io_resp_ctrs_0_0, 1'h1} - + {_scTables_3_io_resp_ctrs_0_0[5], _scTables_3_io_resp_ctrs_0_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_3_io_resp_ctrs_0_0[5], _scTables_3_io_resp_ctrs_0_0, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_19 = 8'({_scTables_0_io_resp_ctrs_0_1[5], _scTables_0_io_resp_ctrs_0_1, 1'h1} - + {_scTables_1_io_resp_ctrs_0_1[5], _scTables_1_io_resp_ctrs_0_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_1_io_resp_ctrs_0_1[5], _scTables_1_io_resp_ctrs_0_1, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_20 = 8'({_scTables_2_io_resp_ctrs_0_1[5], _scTables_2_io_resp_ctrs_0_1, 1'h1} - + {_scTables_3_io_resp_ctrs_0_1[5], _scTables_3_io_resp_ctrs_0_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_3_io_resp_ctrs_0_1[5], _scTables_3_io_resp_ctrs_0_1, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_30 = 8'({_scTables_0_io_resp_ctrs_1_0[5], _scTables_0_io_resp_ctrs_1_0, 1'h1} - + {_scTables_1_io_resp_ctrs_1_0[5], _scTables_1_io_resp_ctrs_1_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_1_io_resp_ctrs_1_0[5], _scTables_1_io_resp_ctrs_1_0, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_31 = 8'({_scTables_2_io_resp_ctrs_1_0[5], _scTables_2_io_resp_ctrs_1_0, 1'h1} - + {_scTables_3_io_resp_ctrs_1_0[5], _scTables_3_io_resp_ctrs_1_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_3_io_resp_ctrs_1_0[5], _scTables_3_io_resp_ctrs_1_0, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_41 = 8'({_scTables_0_io_resp_ctrs_1_1[5], _scTables_0_io_resp_ctrs_1_1, 1'h1} - + {_scTables_1_io_resp_ctrs_1_1[5], _scTables_1_io_resp_ctrs_1_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_1_io_resp_ctrs_1_1[5], _scTables_1_io_resp_ctrs_1_1, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire [7:0] _s1_scTableSums_T_42 = 8'({_scTables_2_io_resp_ctrs_1_1[5], _scTables_2_io_resp_ctrs_1_1, 1'h1} - + {_scTables_3_io_resp_ctrs_1_1[5], _scTables_3_io_resp_ctrs_1_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_scTables_3_io_resp_ctrs_1_1[5], _scTables_3_io_resp_ctrs_1_1, 1'h1}); // @[src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82] wire useAltCtr = s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_0_0[3] | s1_pc_dup_0[7:1] == 7'h1 & useAltOnNaCtrs_0_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_0_2[3] @@ -849,56 +858,61 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_0_123[3] | s1_pc_dup_0[7:1] == 7'h7C & useAltOnNaCtrs_0_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_0_125[3] | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_0_126[3] | (&(s1_pc_dup_0[7:1])) - & useAltOnNaCtrs_0_127[3]; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41 - wire _providerInfo_T = _tables_3_io_resps_0_valid | _tables_2_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65 - wire [2:0] s1_providerResps_0_ctr = + & useAltOnNaCtrs_0_127[3]; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41] + wire _providerInfo_T = _tables_3_io_resps_0_valid | _tables_2_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65] + wire [2:0] providerInfo_resp_ctr = _providerInfo_T ? (_tables_3_io_resps_0_valid ? _tables_3_io_resps_0_bits_ctr : _tables_2_io_resps_0_bits_ctr) : _tables_1_io_resps_0_valid ? _tables_1_io_resps_0_bits_ctr - : _tables_0_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - wire s1_provideds_0 = + : _tables_0_io_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + wire provided = _tables_0_io_resps_0_valid | _tables_1_io_resps_0_valid | _tables_2_io_resps_0_valid - | _tables_3_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47 + | _tables_3_io_resps_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47] wire s1_altUsed_0 = - ~s1_provideds_0 + ~provided | (_providerInfo_T ? (_tables_3_io_resps_0_valid ? _tables_3_io_resps_0_bits_unconf & useAltCtr : _tables_2_io_resps_0_bits_unconf & useAltCtr) : _tables_1_io_resps_0_valid ? _tables_1_io_resps_0_bits_unconf & useAltCtr - : _tables_0_io_resps_0_bits_unconf & useAltCtr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + : _tables_0_io_resps_0_bits_unconf & useAltCtr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] wire s1_tageTakens_0 = - s1_altUsed_0 ? _bt_io_s1_cnt_0[1] : s1_providerResps_0_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77 - wire _GEN_3 = io_update_bits_meta[83:82] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 - wire _GEN_4 = updateValids_0 & io_update_bits_meta[84]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :620:31, :754:22, :755:29, :756:39 - wire _GEN_5 = io_update_bits_meta[83:82] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 - wire _GEN_6 = io_update_bits_meta[83:82] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + s1_altUsed_0 ? _bt_io_s1_cnt_0[1] : providerInfo_resp_ctr[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77] + wire baseupdate_0 = updateValids_0 & io_update_bits_meta[70]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :740:64] + wire _GEN_3 = io_update_bits_meta[83:82] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] + wire _GEN_4 = updateValids_0 & io_update_bits_meta[84]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :620:31, :754:22, :755:29, :756:39] + wire _GEN_5 = io_update_bits_meta[83:82] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] + wire _GEN_6 = io_update_bits_meta[83:82] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] wire [1:0] maskedEntry = io_update_bits_meta[56] & longerHistoryTableMask[0] & allocLFSR_lfsr[0] ? 2'h0 : io_update_bits_meta[57] & longerHistoryTableMask[1] & allocLFSR_lfsr[1] ? 2'h1 : {1'h1, - ~(io_update_bits_meta[58] & longerHistoryTableMask[2] & allocLFSR_lfsr[2])}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33 + ~(io_update_bits_meta[58] & longerHistoryTableMask[2] & allocLFSR_lfsr[2])}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33] wire [3:0] _allocate_T = - (io_update_bits_meta[59:56] & longerHistoryTableMask) >> maskedEntry; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36 + (io_update_bits_meta[59:56] & longerHistoryTableMask) >> maskedEntry; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36] wire [1:0] allocate = _allocate_T[0] ? maskedEntry - : _firstEntry_T ? 2'h0 : _firstEntry_T_1 ? 2'h1 : {1'h1, ~_firstEntry_T_2}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36} - wire _GEN_7 = allocate == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_8 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_7; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 - wire _GEN_9 = allocate == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_10 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_9; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 - wire _GEN_11 = allocate == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_12 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_11; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 - wire _GEN_13 = needToAllocate & (|(io_update_bits_meta[59:56])) & (&allocate); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33 - wire _GEN_14 = needToAllocate & (|(io_update_bits_meta[59:56])); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34 - wire updateResetU_0 = needToAllocate & (&bankTickCtrs_0); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59} + : _firstEntry_T ? 2'h0 : _firstEntry_T_1 ? 2'h1 : {1'h1, ~_firstEntry_T_2}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36}] + wire _GEN_7 = allocate == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_8 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_7; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_0_0 = _GEN_8 | _GEN_4 & _GEN_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_9 = allocate == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_10 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_9; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_0_1 = _GEN_10 | _GEN_4 & _GEN_5; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_11 = allocate == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_12 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_11; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_0_2 = _GEN_12 | _GEN_4 & _GEN_6; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_13 = needToAllocate & (|(io_update_bits_meta[59:56])) & (&allocate); // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33] + wire updateMask_0_3 = _GEN_13 | _GEN_4 & (&(io_update_bits_meta[83:82])); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_14 = needToAllocate & (|(io_update_bits_meta[59:56])); // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34] + wire updateResetU_0 = needToAllocate & (&bankTickCtrs_0); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59}] wire useAltCtr_1 = s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_1_0[3] | s1_pc_dup_0[7:1] == 7'h1 & useAltOnNaCtrs_1_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_1_2[3] @@ -985,8 +999,8 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_1_123[3] | s1_pc_dup_0[7:1] == 7'h7C & useAltOnNaCtrs_1_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_1_125[3] | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_1_126[3] | (&(s1_pc_dup_0[7:1])) - & useAltOnNaCtrs_1_127[3]; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41 - wire _providerInfo_T_5 = _tables_3_io_resps_1_valid | _tables_2_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65 + & useAltOnNaCtrs_1_127[3]; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41] + wire _providerInfo_T_5 = _tables_3_io_resps_1_valid | _tables_2_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65] wire [2:0] s1_providerResps_1_ctr = _providerInfo_T_5 ? (_tables_3_io_resps_1_valid @@ -994,25 +1008,26 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 : _tables_2_io_resps_1_bits_ctr) : _tables_1_io_resps_1_valid ? _tables_1_io_resps_1_bits_ctr - : _tables_0_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - wire s1_provideds_1 = + : _tables_0_io_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + wire provided_1 = _tables_0_io_resps_1_valid | _tables_1_io_resps_1_valid | _tables_2_io_resps_1_valid - | _tables_3_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47 + | _tables_3_io_resps_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47] wire s1_altUsed_1 = - ~s1_provideds_1 + ~provided_1 | (_providerInfo_T_5 ? (_tables_3_io_resps_1_valid ? _tables_3_io_resps_1_bits_unconf & useAltCtr_1 : _tables_2_io_resps_1_bits_unconf & useAltCtr_1) : _tables_1_io_resps_1_valid ? _tables_1_io_resps_1_bits_unconf & useAltCtr_1 - : _tables_0_io_resps_1_bits_unconf & useAltCtr_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + : _tables_0_io_resps_1_bits_unconf & useAltCtr_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] wire s1_tageTakens_1 = - s1_altUsed_1 ? _bt_io_s1_cnt_1[1] : s1_providerResps_1_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77 - wire _GEN_15 = io_update_bits_meta[86:85] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 - wire _GEN_16 = updateValids_1 & io_update_bits_meta[87]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :620:31, :754:22, :755:29, :756:39 - wire _GEN_17 = io_update_bits_meta[86:85] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 - wire _GEN_18 = io_update_bits_meta[86:85] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + s1_altUsed_1 ? _bt_io_s1_cnt_1[1] : s1_providerResps_1_ctr[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77] + wire baseupdate_1 = updateValids_1 & io_update_bits_meta[71]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :740:64] + wire _GEN_15 = io_update_bits_meta[86:85] == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] + wire _GEN_16 = updateValids_1 & io_update_bits_meta[87]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :620:31, :754:22, :755:29, :756:39] + wire _GEN_17 = io_update_bits_meta[86:85] == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] + wire _GEN_18 = io_update_bits_meta[86:85] == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39] wire [1:0] maskedEntry_1 = io_update_bits_meta[60] & longerHistoryTableMask_1[0] & allocLFSR_lfsr_1[0] ? 2'h0 @@ -1020,35 +1035,39 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 ? 2'h1 : {1'h1, ~(io_update_bits_meta[62] & longerHistoryTableMask_1[2] - & allocLFSR_lfsr_1[2])}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33 + & allocLFSR_lfsr_1[2])}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33] wire [3:0] _allocate_T_2 = - (io_update_bits_meta[63:60] & longerHistoryTableMask_1) >> maskedEntry_1; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36 + (io_update_bits_meta[63:60] & longerHistoryTableMask_1) >> maskedEntry_1; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36] wire [1:0] allocate_1 = _allocate_T_2[0] ? maskedEntry_1 - : _firstEntry_T_6 ? 2'h0 : _firstEntry_T_7 ? 2'h1 : {1'h1, ~_firstEntry_T_8}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36} - wire _GEN_19 = allocate_1 == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_20 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_19; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 - wire _GEN_21 = allocate_1 == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_22 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_21; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 - wire _GEN_23 = allocate_1 == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 - wire _GEN_24 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_23; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + : _firstEntry_T_6 ? 2'h0 : _firstEntry_T_7 ? 2'h1 : {1'h1, ~_firstEntry_T_8}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:180:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36}] + wire _GEN_19 = allocate_1 == 2'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_20 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_19; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_1_0 = _GEN_20 | _GEN_16 & _GEN_15; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_21 = allocate_1 == 2'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_22 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_21; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_1_1 = _GEN_22 | _GEN_16 & _GEN_17; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_23 = allocate_1 == 2'h2; // @[src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33] + wire _GEN_24 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_23; // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33] + wire updateMask_1_2 = _GEN_24 | _GEN_16 & _GEN_18; // @[src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] wire _GEN_25 = - needToAllocate_1 & (|(io_update_bits_meta[63:60])) & (&allocate_1); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33 - wire _GEN_26 = needToAllocate_1 & (|(io_update_bits_meta[63:60])); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34 - wire updateResetU_1 = needToAllocate_1 & (&bankTickCtrs_1); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59} - wire [2:0] _s2_tagePrvdCtrCentered_T = s2_tagePrvdCtrCentered_r ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34 + needToAllocate_1 & (|(io_update_bits_meta[63:60])) & (&allocate_1); // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33] + wire updateMask_1_3 = _GEN_25 | _GEN_16 & (&(io_update_bits_meta[86:85])); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33] + wire _GEN_26 = needToAllocate_1 & (|(io_update_bits_meta[63:60])); // @[src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34] + wire updateResetU_1 = needToAllocate_1 & (&bankTickCtrs_1); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59}] + wire [2:0] _s2_tagePrvdCtrCentered_T = s2_tagePrvdCtrCentered_r ^ 3'h4; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34] wire [9:0] _GEN_27 = - {{3{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire [9:0] s2_totalSums_0 = 10'({s2_scTableSums_0[8], s2_scTableSums_0} + _GEN_27); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 - wire [9:0] s2_totalSums_1 = 10'({s2_scTableSums_1[8], s2_scTableSums_1} + _GEN_27); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 - wire [8:0] _GEN_28 = {1'h0, scThresholds_0_thres}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29 + {{3{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire [9:0] s2_totalSums_0 = 10'({s2_scTableSums_0[8], s2_scTableSums_0} + _GEN_27); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47] + wire [9:0] s2_totalSums_1 = 10'({s2_scTableSums_1[8], s2_scTableSums_1} + _GEN_27); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47] + wire [8:0] _GEN_28 = {1'h0, scThresholds_0_thres}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29] wire [8:0] _GEN_29 = - {{2{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + {{2{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14] wire _GEN_30 = s2_tageTakens_dup_3_0 ? $signed(s2_totalSums_1) > -10'sh1 - : $signed(s2_totalSums_0) > -10'sh1; // src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + : $signed(s2_totalSums_0) > -10'sh1; // @[src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58] wire s2_pred = s2_provideds_0 & (s2_tageTakens_dup_3_0 @@ -1061,84 +1080,86 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 | $signed(s2_scTableSums_0) < $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29)) & s2_totalSums_0[9]) ? _GEN_30 - : s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58 - wire [12:0] _GEN_31 = {1'h0, 12'({1'h0, scThresholds_0_thres, 3'h0} + 12'h15)}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47 - wire [12:0] _GEN_32 = {{6{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire [12:0] _GEN_33 = {{3{sum[9]}}, sum}; // src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26 + : s2_tageTakens_dup_3_0; // @[src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58] + wire [12:0] _GEN_31 = {1'h0, 12'({1'h0, scThresholds_0_thres, 3'h0} + 12'h15)}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47] + wire [12:0] _GEN_32 = {{6{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire [12:0] _GEN_33 = {{3{sum[9]}}, sum}; // @[src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26] wire [10:0] sumAboveThreshold_totalSum = - 11'({sum[9], sum} + {{4{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire scUpdateMask_0_3 = - _GEN_1 - & (_update_on_mispred_0_T - | ~($signed(_GEN_33) > $signed(13'(_GEN_31 - _GEN_32)) - & ~(sumAboveThreshold_totalSum[10]) - | $signed(_GEN_33) < $signed(13'(13'(13'h0 - _GEN_31) - _GEN_32)) - & sumAboveThreshold_totalSum[10])); // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :246:32, :328:{29,56}, :343:29, :348:40, :357:{32,55} - wire [2:0] _s2_tagePrvdCtrCentered_T_2 = s2_tagePrvdCtrCentered_r_1 ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34 - wire [9:0] _GEN_34 = - {{3{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + 11'({sum[9], sum} + {{4{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // @[src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire _GEN_34 = + _update_on_mispred_0_T + | ~($signed(_GEN_33) > $signed(13'(_GEN_31 - _GEN_32)) + & ~(sumAboveThreshold_totalSum[10]) + | $signed(_GEN_33) < $signed(13'(13'(13'h0 - _GEN_31) - _GEN_32)) + & sumAboveThreshold_totalSum[10]); // @[src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :343:29, :348:40, :357:32] + wire scUpdateMask_0_3 = _GEN_1 & _GEN_34; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:{29,56}, :357:{32,55}] + wire _GEN_35 = _GEN_1 & _GEN_34; // @[src/main/scala/xiangshan/frontend/SC.scala:212:53, :328:{29,56}, :357:{32,55}, :368:32] + wire [2:0] _s2_tagePrvdCtrCentered_T_2 = s2_tagePrvdCtrCentered_r_1 ^ 3'h4; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34] + wire [9:0] _GEN_36 = + {{3{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14] wire [9:0] s2_totalSums_0_1 = - 10'({s2_scTableSums_1_0[8], s2_scTableSums_1_0} + _GEN_34); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 + 10'({s2_scTableSums_1_0[8], s2_scTableSums_1_0} + _GEN_36); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47] wire [9:0] s2_totalSums_1_1 = - 10'({s2_scTableSums_1_1[8], s2_scTableSums_1_1} + _GEN_34); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 - wire [8:0] _GEN_35 = {1'h0, scThresholds_1_thres}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29 - wire [8:0] _GEN_36 = - {{2{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire _GEN_37 = + 10'({s2_scTableSums_1_1[8], s2_scTableSums_1_1} + _GEN_36); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47] + wire [8:0] _GEN_37 = {1'h0, scThresholds_1_thres}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29] + wire [8:0] _GEN_38 = + {{2{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire _GEN_39 = s2_tageTakens_dup_3_1 ? $signed(s2_totalSums_1_1) > -10'sh1 - : $signed(s2_totalSums_0_1) > -10'sh1; // src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + : $signed(s2_totalSums_0_1) > -10'sh1; // @[src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58] wire s2_pred_1 = s2_provideds_1 & (s2_tageTakens_dup_3_1 - ? $signed(s2_scTableSums_1_1) > $signed(9'(_GEN_35 - _GEN_36)) + ? $signed(s2_scTableSums_1_1) > $signed(9'(_GEN_37 - _GEN_38)) & ~(s2_totalSums_1_1[9]) - | $signed(s2_scTableSums_1_1) < $signed(9'(9'(9'h0 - _GEN_35) - _GEN_36)) + | $signed(s2_scTableSums_1_1) < $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38)) & s2_totalSums_1_1[9] - : $signed(s2_scTableSums_1_0) > $signed(9'(_GEN_35 - _GEN_36)) + : $signed(s2_scTableSums_1_0) > $signed(9'(_GEN_37 - _GEN_38)) & ~(s2_totalSums_0_1[9]) - | $signed(s2_scTableSums_1_0) < $signed(9'(9'(9'h0 - _GEN_35) - _GEN_36)) + | $signed(s2_scTableSums_1_0) < $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38)) & s2_totalSums_0_1[9]) - ? _GEN_37 - : s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58 - wire [12:0] _GEN_38 = {1'h0, 12'({1'h0, scThresholds_1_thres, 3'h0} + 12'h15)}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47 - wire [12:0] _GEN_39 = {{6{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire [12:0] _GEN_40 = {{3{sum_1[9]}}, sum_1}; // src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26 + ? _GEN_39 + : s2_tageTakens_dup_3_1; // @[src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58] + wire [12:0] _GEN_40 = {1'h0, 12'({1'h0, scThresholds_1_thres, 3'h0} + 12'h15)}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47] + wire [12:0] _GEN_41 = {{6{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}; // @[src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire [12:0] _GEN_42 = {{3{sum_1[9]}}, sum_1}; // @[src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26] wire [10:0] sumAboveThreshold_totalSum_1 = 11'({sum_1[9], sum_1} - + {{4{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14 - wire scUpdateMask_1_3 = - _GEN_2 - & (_update_on_mispred_1_T - | ~($signed(_GEN_40) > $signed(13'(_GEN_38 - _GEN_39)) - & ~(sumAboveThreshold_totalSum_1[10]) - | $signed(_GEN_40) < $signed(13'(13'(13'h0 - _GEN_38) - _GEN_39)) - & sumAboveThreshold_totalSum_1[10])); // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :246:32, :328:{29,56}, :343:29, :348:40, :357:{32,55} - wire [1:0] s1_providers_0 = + + {{4{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // @[src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14] + wire _GEN_43 = + _update_on_mispred_1_T + | ~($signed(_GEN_42) > $signed(13'(_GEN_40 - _GEN_41)) + & ~(sumAboveThreshold_totalSum_1[10]) + | $signed(_GEN_42) < $signed(13'(13'(13'h0 - _GEN_40) - _GEN_41)) + & sumAboveThreshold_totalSum_1[10]); // @[src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :343:29, :348:40, :357:32] + wire scUpdateMask_1_3 = _GEN_2 & _GEN_43; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:{29,56}, :357:{32,55}] + wire _GEN_44 = _GEN_2 & _GEN_43; // @[src/main/scala/xiangshan/frontend/SC.scala:212:53, :328:{29,56}, :357:{32,55}, :368:32] + wire [1:0] providerInfo_tableIdx = _providerInfo_T ? {1'h1, _tables_3_io_resps_0_valid} - : {1'h0, _tables_1_io_resps_0_valid}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, :179:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - wire [3:0] _allocatableSlots_T_14 = 4'h1 << s1_providers_0; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77 - wire [2:0] _GEN_41 = _allocatableSlots_T_14[2:0] | _allocatableSlots_T_14[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + : {1'h0, _tables_1_io_resps_0_valid}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, :180:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + wire [3:0] _allocatableSlots_T_14 = 4'h1 << providerInfo_tableIdx; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77] + wire [2:0] _GEN_45 = _allocatableSlots_T_14[2:0] | _allocatableSlots_T_14[3:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire [1:0] s1_providers_1 = _providerInfo_T_5 ? {1'h1, _tables_3_io_resps_1_valid} - : {1'h0, _tables_1_io_resps_1_valid}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, :179:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - wire [3:0] _allocatableSlots_T_39 = 4'h1 << s1_providers_1; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77 - wire [2:0] _GEN_42 = _allocatableSlots_T_39[2:0] | _allocatableSlots_T_39[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 - always @(posedge clock) begin - if (REG_1) // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - s1_pc_dup_0 <= {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39, src/main/scala/xiangshan/frontend/SC.scala:266:47, utility/src/main/scala/utility/Hold.scala:97:23 - else if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} - if (io_s1_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_provideds_0 <= s1_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47 - s2_provideds_1 <= s1_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47 - s2_providers_0 <= s1_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 - s2_providers_1 <= s1_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 - s2_providerResps_0_ctr <= s1_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + : {1'h0, _tables_1_io_resps_1_valid}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, :180:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + wire [3:0] _allocatableSlots_T_39 = 4'h1 << s1_providers_1; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77] + wire [2:0] _GEN_46 = _allocatableSlots_T_39[2:0] | _allocatableSlots_T_39[3:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + if (REG_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + s1_pc_dup_0 <= {5'h0, _reset_vector_delay_io_out}; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, :187:86, :192:39, utility/src/main/scala/utility/Hold.scala:100:23] + else if (io_s0_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + REG <= reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + REG_1 <= REG & ~reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24,39,42}] + if (io_s1_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_provideds_0 <= provided; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47] + s2_provideds_1 <= provided_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47] + s2_providers_0 <= providerInfo_tableIdx; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77] + s2_providers_1 <= s1_providers_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77] + s2_providerResps_0_ctr <= providerInfo_resp_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77] s2_providerResps_0_u <= _providerInfo_T ? (_tables_3_io_resps_0_valid @@ -1146,7 +1167,7 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 : _tables_2_io_resps_0_bits_u) : _tables_1_io_resps_0_valid ? _tables_1_io_resps_0_bits_u - : _tables_0_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + : _tables_0_io_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] s2_providerResps_0_unconf <= _providerInfo_T ? (_tables_3_io_resps_0_valid @@ -1154,8 +1175,8 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 : _tables_2_io_resps_0_bits_unconf) : _tables_1_io_resps_0_valid ? _tables_1_io_resps_0_bits_unconf - : _tables_0_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - s2_providerResps_1_ctr <= s1_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + : _tables_0_io_resps_0_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + s2_providerResps_1_ctr <= s1_providerResps_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77] s2_providerResps_1_u <= _providerInfo_T_5 ? (_tables_3_io_resps_1_valid @@ -1163,7 +1184,7 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 : _tables_2_io_resps_1_bits_u) : _tables_1_io_resps_1_valid ? _tables_1_io_resps_1_bits_u - : _tables_0_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + : _tables_0_io_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] s2_providerResps_1_unconf <= _providerInfo_T_5 ? (_tables_3_io_resps_1_valid @@ -1171,367 +1192,395 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 : _tables_2_io_resps_1_bits_unconf) : _tables_1_io_resps_1_valid ? _tables_1_io_resps_1_bits_unconf - : _tables_0_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} - s2_altUsed_0 <= s1_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38 - s2_altUsed_1 <= s1_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38 - s2_tageTakens_dup_1_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 - s2_tageTakens_dup_1_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 - s2_finalAltPreds_0 <= _bt_io_s1_cnt_0[1]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18 - s2_finalAltPreds_1 <= _bt_io_s1_cnt_1[1]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18 - s2_basecnts_0 <= _bt_io_s1_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38 - s2_basecnts_1 <= _bt_io_s1_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38 + : _tables_0_io_resps_1_bits_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77}] + s2_altUsed_0 <= s1_altUsed_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38] + s2_altUsed_1 <= s1_altUsed_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38] + s2_tageTakens_dup_1_0 <= s1_tageTakens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] + s2_tageTakens_dup_1_1 <= s1_tageTakens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] + s2_finalAltPreds_0 <= _bt_io_s1_cnt_0[1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18] + s2_finalAltPreds_1 <= _bt_io_s1_cnt_1[1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18] + s2_basecnts_0 <= _bt_io_s1_cnt_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38] + s2_basecnts_1 <= _bt_io_s1_cnt_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38] allocatableSlots <= {~_tables_3_io_resps_0_valid & ~_tables_3_io_resps_0_bits_u, ~_tables_2_io_resps_0_valid & ~_tables_2_io_resps_0_bits_u, ~_tables_1_io_resps_0_valid & ~_tables_1_io_resps_0_bits_u, ~_tables_0_io_resps_0_valid & ~_tables_0_io_resps_0_bits_u} - & ~({&s1_providers_0, - _GEN_41[2], - _GEN_41[1] | (&s1_providers_0), - _GEN_41[0] | s1_providers_0 == 2'h2 | (&s1_providers_0)} - & {4{s1_provideds_0}}); // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77 + & ~({&providerInfo_tableIdx, + _GEN_45[2], + _GEN_45[1] | (&providerInfo_tableIdx), + _GEN_45[0] | providerInfo_tableIdx == 2'h2 | (&providerInfo_tableIdx)} + & {4{provided}}); // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77] allocatableSlots_1 <= {~_tables_3_io_resps_1_valid & ~_tables_3_io_resps_1_bits_u, ~_tables_2_io_resps_1_valid & ~_tables_2_io_resps_1_bits_u, ~_tables_1_io_resps_1_valid & ~_tables_1_io_resps_1_bits_u, ~_tables_0_io_resps_1_valid & ~_tables_0_io_resps_1_bits_u} & ~({&s1_providers_1, - _GEN_42[2], - _GEN_42[1] | (&s1_providers_1), - _GEN_42[0] | s1_providers_1 == 2'h2 | (&s1_providers_1)} - & {4{s1_provideds_1}}); // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77 + _GEN_46[2], + _GEN_46[1] | (&s1_providers_1), + _GEN_46[0] | s1_providers_1 == 2'h2 | (&s1_providers_1)} & {4{provided_1}}); // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77] end - if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_tageTakens_dup_0_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 - s2_tageTakens_dup_0_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + if (io_s1_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_tageTakens_dup_0_0 <= s1_tageTakens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] + s2_tageTakens_dup_0_1 <= s1_tageTakens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] end - if (io_s1_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_tageTakens_dup_2_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 - s2_tageTakens_dup_2_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + if (io_s1_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_tageTakens_dup_2_0 <= s1_tageTakens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] + s2_tageTakens_dup_2_1 <= s1_tageTakens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] end - if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s2_tageTakens_dup_3_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 - s2_tageTakens_dup_3_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + if (io_s1_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s2_tageTakens_dup_3_0 <= s1_tageTakens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] + s2_tageTakens_dup_3_1 <= s1_tageTakens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10] s2_scTableSums_0 <= 9'({_s1_scTableSums_T_8[7], _s1_scTableSums_T_8} - + {_s1_scTableSums_T_9[7], _s1_scTableSums_T_9}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_s1_scTableSums_T_9[7], _s1_scTableSums_T_9}); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82] s2_scTableSums_1 <= 9'({_s1_scTableSums_T_19[7], _s1_scTableSums_T_19} - + {_s1_scTableSums_T_20[7], _s1_scTableSums_T_20}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 - s2_tagePrvdCtrCentered_r <= s1_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77 - s2_scResps_r_0_ctrs_0_0 <= _scTables_0_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_0_ctrs_0_1 <= _scTables_0_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_ctrs_0_0 <= _scTables_1_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_ctrs_0_1 <= _scTables_1_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_2_ctrs_0_0 <= _scTables_2_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_2_ctrs_0_1 <= _scTables_2_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_3_ctrs_0_0 <= _scTables_3_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_3_ctrs_0_1 <= _scTables_3_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + + {_s1_scTableSums_T_20[7], _s1_scTableSums_T_20}); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82] + s2_tagePrvdCtrCentered_r <= providerInfo_resp_ctr; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77] + s2_scResps_r_0_ctrs_0_0 <= _scTables_0_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_0_ctrs_0_1 <= _scTables_0_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_ctrs_0_0 <= _scTables_1_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_ctrs_0_1 <= _scTables_1_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_2_ctrs_0_0 <= _scTables_2_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_2_ctrs_0_1 <= _scTables_2_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_3_ctrs_0_0 <= _scTables_3_io_resp_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_3_ctrs_0_1 <= _scTables_3_io_resp_ctrs_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] s2_scTableSums_1_0 <= 9'({_s1_scTableSums_T_30[7], _s1_scTableSums_T_30} - + {_s1_scTableSums_T_31[7], _s1_scTableSums_T_31}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + + {_s1_scTableSums_T_31[7], _s1_scTableSums_T_31}); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82] s2_scTableSums_1_1 <= 9'({_s1_scTableSums_T_41[7], _s1_scTableSums_T_41} - + {_s1_scTableSums_T_42[7], _s1_scTableSums_T_42}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 - s2_tagePrvdCtrCentered_r_1 <= s1_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77 - s2_scResps_r_1_0_ctrs_1_0 <= _scTables_0_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_0_ctrs_1_1 <= _scTables_0_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_1_ctrs_1_0 <= _scTables_1_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_1_ctrs_1_1 <= _scTables_1_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_2_ctrs_1_0 <= _scTables_2_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_2_ctrs_1_1 <= _scTables_2_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_3_ctrs_1_0 <= _scTables_3_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 - s2_scResps_r_1_3_ctrs_1_1 <= _scTables_3_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + + {_s1_scTableSums_T_42[7], _s1_scTableSums_T_42}); // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82] + s2_tagePrvdCtrCentered_r_1 <= s1_providerResps_1_ctr; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77] + s2_scResps_r_1_0_ctrs_1_0 <= _scTables_0_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_0_ctrs_1_1 <= _scTables_0_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_1_ctrs_1_0 <= _scTables_1_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_1_ctrs_1_1 <= _scTables_1_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_2_ctrs_1_0 <= _scTables_2_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_2_ctrs_1_1 <= _scTables_2_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_3_ctrs_1_0 <= _scTables_3_io_resp_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] + s2_scResps_r_1_3_ctrs_1_1 <= _scTables_3_io_resp_ctrs_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41] end - if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - resp_meta_providers_0_valid_r <= s2_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49 - resp_meta_providers_0_bits_r <= s2_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49 - resp_meta_providerResps_0_r_ctr <= s2_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_providerResps_0_r_u <= s2_providerResps_0_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_providerResps_0_r_unconf <= s2_providerResps_0_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_allocates_0_r <= allocatableSlots; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40 - resp_meta_altUsed_0_r <= s2_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41 - resp_meta_altDiffers_0_r <= s2_finalAltPreds_0 != s2_providerResps_0_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54} - resp_meta_takens_0_r <= s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41 - resp_meta_basecnts_0_r <= s2_basecnts_0; // src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41 - resp_meta_providers_1_valid_r <= s2_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49 - resp_meta_providers_1_bits_r <= s2_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49 - resp_meta_providerResps_1_r_ctr <= s2_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_providerResps_1_r_u <= s2_providerResps_1_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_providerResps_1_r_unconf <= s2_providerResps_1_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 - resp_meta_allocates_1_r <= allocatableSlots_1; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40 - resp_meta_altUsed_1_r <= s2_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41 - resp_meta_altDiffers_1_r <= s2_finalAltPreds_1 != s2_providerResps_1_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54} - resp_meta_takens_1_r <= s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41 - resp_meta_basecnts_1_r <= s2_basecnts_1; // src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41 - s3_pred_dup_1 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 - s3_pred_dup_1_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + if (io_s2_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + resp_meta_providers_0_valid_r <= s2_provideds_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49] + resp_meta_providers_0_bits_r <= s2_providers_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49] + resp_meta_providerResps_0_r_ctr <= s2_providerResps_0_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_providerResps_0_r_u <= s2_providerResps_0_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_providerResps_0_r_unconf <= s2_providerResps_0_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_allocates_0_r <= allocatableSlots; // @[src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40] + resp_meta_altUsed_0_r <= s2_altUsed_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41] + resp_meta_altDiffers_0_r <= s2_finalAltPreds_0 != s2_providerResps_0_ctr[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54}] + resp_meta_takens_0_r <= s2_tageTakens_dup_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41] + resp_meta_basecnts_0_r <= s2_basecnts_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41] + resp_meta_providers_1_valid_r <= s2_provideds_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49] + resp_meta_providers_1_bits_r <= s2_providers_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49] + resp_meta_providerResps_1_r_ctr <= s2_providerResps_1_ctr; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_providerResps_1_r_u <= s2_providerResps_1_u; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_providerResps_1_r_unconf <= s2_providerResps_1_unconf; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49] + resp_meta_allocates_1_r <= allocatableSlots_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40] + resp_meta_altUsed_1_r <= s2_altUsed_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41] + resp_meta_altDiffers_1_r <= s2_finalAltPreds_1 != s2_providerResps_1_ctr[2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54}] + resp_meta_takens_1_r <= s2_tageTakens_dup_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41] + resp_meta_basecnts_1_r <= s2_basecnts_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41] + s3_pred_dup_1 <= s2_pred; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + s3_pred_dup_1_1 <= s2_pred_1; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] end - tage_enable_dup_REG <= io_ctrl_tage_enable; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 - tage_enable_dup_REG_1 <= io_ctrl_tage_enable; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 - tables_0_io_update_mask_0_REG <= _GEN_8 | _GEN_4 & _GEN_3; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_0_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_0_io_update_alloc_0_REG <= _GEN_14 & _GEN_7; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_0_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_0_io_update_uMask_0_REG <= - _GEN_8 | updateValids_0 & io_update_bits_meta[84] & _GEN_3 - & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_0_io_update_us_0_REG <= ~_GEN_8 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_0_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_1_io_update_mask_0_REG <= _GEN_10 | _GEN_4 & _GEN_5; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_1_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_1_io_update_alloc_0_REG <= _GEN_14 & _GEN_9; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_1_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_1_io_update_uMask_0_REG <= - _GEN_10 | updateValids_0 & io_update_bits_meta[84] & _GEN_5 - & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_1_io_update_us_0_REG <= ~_GEN_10 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_1_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_2_io_update_mask_0_REG <= _GEN_12 | _GEN_4 & _GEN_6; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_2_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_2_io_update_alloc_0_REG <= _GEN_14 & _GEN_11; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_2_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_2_io_update_uMask_0_REG <= - _GEN_12 | updateValids_0 & io_update_bits_meta[84] & _GEN_6 - & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_2_io_update_us_0_REG <= ~_GEN_12 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_2_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_3_io_update_mask_0_REG <= _GEN_13 | _GEN_4 & (&(io_update_bits_meta[83:82])); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_3_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_3_io_update_alloc_0_REG <= _GEN_14 & (&allocate); // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_3_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_3_io_update_uMask_0_REG <= - _GEN_13 | updateValids_0 & io_update_bits_meta[84] & (&(io_update_bits_meta[83:82])) - & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_3_io_update_us_0_REG <= ~_GEN_13 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_3_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_0_io_update_mask_1_REG <= _GEN_20 | _GEN_16 & _GEN_15; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_0_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_0_io_update_alloc_1_REG <= _GEN_26 & _GEN_19; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_0_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_0_io_update_uMask_1_REG <= - _GEN_20 | updateValids_1 & io_update_bits_meta[87] & _GEN_15 - & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_0_io_update_us_1_REG <= ~_GEN_20 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_0_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_0_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_1_io_update_mask_1_REG <= _GEN_22 | _GEN_16 & _GEN_17; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_1_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_1_io_update_alloc_1_REG <= _GEN_26 & _GEN_21; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_1_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_1_io_update_uMask_1_REG <= - _GEN_22 | updateValids_1 & io_update_bits_meta[87] & _GEN_17 - & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_1_io_update_us_1_REG <= ~_GEN_22 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_1_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_1_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_2_io_update_mask_1_REG <= _GEN_24 | _GEN_16 & _GEN_18; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_2_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_2_io_update_alloc_1_REG <= _GEN_26 & _GEN_23; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_2_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_2_io_update_uMask_1_REG <= - _GEN_24 | updateValids_1 & io_update_bits_meta[87] & _GEN_18 - & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_2_io_update_us_1_REG <= ~_GEN_24 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_2_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_2_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_3_io_update_mask_1_REG <= _GEN_25 | _GEN_16 & (&(io_update_bits_meta[86:85])); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 - tables_3_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 - tables_3_io_update_alloc_1_REG <= _GEN_26 & (&allocate_1); // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :836:48 - tables_3_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 - tables_3_io_update_uMask_1_REG <= - _GEN_25 | updateValids_1 & io_update_bits_meta[87] & (&(io_update_bits_meta[86:85])) - & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 - tables_3_io_update_us_1_REG <= ~_GEN_25 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 - tables_3_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 - tables_3_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 - tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - REG_2_0 <= updateValids_0 & io_update_bits_meta[70]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :740:64, :848:31 - REG_2_1 <= updateValids_1 & io_update_bits_meta[71]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :740:64, :848:31 - REG_3_0 <= io_update_bits_meta[65:64]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :849:30 - REG_3_1 <= io_update_bits_meta[67:66]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :849:30 - bt_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:850:29 - REG_4_0 <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :851:33 - REG_4_1 <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :851:33 - if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - resp_meta_scMeta_tageTakens_0_r <= s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - resp_meta_scMeta_scUsed_0_r <= s2_provideds_0; // src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38 - resp_meta_scMeta_scPreds_0_r <= _GEN_30; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40 - r_0 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_0_ctrs_0_1 : s2_scResps_r_0_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_1 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_1_ctrs_0_1 : s2_scResps_r_1_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_2 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_2_ctrs_0_1 : s2_scResps_r_2_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_3 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_3_ctrs_0_1 : s2_scResps_r_3_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - s3_pred_dup_3 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 - resp_meta_scMeta_tageTakens_1_r <= s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - resp_meta_scMeta_scUsed_1_r <= s2_provideds_1; // src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38 - resp_meta_scMeta_scPreds_1_r <= _GEN_37; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40 - r_1_0 <= - s2_tageTakens_dup_3_1 ? s2_scResps_r_1_0_ctrs_1_1 : s2_scResps_r_1_0_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_1_1 <= - s2_tageTakens_dup_3_1 ? s2_scResps_r_1_1_ctrs_1_1 : s2_scResps_r_1_1_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_1_2 <= - s2_tageTakens_dup_3_1 ? s2_scResps_r_1_2_ctrs_1_1 : s2_scResps_r_1_2_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - r_1_3 <= - s2_tageTakens_dup_3_1 ? s2_scResps_r_1_3_ctrs_1_1 : s2_scResps_r_1_3_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 - s3_pred_dup_3_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + tage_enable_dup_REG <= io_ctrl_tage_enable; // @[src/main/scala/xiangshan/frontend/Tage.scala:705:38] + tage_enable_dup_REG_1 <= io_ctrl_tage_enable; // @[src/main/scala/xiangshan/frontend/Tage.scala:705:38] + tables_0_io_update_reset_u_0_REG <= updateResetU_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_0_io_update_mask_0_REG <= updateMask_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + if (updateMask_0_0 | updateMask_1_0) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :832:59] + tables_0_io_update_takens_0_r <= updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_0_io_update_alloc_0_r <= _GEN_14 & _GEN_7; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_0_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_0_io_update_uMask_0_r <= + _GEN_8 | updateValids_0 & io_update_bits_meta[84] & _GEN_3 + & io_update_bits_meta[68]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_0_io_update_us_0_r <= ~_GEN_8 & updateProviderCorrect; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_0_io_update_takens_1_r <= updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_0_io_update_alloc_1_r <= _GEN_26 & _GEN_19; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_0_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_0_io_update_uMask_1_r <= + _GEN_20 | updateValids_1 & io_update_bits_meta[87] & _GEN_15 + & io_update_bits_meta[69]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_0_io_update_us_1_r <= ~_GEN_20 & updateProviderCorrect_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_0_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + tables_0_io_update_folded_hist_r_1_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_0_io_update_folded_hist_r_1_hist_7_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] end - if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pred_dup_0 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 - s3_pred_dup_0_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + tables_1_io_update_reset_u_0_REG <= updateResetU_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_1_io_update_mask_0_REG <= updateMask_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + if (updateMask_0_1 | updateMask_1_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :832:59] + tables_1_io_update_takens_0_r <= updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_1_io_update_alloc_0_r <= _GEN_14 & _GEN_9; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_1_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_1_io_update_uMask_0_r <= + _GEN_10 | updateValids_0 & io_update_bits_meta[84] & _GEN_5 + & io_update_bits_meta[68]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_1_io_update_us_0_r <= ~_GEN_10 & updateProviderCorrect; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_1_io_update_takens_1_r <= updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_1_io_update_alloc_1_r <= _GEN_26 & _GEN_21; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_1_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_1_io_update_uMask_1_r <= + _GEN_22 | updateValids_1 & io_update_bits_meta[87] & _GEN_17 + & io_update_bits_meta[69]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_1_io_update_us_1_r <= ~_GEN_22 & updateProviderCorrect_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_1_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + tables_1_io_update_folded_hist_r_1_hist_15_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_1_io_update_folded_hist_r_1_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_1_io_update_folded_hist_r_1_hist_1_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] end - if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s3_pred_dup_2 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 - s3_pred_dup_2_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + tables_2_io_update_reset_u_0_REG <= updateResetU_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_2_io_update_mask_0_REG <= updateMask_0_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + if (updateMask_0_2 | updateMask_1_2) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :832:59] + tables_2_io_update_takens_0_r <= updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_2_io_update_alloc_0_r <= _GEN_14 & _GEN_11; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_2_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_2_io_update_uMask_0_r <= + _GEN_12 | updateValids_0 & io_update_bits_meta[84] & _GEN_6 + & io_update_bits_meta[68]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_2_io_update_us_0_r <= ~_GEN_12 & updateProviderCorrect; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_2_io_update_takens_1_r <= updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_2_io_update_alloc_1_r <= _GEN_26 & _GEN_23; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_2_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_2_io_update_uMask_1_r <= + _GEN_24 | updateValids_1 & io_update_bits_meta[87] & _GEN_18 + & io_update_bits_meta[69]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_2_io_update_us_1_r <= ~_GEN_24 & updateProviderCorrect_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_2_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + tables_2_io_update_folded_hist_r_1_hist_17_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_2_io_update_folded_hist_r_1_hist_9_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_2_io_update_folded_hist_r_1_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] end - sc_enable_dup_REG <= io_ctrl_sc_enable; // src/main/scala/xiangshan/frontend/SC.scala:319:38 - sc_enable_dup_REG_1 <= io_ctrl_sc_enable; // src/main/scala/xiangshan/frontend/SC.scala:319:38 - scTables_0_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_0_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_0_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_0_io_update_oldCtrs_0_REG <= io_update_bits_meta[5:0]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_1_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_1_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_1_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_1_io_update_oldCtrs_0_REG <= io_update_bits_meta[11:6]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_2_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_2_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_2_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_2_io_update_oldCtrs_0_REG <= io_update_bits_meta[17:12]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_3_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_3_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_3_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_3_io_update_oldCtrs_0_REG <= io_update_bits_meta[23:18]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_0_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_0_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_0_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_0_io_update_oldCtrs_1_REG <= io_update_bits_meta[29:24]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_0_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - scTables_1_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_1_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_1_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_1_io_update_oldCtrs_1_REG <= io_update_bits_meta[35:30]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_1_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 - scTables_2_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_2_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_2_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_2_io_update_oldCtrs_1_REG <= io_update_bits_meta[41:36]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_2_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 - scTables_3_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 - scTables_3_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_3_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 - scTables_3_io_update_oldCtrs_1_REG <= io_update_bits_meta[47:42]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 - scTables_3_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 - scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist <= - io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + tables_3_io_update_reset_u_0_REG <= updateResetU_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_3_io_update_mask_0_REG <= updateMask_0_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + if (updateMask_0_3 | updateMask_1_3) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :832:59] + tables_3_io_update_takens_0_r <= updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_3_io_update_alloc_0_r <= _GEN_14 & (&allocate); // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_3_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_3_io_update_uMask_0_r <= + _GEN_13 | updateValids_0 & io_update_bits_meta[84] + & (&(io_update_bits_meta[83:82])) & io_update_bits_meta[68]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_3_io_update_us_0_r <= ~_GEN_13 & updateProviderCorrect; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_3_io_update_takens_1_r <= updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :838:49] + tables_3_io_update_alloc_1_r <= _GEN_26 & (&allocate_1); // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :839:48] + tables_3_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :840:50] + tables_3_io_update_uMask_1_r <= + _GEN_25 | updateValids_1 & io_update_bits_meta[87] + & (&(io_update_bits_meta[86:85])) & io_update_bits_meta[69]; // @[src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :842:48] + tables_3_io_update_us_1_r <= ~_GEN_25 & updateProviderCorrect_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :843:45] + tables_3_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] + tables_3_io_update_folded_hist_r_1_hist_16_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_3_io_update_folded_hist_r_1_hist_8_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + tables_3_io_update_folded_hist_r_1_hist_5_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + end + tables_0_io_update_reset_u_1_REG <= updateResetU_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_0_io_update_mask_1_REG <= updateMask_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + tables_1_io_update_reset_u_1_REG <= updateResetU_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_1_io_update_mask_1_REG <= updateMask_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + tables_2_io_update_reset_u_1_REG <= updateResetU_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_2_io_update_mask_1_REG <= updateMask_1_2; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + tables_3_io_update_reset_u_1_REG <= updateResetU_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :836:48] + tables_3_io_update_mask_1_REG <= updateMask_1_3; // @[src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :837:48] + REG_2_0 <= baseupdate_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:740:64, :850:31] + REG_2_1 <= baseupdate_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:740:64, :850:31] + if (baseupdate_0 | baseupdate_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:740:64, :851:65] + r_0 <= io_update_bits_meta[65:64]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :851:32] + r_1 <= io_update_bits_meta[67:66]; // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :851:32] + bt_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31] + r_1_0 <= updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :853:35] + r_1_1 <= updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:715:33, :853:35] + end + if (io_s2_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + resp_meta_scMeta_tageTakens_0_r <= s2_tageTakens_dup_3_0; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + resp_meta_scMeta_scUsed_0_r <= s2_provideds_0; // @[src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38] + resp_meta_scMeta_scPreds_0_r <= _GEN_30; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40] + r_2_0 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_0_ctrs_0_1 : s2_scResps_r_0_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_2_1 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_1_ctrs_0_1 : s2_scResps_r_1_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_2_2 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_2_ctrs_0_1 : s2_scResps_r_2_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_2_3 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_3_ctrs_0_1 : s2_scResps_r_3_ctrs_0_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + s3_pred_dup_3 <= s2_pred; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + resp_meta_scMeta_tageTakens_1_r <= s2_tageTakens_dup_3_1; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + resp_meta_scMeta_scUsed_1_r <= s2_provideds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38] + resp_meta_scMeta_scPreds_1_r <= _GEN_39; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40] + r_3_0 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_0_ctrs_1_1 : s2_scResps_r_1_0_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_3_1 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_1_ctrs_1_1 : s2_scResps_r_1_1_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_3_2 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_2_ctrs_1_1 : s2_scResps_r_1_2_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + r_3_3 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_3_ctrs_1_1 : s2_scResps_r_1_3_ctrs_1_0; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58] + s3_pred_dup_3_1 <= s2_pred_1; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + end + if (io_s2_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pred_dup_0 <= s2_pred; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + s3_pred_dup_0_1 <= s2_pred_1; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + end + if (io_s2_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s3_pred_dup_2 <= s2_pred; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + s3_pred_dup_2_1 <= s2_pred_1; // @[src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54] + end + sc_enable_dup_REG <= io_ctrl_sc_enable; // @[src/main/scala/xiangshan/frontend/SC.scala:319:38] + sc_enable_dup_REG_1 <= io_ctrl_sc_enable; // @[src/main/scala/xiangshan/frontend/SC.scala:319:38] + scTables_0_io_update_mask_0_REG <= scUpdateMask_0_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :375:63] + scTables_0_io_update_tagePreds_0_r <= io_update_bits_meta[52]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_0_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_0_io_update_oldCtrs_0_r <= io_update_bits_meta[5:0]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_0_io_update_tagePreds_1_r <= io_update_bits_meta[53]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_0_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_0_io_update_oldCtrs_1_r <= io_update_bits_meta[29:24]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_0_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + end + scTables_1_io_update_mask_0_REG <= scUpdateMask_0_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :375:63] + scTables_1_io_update_tagePreds_0_r <= io_update_bits_meta[52]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_1_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_1_io_update_oldCtrs_0_r <= io_update_bits_meta[11:6]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_1_io_update_tagePreds_1_r <= io_update_bits_meta[53]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_1_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_1_io_update_oldCtrs_1_r <= io_update_bits_meta[35:30]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_1_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + end + scTables_2_io_update_mask_0_REG <= scUpdateMask_0_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :375:63] + scTables_2_io_update_tagePreds_0_r <= io_update_bits_meta[52]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_2_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_2_io_update_oldCtrs_0_r <= io_update_bits_meta[17:12]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_2_io_update_tagePreds_1_r <= io_update_bits_meta[53]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_2_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_2_io_update_oldCtrs_1_r <= io_update_bits_meta[41:36]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_2_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + end + scTables_3_io_update_mask_0_REG <= scUpdateMask_0_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :375:63] + scTables_3_io_update_tagePreds_0_r <= io_update_bits_meta[52]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_3_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_3_io_update_oldCtrs_0_r <= io_update_bits_meta[23:18]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_3_io_update_tagePreds_1_r <= io_update_bits_meta[53]; // @[src/main/scala/xiangshan/frontend/SC.scala:380:56, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_3_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + scTables_3_io_update_oldCtrs_1_r <= io_update_bits_meta[47:42]; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + scTables_3_io_update_pc_r_1 <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + end + scTables_0_io_update_mask_1_REG <= scUpdateMask_1_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + scTables_1_io_update_mask_1_REG <= scUpdateMask_1_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + scTables_2_io_update_mask_1_REG <= scUpdateMask_1_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + scTables_3_io_update_mask_1_REG <= scUpdateMask_1_3; // @[src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :379:49] + io_perf_0_value_REG <= + 2'({1'h0, io_update_bits_meta[84]} + {1'h0, io_update_bits_meta[87]}); // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:403:48, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + io_perf_0_value_REG_1 <= io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_1_value_REG <= + 2'({1'h0, _GEN_35 & _update_on_mispred_0_T} + + {1'h0, _GEN_44 & _update_on_mispred_1_T}); // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:212:53, :328:56, :348:40, :357:55, :368:32, :393:54] + io_perf_1_value_REG_1 <= io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_2_value_REG <= + 2'({1'h0, _GEN_35 & io_update_bits_meta[48] == io_update_bits_br_taken_mask_0} + + {1'h0, _GEN_44 & io_update_bits_meta[49] == io_update_bits_br_taken_mask_1}); // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/SC.scala:212:53, :328:56, :347:40, :357:55, :368:32, :369:31, :394:53, src/main/scala/xiangshan/frontend/Tage.scala:618:40] + io_perf_2_value_REG_1 <= io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] end // always @(posedge) - wire [3:0] _allocFailureMask_T = ~(io_update_bits_meta[59:56]); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35 - wire [1:0] _GEN_43 = {1'h0, _allocFailureMask_T[0] & longerHistoryTableMask[0]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_44 = {1'h0, _allocFailureMask_T[1] & longerHistoryTableMask[1]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_45 = {1'h0, _allocFailureMask_T[2] & longerHistoryTableMask[2]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_46 = {1'h0, _allocFailureMask_T[3] & longerHistoryTableMask[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_47 = {1'h0, _firstEntry_T}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_48 = {1'h0, _firstEntry_T_1}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_49 = {1'h0, _firstEntry_T_2}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_50 = {1'h0, io_update_bits_meta[59] & longerHistoryTableMask[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire [3:0] _allocFailureMask_T = ~(io_update_bits_meta[59:56]); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35] + wire [1:0] _GEN_47 = {1'h0, _allocFailureMask_T[0] & longerHistoryTableMask[0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_48 = {1'h0, _allocFailureMask_T[1] & longerHistoryTableMask[1]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_49 = {1'h0, _allocFailureMask_T[2] & longerHistoryTableMask[2]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_50 = {1'h0, _allocFailureMask_T[3] & longerHistoryTableMask[3]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_51 = {1'h0, _firstEntry_T}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_52 = {1'h0, _firstEntry_T_1}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_53 = {1'h0, _firstEntry_T_2}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_54 = {1'h0, io_update_bits_meta[59] & longerHistoryTableMask[3]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] wire tickInc = - 3'({1'h0, 2'(_GEN_43 + _GEN_44)} - + {1'h0, - 2'(_GEN_45 - + _GEN_46)}) > 3'({1'h0, 2'(_GEN_47 + _GEN_48)} - + {1'h0, 2'(_GEN_49 + _GEN_50)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56} - wire [6:0] _GEN_51 = - {4'h0, - 3'(3'({1'h0, 2'(_GEN_43 + _GEN_44)} + {1'h0, 2'(_GEN_45 + _GEN_46)}) - - (3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35 - wire tickDec = 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 - + _GEN_50)}) > 3'({1'h0, 2'(_GEN_43 + _GEN_44)} - + {1'h0, 2'(_GEN_45 + _GEN_46)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52} - wire [6:0] _GEN_52 = + + _GEN_50)}) > 3'({1'h0, 2'(_GEN_51 + _GEN_52)} + + {1'h0, 2'(_GEN_53 + _GEN_54)}); // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56}] + wire [6:0] _GEN_55 = {4'h0, 3'(3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)}) - - (3'({1'h0, 2'(_GEN_43 + _GEN_44)} + {1'h0, 2'(_GEN_45 + _GEN_46)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35 - wire [3:0] _allocFailureMask_T_1 = ~(io_update_bits_meta[63:60]); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35 - wire [1:0] _GEN_53 = {1'h0, _allocFailureMask_T_1[0] & longerHistoryTableMask_1[0]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_54 = {1'h0, _allocFailureMask_T_1[1] & longerHistoryTableMask_1[1]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_55 = {1'h0, _allocFailureMask_T_1[2] & longerHistoryTableMask_1[2]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_56 = {1'h0, _allocFailureMask_T_1[3] & longerHistoryTableMask_1[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 - wire [1:0] _GEN_57 = {1'h0, _firstEntry_T_6}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_58 = {1'h0, _firstEntry_T_7}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_59 = {1'h0, _firstEntry_T_8}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 - wire [1:0] _GEN_60 = {1'h0, io_update_bits_meta[63] & longerHistoryTableMask_1[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} - wire tickInc_1 = - 3'({1'h0, 2'(_GEN_53 + _GEN_54)} + - (3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)})))}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35] + wire tickDec = + 3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, - 2'(_GEN_55 - + _GEN_56)}) > 3'({1'h0, 2'(_GEN_57 + _GEN_58)} - + {1'h0, 2'(_GEN_59 + _GEN_60)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56} - wire [6:0] _GEN_61 = + 2'(_GEN_53 + + _GEN_54)}) > 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + + {1'h0, 2'(_GEN_49 + _GEN_50)}); // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52}] + wire [6:0] _GEN_56 = {4'h0, - 3'(3'({1'h0, 2'(_GEN_53 + _GEN_54)} + {1'h0, 2'(_GEN_55 + _GEN_56)}) - - (3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35 - wire tickDec_1 = + 3'(3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)}) + - (3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})))}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35] + wire [3:0] _allocFailureMask_T_1 = ~(io_update_bits_meta[63:60]); // @[src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35] + wire [1:0] _GEN_57 = {1'h0, _allocFailureMask_T_1[0] & longerHistoryTableMask_1[0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_58 = {1'h0, _allocFailureMask_T_1[1] & longerHistoryTableMask_1[1]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_59 = {1'h0, _allocFailureMask_T_1[2] & longerHistoryTableMask_1[2]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_60 = {1'h0, _allocFailureMask_T_1[3] & longerHistoryTableMask_1[3]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27] + wire [1:0] _GEN_61 = {1'h0, _firstEntry_T_6}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_62 = {1'h0, _firstEntry_T_7}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_63 = {1'h0, _firstEntry_T_8}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56] + wire [1:0] _GEN_64 = {1'h0, io_update_bits_meta[63] & longerHistoryTableMask_1[3]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56}] + wire tickInc_1 = 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 - + _GEN_60)}) > 3'({1'h0, 2'(_GEN_53 + _GEN_54)} - + {1'h0, 2'(_GEN_55 + _GEN_56)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52} - wire [6:0] _GEN_62 = + + _GEN_60)}) > 3'({1'h0, 2'(_GEN_61 + _GEN_62)} + + {1'h0, 2'(_GEN_63 + _GEN_64)}); // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56}] + wire [6:0] _GEN_65 = {4'h0, 3'(3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)}) - - (3'({1'h0, 2'(_GEN_53 + _GEN_54)} + {1'h0, 2'(_GEN_55 + _GEN_56)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35 - wire _newThres_newCtr_T = (&scThresholds_0_ctr) & _update_on_mispred_0_T; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 - wire _newThres_newCtr_T_2 = scThresholds_0_ctr == 5'h0 & ~_update_on_mispred_0_T; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 - wire [4:0] _newThres_newCtr_T_3 = 5'(scThresholds_0_ctr + 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 - wire [4:0] _newThres_newCtr_T_5 = 5'(scThresholds_0_ctr - 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 - wire _GEN_63 = io_update_bits_meta[48] == io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + - (3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)})))}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35] + wire tickDec_1 = + 3'({1'h0, 2'(_GEN_61 + _GEN_62)} + + {1'h0, + 2'(_GEN_63 + + _GEN_64)}) > 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + + {1'h0, 2'(_GEN_59 + _GEN_60)}); // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52}] + wire [6:0] _GEN_66 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)}) + - (3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})))}; // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35] + wire _newThres_newCtr_T = (&scThresholds_0_ctr) & _update_on_mispred_0_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40] + wire _newThres_newCtr_T_2 = scThresholds_0_ctr == 5'h0 & ~_update_on_mispred_0_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40] + wire [4:0] _newThres_newCtr_T_3 = 5'(scThresholds_0_ctr + 5'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/SC.scala:229:52] + wire [4:0] _newThres_newCtr_T_5 = 5'(scThresholds_0_ctr - 5'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/SC.scala:229:52] + wire _GEN_67 = io_update_bits_meta[48] == io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40] wire [4:0] newThres_newCtr = _newThres_newCtr_T ? 5'h1F : _newThres_newCtr_T_2 ? 5'h0 - : _GEN_63 ? _newThres_newCtr_T_5 : _newThres_newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:{8,21}, :97:{10,26}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40 - wire _newThres_res_ctr_T_4 = newThres_newCtr == 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:96:8, :97:10, src/main/scala/xiangshan/frontend/SC.scala:182:42 - wire _newThres_newCtr_T_9 = (&scThresholds_1_ctr) & _update_on_mispred_1_T; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 + : _GEN_67 ? _newThres_newCtr_T_5 : _newThres_newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:{8,21}, :98:{10,26}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40] + wire _newThres_res_ctr_T_4 = newThres_newCtr == 5'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, :98:10, src/main/scala/xiangshan/frontend/SC.scala:182:42] + wire _newThres_newCtr_T_9 = (&scThresholds_1_ctr) & _update_on_mispred_1_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40] wire _newThres_newCtr_T_11 = - scThresholds_1_ctr == 5'h0 & ~_update_on_mispred_1_T; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 - wire [4:0] _newThres_newCtr_T_12 = 5'(scThresholds_1_ctr + 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 - wire [4:0] _newThres_newCtr_T_14 = 5'(scThresholds_1_ctr - 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 - wire _GEN_64 = io_update_bits_meta[49] == io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scThresholds_1_ctr == 5'h0 & ~_update_on_mispred_1_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40] + wire [4:0] _newThres_newCtr_T_12 = 5'(scThresholds_1_ctr + 5'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/SC.scala:229:52] + wire [4:0] _newThres_newCtr_T_14 = 5'(scThresholds_1_ctr - 5'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/SC.scala:229:52] + wire _GEN_68 = io_update_bits_meta[49] == io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40] wire [4:0] newThres_newCtr_1 = _newThres_newCtr_T_9 ? 5'h1F : _newThres_newCtr_T_11 ? 5'h0 - : _GEN_64 ? _newThres_newCtr_T_14 : _newThres_newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:{8,21}, :97:{10,26}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40 - wire _newThres_res_ctr_T_11 = newThres_newCtr_1 == 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:96:8, :97:10, src/main/scala/xiangshan/frontend/SC.scala:182:42 + : _GEN_68 ? _newThres_newCtr_T_14 : _newThres_newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:{8,21}, :98:{10,26}, :99:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40] + wire _newThres_res_ctr_T_11 = newThres_newCtr_1 == 5'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, :98:10, src/main/scala/xiangshan/frontend/SC.scala:182:42] wire [3:0] updateUseAltCtr = (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_0_0 : 4'h0) | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_0_1 : 4'h0) @@ -1660,16 +1709,16 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_0_124 : 4'h0) | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_0_125 : 4'h0) | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_0_126 : 4'h0) - | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_0_127 : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41 - wire updateAltCorrect = io_update_bits_meta[65] == bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42 - wire _GEN_65 = + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_0_127 : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41] + wire updateAltCorrect = io_update_bits_meta[65] == updateTaken; // @[src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42] + wire _GEN_69 = io_update_bits_meta[84] & (io_update_bits_meta[76:74] == 3'h4 | io_update_bits_meta[76:74] == 3'h3) - & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50 - wire _newCtr_T = (&updateUseAltCtr) & updateAltCorrect; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42 - wire _newCtr_T_2 = updateUseAltCtr == 4'h0 & ~updateAltCorrect; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42 - wire [3:0] _newCtr_T_3 = 4'(updateUseAltCtr + 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24 - wire [3:0] _newCtr_T_5 = 4'(updateUseAltCtr - 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:35 + & io_update_bits_meta[68]; // @[src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50] + wire _newCtr_T = (&updateUseAltCtr) & updateAltCorrect; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42] + wire _newCtr_T_2 = updateUseAltCtr == 4'h0 & ~updateAltCorrect; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42] + wire [3:0] _newCtr_T_3 = 4'(updateUseAltCtr + 4'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:99:24] + wire [3:0] _newCtr_T_5 = 4'(updateUseAltCtr - 4'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:99:35] wire [3:0] updateUseAltCtr_1 = (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_1_0 : 4'h0) | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_1_1 : 4'h0) @@ -1798,3730 +1847,3732 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_1_124 : 4'h0) | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_1_125 : 4'h0) | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_1_126 : 4'h0) - | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_1_127 : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41 - wire updateAltCorrect_1 = io_update_bits_meta[67] == bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42 - wire _GEN_66 = + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_1_127 : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41] + wire updateAltCorrect_1 = io_update_bits_meta[67] == updateTaken_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42] + wire _GEN_70 = io_update_bits_meta[87] & (io_update_bits_meta[81:79] == 3'h4 | io_update_bits_meta[81:79] == 3'h3) - & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50 - wire _newCtr_T_9 = (&updateUseAltCtr_1) & updateAltCorrect_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42 - wire _newCtr_T_11 = updateUseAltCtr_1 == 4'h0 & ~updateAltCorrect_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42 - wire [3:0] _newCtr_T_12 = 4'(updateUseAltCtr_1 + 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24 - wire [3:0] _newCtr_T_14 = 4'(updateUseAltCtr_1 - 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:35 - wire [9:0] _sumAbs_T_4 = $signed(sum) < 10'sh0 ? 10'(10'h0 - sum) : sum; // src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26 - wire [9:0] _sumAbs_T_9 = $signed(sum_1) < 10'sh0 ? 10'(10'h0 - sum_1) : sum_1; // src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26 - always @(posedge clock or posedge reset) begin - if (reset) begin - bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - useAltOnNaCtrs_0_0 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_1 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_2 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_3 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_4 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_5 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_6 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_7 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_8 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_9 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_10 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_11 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_12 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_13 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_14 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_15 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_16 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_17 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_18 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_19 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_20 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_21 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_22 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_23 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_24 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_25 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_26 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_27 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_28 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_29 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_30 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_31 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_32 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_33 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_34 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_35 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_36 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_37 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_38 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_39 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_40 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_41 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_42 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_43 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_44 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_45 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_46 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_47 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_48 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_49 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_50 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_51 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_52 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_53 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_54 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_55 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_56 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_57 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_58 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_59 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_60 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_61 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_62 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_63 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_64 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_65 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_66 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_67 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_68 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_69 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_70 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_71 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_72 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_73 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_74 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_75 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_76 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_77 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_78 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_79 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_80 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_81 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_82 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_83 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_84 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_85 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_86 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_87 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_88 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_89 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_90 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_91 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_92 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_93 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_94 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_95 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_96 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_97 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_98 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_99 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_100 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_101 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_102 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_103 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_104 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_105 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_106 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_107 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_108 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_109 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_110 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_111 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_112 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_113 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_114 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_115 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_116 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_117 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_118 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_119 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_120 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_121 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_122 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_123 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_124 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_125 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_126 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_127 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_0 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_1 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_2 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_3 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_4 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_5 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_6 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_7 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_8 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_9 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_10 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_11 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_12 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_13 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_14 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_15 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_16 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_17 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_18 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_19 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_20 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_21 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_22 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_23 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_24 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_25 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_26 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_27 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_28 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_29 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_30 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_31 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_32 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_33 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_34 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_35 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_36 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_37 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_38 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_39 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_40 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_41 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_42 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_43 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_44 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_45 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_46 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_47 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_48 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_49 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_50 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_51 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_52 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_53 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_54 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_55 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_56 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_57 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_58 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_59 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_60 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_61 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_62 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_63 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_64 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_65 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_66 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_67 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_68 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_69 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_70 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_71 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_72 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_73 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_74 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_75 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_76 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_77 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_78 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_79 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_80 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_81 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_82 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_83 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_84 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_85 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_86 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_87 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_88 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_89 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_90 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_91 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_92 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_93 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_94 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_95 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_96 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_97 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_98 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_99 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_100 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_101 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_102 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_103 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_104 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_105 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_106 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_107 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_108 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_109 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_110 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_111 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_112 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_113 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_114 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_115 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_116 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_117 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_118 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_119 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_120 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_121 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_122 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_123 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_124 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_125 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_126 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_127 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - allocLFSR_lfsr <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 - allocLFSR_lfsr_1 <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 - scThresholds_0_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - scThresholds_0_thres <= 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - scThresholds_1_thres <= 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + & io_update_bits_meta[69]; // @[src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50] + wire _newCtr_T_9 = (&updateUseAltCtr_1) & updateAltCorrect_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42] + wire _newCtr_T_11 = updateUseAltCtr_1 == 4'h0 & ~updateAltCorrect_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42] + wire [3:0] _newCtr_T_12 = 4'(updateUseAltCtr_1 + 4'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:99:24] + wire [3:0] _newCtr_T_14 = 4'(updateUseAltCtr_1 - 4'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:99:35] + wire [9:0] _sumAbs_T_4 = $signed(sum) < 10'sh0 ? 10'(10'h0 - sum) : sum; // @[src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26] + wire [9:0] _sumAbs_T_9 = $signed(sum_1) < 10'sh0 ? 10'(10'h0 - sum_1) : sum_1; // @[src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + bankTickCtrDistanceToTops_0 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrDistanceToTops_1 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_0 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + bankTickCtrs_1 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + useAltOnNaCtrs_0_0 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_1 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_2 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_3 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_4 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_5 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_6 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_7 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_8 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_9 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_10 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_11 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_12 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_13 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_14 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_15 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_16 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_17 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_18 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_19 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_20 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_21 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_22 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_23 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_24 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_25 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_26 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_27 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_28 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_29 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_30 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_31 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_32 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_33 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_34 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_35 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_36 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_37 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_38 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_39 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_40 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_41 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_42 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_43 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_44 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_45 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_46 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_47 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_48 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_49 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_50 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_51 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_52 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_53 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_54 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_55 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_56 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_57 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_58 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_59 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_60 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_61 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_62 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_63 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_64 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_65 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_66 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_67 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_68 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_69 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_70 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_71 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_72 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_73 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_74 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_75 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_76 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_77 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_78 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_79 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_80 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_81 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_82 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_83 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_84 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_85 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_86 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_87 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_88 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_89 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_90 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_91 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_92 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_93 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_94 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_95 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_96 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_97 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_98 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_99 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_100 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_101 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_102 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_103 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_104 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_105 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_106 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_107 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_108 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_109 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_110 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_111 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_112 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_113 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_114 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_115 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_116 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_117 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_118 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_119 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_120 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_121 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_122 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_123 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_124 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_125 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_126 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_127 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_0 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_1 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_2 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_3 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_4 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_5 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_6 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_7 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_8 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_9 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_10 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_11 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_12 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_13 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_14 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_15 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_16 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_17 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_18 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_19 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_20 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_21 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_22 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_23 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_24 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_25 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_26 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_27 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_28 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_29 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_30 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_31 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_32 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_33 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_34 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_35 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_36 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_37 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_38 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_39 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_40 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_41 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_42 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_43 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_44 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_45 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_46 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_47 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_48 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_49 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_50 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_51 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_52 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_53 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_54 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_55 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_56 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_57 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_58 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_59 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_60 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_61 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_62 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_63 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_64 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_65 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_66 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_67 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_68 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_69 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_70 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_71 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_72 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_73 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_74 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_75 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_76 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_77 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_78 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_79 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_80 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_81 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_82 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_83 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_84 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_85 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_86 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_87 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_88 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_89 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_90 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_91 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_92 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_93 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_94 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_95 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_96 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_97 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_98 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_99 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_100 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_101 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_102 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_103 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_104 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_105 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_106 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_107 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_108 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_109 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_110 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_111 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_112 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_113 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_114 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_115 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_116 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_117 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_118 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_119 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_120 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_121 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_122 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_123 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_124 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_125 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_126 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_127 <= 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + allocLFSR_lfsr <= 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + allocLFSR_lfsr_1 <= 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + scThresholds_0_ctr <= 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + scThresholds_0_thres <= 8'h6; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_ctr <= 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + scThresholds_1_thres <= 8'h6; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] end - else begin - if (needToAllocate) begin // src/main/scala/xiangshan/frontend/Tage.scala:770:53 - if (&bankTickCtrs_0) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29 - bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + if (needToAllocate) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:770:53] + if (&bankTickCtrs_0) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29] + bankTickCtrDistanceToTops_0 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_0 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] end - else if (tickInc) begin // src/main/scala/xiangshan/frontend/Tage.scala:778:46 - if (_GEN_51 >= bankTickCtrDistanceToTops_0 & tickInc) begin // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67} - bankTickCtrDistanceToTops_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 - bankTickCtrs_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + else if (tickInc) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:778:46] + if (_GEN_55 >= bankTickCtrDistanceToTops_0 & tickInc) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67}] + bankTickCtrDistanceToTops_0 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45] + bankTickCtrs_0 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45] end - else begin // src/main/scala/xiangshan/frontend/Tage.scala:782:67 - bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 - _GEN_51); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72 - bankTickCtrs_0 <= 7'(bankTickCtrs_0 + _GEN_51); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:782:67] + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 - _GEN_55); // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72] + bankTickCtrs_0 <= 7'(bankTickCtrs_0 + _GEN_55); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46] end end - else if (tickDec) begin // src/main/scala/xiangshan/frontend/Tage.scala:779:42 - if (_GEN_52 >= bankTickCtrs_0 & tickDec) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54} - bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + else if (tickDec) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:779:42] + if (_GEN_56 >= bankTickCtrs_0 & tickDec) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54}] + bankTickCtrDistanceToTops_0 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_0 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] end - else begin // src/main/scala/xiangshan/frontend/Tage.scala:783:54 - bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 + _GEN_52); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72 - bankTickCtrs_0 <= 7'(bankTickCtrs_0 - _GEN_52); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:783:54] + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 + _GEN_56); // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72] + bankTickCtrs_0 <= 7'(bankTickCtrs_0 - _GEN_56); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46] end end end - if (needToAllocate_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:770:53 - if (&bankTickCtrs_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29 - bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + if (needToAllocate_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:770:53] + if (&bankTickCtrs_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29] + bankTickCtrDistanceToTops_1 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_1 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] end - else if (tickInc_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:778:46 - if (_GEN_61 >= bankTickCtrDistanceToTops_1 & tickInc_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67} - bankTickCtrDistanceToTops_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 - bankTickCtrs_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + else if (tickInc_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:778:46] + if (_GEN_65 >= bankTickCtrDistanceToTops_1 & tickInc_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67}] + bankTickCtrDistanceToTops_1 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45] + bankTickCtrs_1 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45] end - else begin // src/main/scala/xiangshan/frontend/Tage.scala:782:67 - bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 - _GEN_61); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72 - bankTickCtrs_1 <= 7'(bankTickCtrs_1 + _GEN_61); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:782:67] + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 - _GEN_65); // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72] + bankTickCtrs_1 <= 7'(bankTickCtrs_1 + _GEN_65); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46] end end - else if (tickDec_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:779:42 - if (_GEN_62 >= bankTickCtrs_1 & tickDec_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54} - bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + else if (tickDec_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:779:42] + if (_GEN_66 >= bankTickCtrs_1 & tickDec_1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54}] + bankTickCtrDistanceToTops_1 <= 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_1 <= 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] end - else begin // src/main/scala/xiangshan/frontend/Tage.scala:783:54 - bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 + _GEN_62); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72 - bankTickCtrs_1 <= 7'(bankTickCtrs_1 - _GEN_62); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46 + else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:783:54] + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 + _GEN_66); // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72] + bankTickCtrs_1 <= 7'(bankTickCtrs_1 - _GEN_66); // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46] end end end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h0) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_0 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_0 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_0 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_0 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_1 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_1 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_1 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_1 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_2 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_2 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_2 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_2 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_3 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_3 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_3 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_3 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_4 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_4 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_4 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_4 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_5 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_5 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_5 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_5 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_6 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_6 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_6 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_6 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_7 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_7 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_7 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_7 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h8) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_8 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_8 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_8 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_8 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h9) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_9 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_9 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_9 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_9 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hA) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_10 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_10 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_10 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_10 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hB) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_11 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_11 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_11 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_11 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hC) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_12 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_12 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_12 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_12 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hD) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_13 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_13 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_13 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_13 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hE) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_14 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_14 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_14 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_14 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hF) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_15 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_15 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_15 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_15 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h10) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_16 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_16 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_16 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_16 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h11) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_17 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_17 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_17 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_17 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h12) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_18 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_18 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_18 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_18 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h13) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_19 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_19 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_19 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_19 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h14) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_20 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_20 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_20 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_20 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h15) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_21 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_21 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_21 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_21 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h16) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_22 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_22 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_22 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_22 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h17) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_23 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_23 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_23 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_23 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h18) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_24 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_24 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_24 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_24 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h19) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_25 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_25 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_25 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_25 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_26 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_26 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_26 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_26 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_27 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_27 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_27 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_27 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_28 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_28 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_28 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_28 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_29 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_29 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_29 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_29 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_30 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_30 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_30 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_30 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_31 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_31 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_31 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_31 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h20) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_32 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_32 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_32 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_32 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h21) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_33 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_33 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_33 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_33 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h22) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_34 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_34 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_34 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_34 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h23) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_35 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_35 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_35 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_35 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h24) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_36 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_36 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_36 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_36 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h25) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_37 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_37 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_37 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_37 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h26) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_38 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_38 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_38 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_38 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h27) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_39 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_39 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_39 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_39 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h28) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_40 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_40 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_40 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_40 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h29) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_41 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_41 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_41 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_41 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_42 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_42 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_42 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_42 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_43 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_43 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_43 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_43 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_44 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_44 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_44 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_44 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_45 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_45 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_45 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_45 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_46 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_46 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_46 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_46 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_47 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_47 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_47 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_47 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h30) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_48 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_48 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_48 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_48 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h31) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_49 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_49 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_49 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_49 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h32) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_50 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_50 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_50 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_50 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h33) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_51 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_51 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_51 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_51 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h34) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_52 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_52 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_52 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_52 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h35) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_53 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_53 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_53 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_53 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h36) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_54 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_54 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_54 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_54 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h37) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_55 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_55 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_55 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_55 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h38) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_56 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_56 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_56 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_56 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h39) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_57 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_57 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_57 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_57 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_58 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_58 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_58 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_58 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_59 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_59 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_59 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_59 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_60 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_60 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_60 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_60 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_61 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_61 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_61 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_61 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_62 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_62 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_62 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_62 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_63 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_63 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_63 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_63 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h40) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_64 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_64 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_64 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_64 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h41) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_65 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_65 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_65 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_65 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h42) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_66 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_66 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_66 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_66 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h43) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_67 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_67 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_67 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_67 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h44) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_68 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_68 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_68 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_68 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h45) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_69 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_69 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_69 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_69 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h46) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_70 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_70 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_70 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_70 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h47) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_71 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_71 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_71 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_71 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h48) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_72 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_72 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_72 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_72 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h49) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_73 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_73 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_73 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_73 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_74 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_74 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_74 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_74 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_75 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_75 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_75 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_75 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_76 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_76 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_76 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_76 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_77 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_77 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_77 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_77 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_78 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_78 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_78 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_78 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_79 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_79 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_79 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_79 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h50) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_80 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_80 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_80 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_80 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h51) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_81 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_81 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_81 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_81 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h52) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_82 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_82 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_82 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_82 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h53) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_83 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_83 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_83 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_83 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h54) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_84 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_84 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_84 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_84 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h55) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_85 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_85 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_85 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_85 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h56) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_86 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_86 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_86 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_86 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h57) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_87 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_87 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_87 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_87 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h58) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_88 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_88 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_88 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_88 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h59) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_89 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_89 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_89 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_89 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_90 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_90 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_90 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_90 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_91 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_91 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_91 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_91 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_92 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_92 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_92 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_92 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_93 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_93 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_93 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_93 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_94 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_94 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_94 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_94 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_95 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_95 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_95 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_95 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h60) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_96 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_96 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_96 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_96 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h61) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_97 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_97 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_97 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_97 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h62) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_98 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_98 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_98 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_98 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h63) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_99 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_99 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_99 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_99 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h64) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_100 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_100 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_100 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_100 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h65) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_101 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_101 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_101 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_101 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h66) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_102 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_102 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_102 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_102 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h67) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_103 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_103 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_103 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_103 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h68) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_104 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_104 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_104 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_104 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h69) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_105 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_105 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_105 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_105 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_106 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_106 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_106 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_106 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_107 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_107 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_107 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_107 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_108 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_108 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_108 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_108 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_109 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_109 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_109 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_109 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_110 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_110 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_110 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_110 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_111 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_111 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_111 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_111 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h70) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_112 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_112 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_112 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_112 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h71) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_113 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_113 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_113 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_113 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h72) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_114 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_114 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_114 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_114 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h73) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_115 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_115 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_115 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_115 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h74) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_116 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_116 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_116 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_116 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h75) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_117 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_117 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_117 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_117 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h76) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_118 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_118 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_118 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_118 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h77) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_119 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_119 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_119 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_119 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h78) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_120 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_120 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_120 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_120 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h79) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_121 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_121 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_121 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_121 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_122 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_122 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_122 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_122 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_123 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_123 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_123 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_123 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_124 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_124 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_124 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_124 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_125 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_125 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_125 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_125 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_126 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_126 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_126 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_126 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_0 & _GEN_65 & (&(io_update_bits_pc[7:1]))) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_0_127 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_0_127 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_127 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_0_127 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h0) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_0 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_0 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_0 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_0 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_1 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_1 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_1 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_1 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_2 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_2 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_2 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_2 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_3 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_3 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_3 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_3 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_4 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_4 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_4 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_4 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_5 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_5 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_5 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_5 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_6 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_6 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_6 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_6 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_7 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_7 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_7 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_7 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h8) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_8 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_8 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_8 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_8 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h9) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_9 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_9 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_9 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_9 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hA) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_10 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_10 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_10 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_10 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hB) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_11 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_11 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_11 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_11 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hC) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_12 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_12 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_12 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_12 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hD) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_13 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_13 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_13 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_13 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hE) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_14 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_14 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_14 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_14 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hF) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_15 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_15 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_15 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_15 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h10) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_16 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_16 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_16 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_16 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h11) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_17 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_17 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_17 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_17 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h12) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_18 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_18 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_18 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_18 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h13) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_19 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_19 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_19 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_19 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h14) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_20 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_20 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_20 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_20 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h15) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_21 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_21 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_21 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_21 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h16) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_22 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_22 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_22 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_22 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h17) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_23 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_23 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_23 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_23 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h18) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_24 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_24 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_24 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_24 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h19) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_25 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_25 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_25 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_25 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_26 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_26 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_26 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_26 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_27 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_27 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_27 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_27 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_28 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_28 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_28 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_28 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_29 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_29 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_29 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_29 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_30 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_30 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_30 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_30 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_31 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_31 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_31 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_31 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h20) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_32 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_32 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_32 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_32 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h21) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_33 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_33 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_33 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_33 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h22) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_34 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_34 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_34 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_34 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h23) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_35 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_35 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_35 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_35 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h24) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_36 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_36 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_36 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_36 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h25) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_37 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_37 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_37 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_37 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h26) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_38 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_38 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_38 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_38 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h27) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_39 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_39 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_39 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_39 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h28) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_40 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_40 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_40 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_40 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h29) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_41 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_41 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_41 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_41 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_42 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_42 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_42 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_42 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_43 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_43 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_43 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_43 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_44 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_44 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_44 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_44 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_45 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_45 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_45 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_45 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_46 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_46 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_46 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_46 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_47 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_47 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_47 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_47 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h30) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_48 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_48 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_48 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_48 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h31) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_49 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_49 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_49 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_49 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h32) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_50 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_50 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_50 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_50 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h33) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_51 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_51 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_51 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_51 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h34) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_52 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_52 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_52 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_52 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h35) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_53 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_53 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_53 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_53 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h36) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_54 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_54 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_54 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_54 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h37) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_55 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_55 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_55 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_55 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h38) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_56 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_56 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_56 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_56 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h39) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_57 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_57 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_57 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_57 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_58 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_58 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_58 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_58 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_59 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_59 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_59 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_59 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_60 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_60 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_60 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_60 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_61 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_61 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_61 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_61 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_62 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_62 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_62 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_62 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_63 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_63 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_63 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_63 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h40) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_64 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_64 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_64 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_64 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h41) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_65 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_65 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_65 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_65 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h42) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_66 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_66 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_66 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_66 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h43) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_67 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_67 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_67 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_67 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h44) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_68 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_68 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_68 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_68 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h45) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_69 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_69 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_69 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_69 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h46) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_70 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_70 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_70 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_70 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h47) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_71 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_71 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_71 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_71 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h48) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_72 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_72 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_72 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_72 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h49) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_73 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_73 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_73 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_73 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_74 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_74 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_74 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_74 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_75 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_75 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_75 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_75 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_76 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_76 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_76 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_76 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_77 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_77 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_77 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_77 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_78 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_78 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_78 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_78 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_79 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_79 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_79 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_79 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h50) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_80 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_80 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_80 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_80 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h51) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_81 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_81 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_81 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_81 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h52) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_82 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_82 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_82 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_82 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h53) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_83 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_83 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_83 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_83 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h54) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_84 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_84 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_84 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_84 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h55) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_85 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_85 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_85 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_85 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h56) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_86 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_86 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_86 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_86 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h57) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_87 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_87 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_87 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_87 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h58) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_88 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_88 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_88 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_88 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h59) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_89 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_89 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_89 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_89 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_90 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_90 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_90 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_90 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_91 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_91 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_91 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_91 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_92 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_92 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_92 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_92 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_93 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_93 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_93 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_93 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_94 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_94 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_94 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_94 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_95 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_95 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_95 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_95 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h60) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_96 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_96 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_96 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_96 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h61) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_97 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_97 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_97 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_97 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h62) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_98 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_98 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_98 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_98 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h63) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_99 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_99 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_99 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_99 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h64) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_100 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_100 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_100 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_100 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h65) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_101 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_101 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_101 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_101 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h66) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_102 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_102 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_102 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_102 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h67) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_103 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_103 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_103 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_103 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h68) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_104 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_104 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_104 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_104 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h69) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_105 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_105 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_105 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_105 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_106 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_106 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_106 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_106 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_107 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_107 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_107 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_107 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_108 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_108 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_108 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_108 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_109 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_109 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_109 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_109 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_110 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_110 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_110 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_110 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_111 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_111 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_111 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_111 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h70) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_112 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_112 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_112 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_112 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h71) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_113 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_113 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_113 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_113 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h72) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_114 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_114 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_114 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_114 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h73) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_115 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_115 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_115 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_115 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h74) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_116 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_116 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_116 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_116 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h75) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_117 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_117 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_117 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_117 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h76) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_118 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_118 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_118 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_118 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h77) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_119 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_119 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_119 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_119 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h78) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_120 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_120 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_120 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_120 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h79) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_121 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_121 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_121 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_121 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_122 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_122 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_122 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_122 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_123 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_123 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_123 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_123 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_124 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_124 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_124 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_124 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_125 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_125 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_125 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_125 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_126 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_126 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_126 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_126 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (updateValids_1 & _GEN_66 & (&(io_update_bits_pc[7:1]))) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 - if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - useAltOnNaCtrs_1_127 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - useAltOnNaCtrs_1_127 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 - else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_127 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 - useAltOnNaCtrs_1_127 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 - end - if (allocLFSR_lfsr == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 - allocLFSR_lfsr <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 - else // utility/src/main/scala/utility/LFSR64.scala:31:24 + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h0) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_0 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_0 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_0 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_0 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_1 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_1 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_1 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_1 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_2 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_2 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_2 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_2 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_3 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_3 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_3 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_3 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_4 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_4 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_4 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_4 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_5 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_5 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_5 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_5 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_6 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_6 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_6 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_6 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_7 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_7 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_7 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_7 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h8) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_8 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_8 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_8 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_8 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h9) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_9 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_9 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_9 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_9 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hA) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_10 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_10 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_10 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_10 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hB) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_11 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_11 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_11 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_11 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hC) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_12 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_12 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_12 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_12 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hD) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_13 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_13 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_13 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_13 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hE) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_14 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_14 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_14 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_14 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hF) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_15 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_15 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_15 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_15 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h10) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_16 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_16 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_16 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_16 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h11) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_17 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_17 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_17 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_17 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h12) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_18 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_18 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_18 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_18 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h13) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_19 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_19 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_19 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_19 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h14) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_20 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_20 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_20 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_20 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h15) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_21 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_21 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_21 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_21 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h16) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_22 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_22 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_22 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_22 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h17) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_23 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_23 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_23 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_23 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h18) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_24 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_24 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_24 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_24 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h19) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_25 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_25 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_25 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_25 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_26 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_26 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_26 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_26 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_27 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_27 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_27 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_27 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_28 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_28 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_28 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_28 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_29 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_29 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_29 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_29 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_30 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_30 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_30 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_30 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_31 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_31 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_31 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_31 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h20) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_32 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_32 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_32 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_32 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h21) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_33 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_33 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_33 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_33 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h22) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_34 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_34 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_34 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_34 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h23) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_35 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_35 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_35 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_35 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h24) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_36 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_36 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_36 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_36 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h25) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_37 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_37 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_37 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_37 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h26) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_38 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_38 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_38 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_38 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h27) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_39 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_39 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_39 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_39 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h28) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_40 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_40 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_40 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_40 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h29) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_41 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_41 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_41 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_41 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_42 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_42 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_42 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_42 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_43 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_43 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_43 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_43 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_44 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_44 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_44 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_44 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_45 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_45 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_45 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_45 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_46 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_46 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_46 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_46 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_47 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_47 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_47 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_47 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h30) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_48 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_48 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_48 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_48 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h31) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_49 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_49 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_49 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_49 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h32) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_50 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_50 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_50 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_50 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h33) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_51 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_51 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_51 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_51 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h34) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_52 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_52 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_52 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_52 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h35) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_53 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_53 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_53 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_53 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h36) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_54 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_54 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_54 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_54 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h37) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_55 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_55 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_55 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_55 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h38) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_56 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_56 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_56 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_56 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h39) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_57 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_57 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_57 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_57 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_58 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_58 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_58 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_58 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_59 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_59 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_59 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_59 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_60 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_60 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_60 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_60 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_61 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_61 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_61 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_61 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_62 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_62 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_62 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_62 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_63 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_63 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_63 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_63 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h40) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_64 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_64 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_64 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_64 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h41) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_65 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_65 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_65 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_65 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h42) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_66 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_66 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_66 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_66 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h43) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_67 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_67 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_67 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_67 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h44) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_68 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_68 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_68 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_68 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h45) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_69 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_69 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_69 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_69 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h46) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_70 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_70 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_70 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_70 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h47) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_71 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_71 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_71 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_71 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h48) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_72 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_72 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_72 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_72 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h49) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_73 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_73 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_73 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_73 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_74 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_74 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_74 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_74 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_75 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_75 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_75 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_75 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_76 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_76 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_76 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_76 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_77 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_77 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_77 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_77 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_78 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_78 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_78 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_78 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_79 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_79 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_79 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_79 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h50) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_80 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_80 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_80 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_80 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h51) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_81 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_81 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_81 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_81 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h52) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_82 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_82 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_82 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_82 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h53) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_83 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_83 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_83 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_83 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h54) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_84 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_84 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_84 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_84 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h55) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_85 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_85 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_85 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_85 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h56) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_86 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_86 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_86 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_86 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h57) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_87 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_87 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_87 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_87 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h58) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_88 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_88 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_88 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_88 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h59) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_89 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_89 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_89 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_89 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_90 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_90 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_90 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_90 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_91 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_91 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_91 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_91 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_92 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_92 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_92 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_92 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_93 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_93 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_93 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_93 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_94 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_94 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_94 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_94 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_95 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_95 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_95 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_95 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h60) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_96 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_96 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_96 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_96 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h61) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_97 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_97 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_97 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_97 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h62) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_98 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_98 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_98 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_98 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h63) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_99 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_99 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_99 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_99 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h64) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_100 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_100 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_100 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_100 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h65) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_101 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_101 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_101 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_101 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h66) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_102 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_102 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_102 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_102 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h67) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_103 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_103 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_103 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_103 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h68) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_104 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_104 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_104 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_104 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h69) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_105 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_105 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_105 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_105 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_106 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_106 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_106 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_106 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_107 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_107 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_107 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_107 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_108 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_108 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_108 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_108 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_109 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_109 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_109 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_109 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_110 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_110 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_110 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_110 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_111 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_111 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_111 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_111 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h70) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_112 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_112 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_112 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_112 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h71) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_113 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_113 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_113 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_113 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h72) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_114 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_114 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_114 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_114 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h73) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_115 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_115 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_115 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_115 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h74) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_116 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_116 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_116 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_116 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h75) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_117 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_117 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_117 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_117 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h76) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_118 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_118 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_118 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_118 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h77) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_119 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_119 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_119 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_119 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h78) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_120 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_120 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_120 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_120 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h79) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_121 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_121 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_121 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_121 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_122 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_122 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_122 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_122 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_123 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_123 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_123 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_123 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_124 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_124 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_124 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_124 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_125 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_125 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_125 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_125 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_126 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_126 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_126 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_126 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_0 & _GEN_69 & (&(io_update_bits_pc[7:1]))) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_0_127 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_0_127 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_127 <= _newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_0_127 <= _newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h0) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_0 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_0 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_0 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_0 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_1 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_1 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_1 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_1 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_2 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_2 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_2 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_2 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_3 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_3 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_3 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_3 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_4 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_4 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_4 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_4 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_5 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_5 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_5 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_5 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_6 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_6 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_6 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_6 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_7 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_7 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_7 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_7 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h8) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_8 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_8 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_8 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_8 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h9) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_9 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_9 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_9 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_9 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hA) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_10 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_10 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_10 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_10 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hB) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_11 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_11 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_11 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_11 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hC) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_12 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_12 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_12 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_12 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hD) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_13 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_13 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_13 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_13 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hE) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_14 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_14 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_14 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_14 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hF) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_15 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_15 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_15 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_15 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h10) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_16 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_16 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_16 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_16 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h11) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_17 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_17 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_17 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_17 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h12) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_18 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_18 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_18 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_18 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h13) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_19 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_19 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_19 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_19 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h14) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_20 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_20 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_20 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_20 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h15) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_21 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_21 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_21 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_21 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h16) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_22 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_22 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_22 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_22 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h17) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_23 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_23 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_23 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_23 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h18) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_24 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_24 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_24 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_24 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h19) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_25 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_25 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_25 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_25 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_26 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_26 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_26 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_26 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_27 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_27 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_27 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_27 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_28 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_28 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_28 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_28 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_29 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_29 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_29 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_29 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_30 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_30 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_30 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_30 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_31 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_31 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_31 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_31 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h20) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_32 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_32 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_32 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_32 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h21) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_33 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_33 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_33 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_33 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h22) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_34 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_34 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_34 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_34 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h23) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_35 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_35 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_35 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_35 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h24) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_36 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_36 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_36 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_36 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h25) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_37 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_37 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_37 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_37 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h26) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_38 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_38 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_38 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_38 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h27) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_39 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_39 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_39 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_39 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h28) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_40 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_40 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_40 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_40 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h29) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_41 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_41 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_41 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_41 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_42 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_42 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_42 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_42 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_43 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_43 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_43 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_43 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_44 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_44 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_44 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_44 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_45 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_45 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_45 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_45 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_46 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_46 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_46 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_46 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_47 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_47 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_47 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_47 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h30) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_48 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_48 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_48 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_48 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h31) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_49 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_49 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_49 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_49 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h32) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_50 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_50 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_50 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_50 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h33) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_51 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_51 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_51 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_51 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h34) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_52 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_52 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_52 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_52 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h35) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_53 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_53 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_53 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_53 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h36) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_54 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_54 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_54 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_54 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h37) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_55 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_55 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_55 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_55 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h38) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_56 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_56 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_56 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_56 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h39) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_57 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_57 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_57 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_57 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_58 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_58 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_58 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_58 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_59 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_59 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_59 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_59 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_60 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_60 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_60 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_60 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_61 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_61 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_61 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_61 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_62 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_62 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_62 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_62 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_63 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_63 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_63 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_63 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h40) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_64 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_64 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_64 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_64 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h41) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_65 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_65 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_65 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_65 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h42) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_66 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_66 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_66 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_66 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h43) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_67 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_67 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_67 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_67 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h44) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_68 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_68 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_68 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_68 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h45) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_69 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_69 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_69 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_69 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h46) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_70 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_70 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_70 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_70 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h47) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_71 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_71 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_71 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_71 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h48) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_72 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_72 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_72 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_72 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h49) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_73 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_73 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_73 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_73 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_74 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_74 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_74 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_74 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_75 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_75 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_75 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_75 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_76 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_76 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_76 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_76 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_77 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_77 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_77 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_77 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_78 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_78 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_78 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_78 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_79 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_79 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_79 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_79 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h50) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_80 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_80 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_80 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_80 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h51) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_81 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_81 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_81 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_81 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h52) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_82 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_82 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_82 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_82 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h53) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_83 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_83 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_83 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_83 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h54) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_84 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_84 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_84 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_84 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h55) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_85 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_85 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_85 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_85 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h56) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_86 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_86 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_86 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_86 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h57) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_87 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_87 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_87 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_87 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h58) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_88 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_88 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_88 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_88 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h59) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_89 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_89 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_89 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_89 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_90 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_90 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_90 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_90 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_91 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_91 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_91 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_91 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_92 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_92 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_92 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_92 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_93 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_93 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_93 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_93 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_94 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_94 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_94 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_94 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_95 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_95 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_95 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_95 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h60) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_96 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_96 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_96 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_96 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h61) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_97 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_97 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_97 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_97 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h62) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_98 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_98 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_98 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_98 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h63) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_99 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_99 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_99 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_99 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h64) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_100 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_100 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_100 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_100 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h65) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_101 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_101 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_101 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_101 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h66) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_102 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_102 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_102 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_102 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h67) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_103 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_103 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_103 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_103 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h68) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_104 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_104 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_104 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_104 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h69) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_105 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_105 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_105 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_105 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_106 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_106 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_106 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_106 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_107 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_107 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_107 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_107 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_108 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_108 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_108 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_108 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_109 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_109 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_109 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_109 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_110 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_110 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_110 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_110 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6F) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_111 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_111 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_111 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_111 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h70) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_112 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_112 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_112 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_112 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h71) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_113 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_113 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_113 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_113 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h72) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_114 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_114 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_114 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_114 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h73) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_115 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_115 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_115 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_115 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h74) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_116 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_116 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_116 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_116 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h75) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_117 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_117 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_117 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_117 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h76) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_118 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_118 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_118 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_118 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h77) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_119 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_119 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_119 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_119 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h78) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_120 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_120 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_120 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_120 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h79) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_121 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_121 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_121 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_121 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7A) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_122 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_122 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_122 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_122 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7B) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_123 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_123 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_123 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_123 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7C) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_124 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_124 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_124 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_124 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7D) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_125 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_125 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_125 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_125 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7E) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_126 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_126 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_126 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_126 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (updateValids_1 & _GEN_70 & (&(io_update_bits_pc[7:1]))) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41] + if (_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + useAltOnNaCtrs_1_127 <= 4'hF; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + useAltOnNaCtrs_1_127 <= 4'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17] + else if (updateAltCorrect_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_127 <= _newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + else // @[src/main/scala/xiangshan/frontend/Tage.scala:726:42] + useAltOnNaCtrs_1_127 <= _newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31] + end + if (allocLFSR_lfsr == 64'h0) // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24] + allocLFSR_lfsr <= 64'h1; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18] + else // @[utility/src/main/scala/utility/LFSR64.scala:31:24] allocLFSR_lfsr <= {allocLFSR_lfsr[0] ^ allocLFSR_lfsr[1] ^ allocLFSR_lfsr[3] ^ allocLFSR_lfsr[4], - allocLFSR_lfsr[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} - if (allocLFSR_lfsr_1 == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 - allocLFSR_lfsr_1 <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 - else // utility/src/main/scala/utility/LFSR64.scala:31:24 + allocLFSR_lfsr[63:1]}; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51}] + if (allocLFSR_lfsr_1 == 64'h0) // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24] + allocLFSR_lfsr_1 <= 64'h1; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18] + else // @[utility/src/main/scala/utility/LFSR64.scala:31:24] allocLFSR_lfsr_1 <= {allocLFSR_lfsr_1[0] ^ allocLFSR_lfsr_1[1] ^ allocLFSR_lfsr_1[3] ^ allocLFSR_lfsr_1[4], - allocLFSR_lfsr_1[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} + allocLFSR_lfsr_1[63:1]}; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51}] if (_GEN_1 & io_update_bits_meta[48] != io_update_bits_meta[52] & _sumAbs_T_4 >= {2'h0, 8'(scThresholds_0_thres - 8'h4)} - & _sumAbs_T_4 <= {2'h0, 8'(scThresholds_0_thres - 8'h2)}) begin // src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26 - if ((&newThres_newCtr) | _newThres_res_ctr_T_4) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39 - scThresholds_0_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - else if (_newThres_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - scThresholds_0_ctr <= 5'h1F; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else if (_newThres_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - scThresholds_0_ctr <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else if (_GEN_63) // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 - scThresholds_0_ctr <= _newThres_newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 - scThresholds_0_ctr <= _newThres_newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 - if ((&newThres_newCtr) & scThresholds_0_thres < 8'h20) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_0_thres <= 8'(scThresholds_0_thres + 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - else if (_newThres_res_ctr_T_4 & scThresholds_0_thres > 8'h5) // src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_0_thres <= 8'(scThresholds_0_thres - 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52 + & _sumAbs_T_4 <= {2'h0, 8'(scThresholds_0_thres - 8'h2)}) begin // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26] + if ((&newThres_newCtr) | _newThres_res_ctr_T_4) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39] + scThresholds_0_ctr <= 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + else if (_newThres_newCtr_T) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + scThresholds_0_ctr <= 5'h1F; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else if (_newThres_newCtr_T_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + scThresholds_0_ctr <= 5'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else if (_GEN_67) // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40] + scThresholds_0_ctr <= _newThres_newCtr_T_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40] + scThresholds_0_ctr <= _newThres_newCtr_T_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/SC.scala:229:52] + if ((&newThres_newCtr) & scThresholds_0_thres < 8'h20) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_0_thres <= 8'(scThresholds_0_thres + 8'h2); // @[src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + else if (_newThres_res_ctr_T_4 & scThresholds_0_thres > 8'h5) // @[src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_0_thres <= 8'(scThresholds_0_thres - 8'h2); // @[src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52] end if (_GEN_2 & io_update_bits_meta[49] != io_update_bits_meta[53] & _sumAbs_T_9 >= {2'h0, 8'(scThresholds_1_thres - 8'h4)} - & _sumAbs_T_9 <= {2'h0, 8'(scThresholds_1_thres - 8'h2)}) begin // src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26 - if ((&newThres_newCtr_1) | _newThres_res_ctr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39 - scThresholds_1_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - else if (_newThres_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 - scThresholds_1_ctr <= 5'h1F; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else if (_newThres_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 - scThresholds_1_ctr <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else if (_GEN_64) // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 - scThresholds_1_ctr <= _newThres_newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 - else // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 - scThresholds_1_ctr <= _newThres_newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 - if ((&newThres_newCtr_1) & scThresholds_1_thres < 8'h20) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_thres <= 8'(scThresholds_1_thres + 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - else if (_newThres_res_ctr_T_11 & scThresholds_1_thres > 8'h5) // src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_thres <= 8'(scThresholds_1_thres - 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52 + & _sumAbs_T_9 <= {2'h0, 8'(scThresholds_1_thres - 8'h2)}) begin // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26] + if ((&newThres_newCtr_1) | _newThres_res_ctr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39] + scThresholds_1_ctr <= 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + else if (_newThres_newCtr_T_9) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:21] + scThresholds_1_ctr <= 5'h1F; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else if (_newThres_newCtr_T_11) // @[src/main/scala/xiangshan/frontend/BPU.scala:98:26] + scThresholds_1_ctr <= 5'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else if (_GEN_68) // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40] + scThresholds_1_ctr <= _newThres_newCtr_T_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/SC.scala:229:52] + else // @[src/main/scala/xiangshan/frontend/BPU.scala:99:12, src/main/scala/xiangshan/frontend/SC.scala:348:40] + scThresholds_1_ctr <= _newThres_newCtr_T_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/SC.scala:229:52] + if ((&newThres_newCtr_1) & scThresholds_1_thres < 8'h20) // @[src/main/scala/xiangshan/frontend/BPU.scala:97:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_thres <= 8'(scThresholds_1_thres + 8'h2); // @[src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + else if (_newThres_res_ctr_T_11 & scThresholds_1_thres > 8'h5) // @[src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_thres <= 8'(scThresholds_1_thres - 8'h2); // @[src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52] end end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:231]; // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - initial begin // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + logic [31:0] _RANDOM[0:233]; // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - for (logic [7:0] i = 8'h0; i < 8'hE8; i += 8'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - end // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s1_pc_dup_0 = {_RANDOM[8'h0], _RANDOM[8'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - REG = _RANDOM[8'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - REG_1 = _RANDOM[8'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24}, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - bankTickCtrDistanceToTops_0 = _RANDOM[8'hE][28:22]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :924:7 - bankTickCtrDistanceToTops_1 = {_RANDOM[8'hE][31:29], _RANDOM[8'hF][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :924:7 - bankTickCtrs_0 = _RANDOM[8'hF][10:4]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45, :924:7 - bankTickCtrs_1 = _RANDOM[8'hF][17:11]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45, :924:7 - useAltOnNaCtrs_0_0 = _RANDOM[8'hF][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 - useAltOnNaCtrs_0_1 = _RANDOM[8'hF][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 - useAltOnNaCtrs_0_2 = _RANDOM[8'hF][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 - useAltOnNaCtrs_0_3 = {_RANDOM[8'hF][31:30], _RANDOM[8'h10][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 - useAltOnNaCtrs_0_4 = _RANDOM[8'h10][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_5 = _RANDOM[8'h10][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_6 = _RANDOM[8'h10][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_7 = _RANDOM[8'h10][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_8 = _RANDOM[8'h10][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_9 = _RANDOM[8'h10][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_10 = _RANDOM[8'h10][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_11 = {_RANDOM[8'h10][31:30], _RANDOM[8'h11][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_12 = _RANDOM[8'h11][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_13 = _RANDOM[8'h11][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_14 = _RANDOM[8'h11][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_15 = _RANDOM[8'h11][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_16 = _RANDOM[8'h11][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_17 = _RANDOM[8'h11][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_18 = _RANDOM[8'h11][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_19 = {_RANDOM[8'h11][31:30], _RANDOM[8'h12][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_20 = _RANDOM[8'h12][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_21 = _RANDOM[8'h12][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_22 = _RANDOM[8'h12][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_23 = _RANDOM[8'h12][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_24 = _RANDOM[8'h12][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_25 = _RANDOM[8'h12][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_26 = _RANDOM[8'h12][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_27 = {_RANDOM[8'h12][31:30], _RANDOM[8'h13][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_28 = _RANDOM[8'h13][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_29 = _RANDOM[8'h13][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_30 = _RANDOM[8'h13][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_31 = _RANDOM[8'h13][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_32 = _RANDOM[8'h13][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_33 = _RANDOM[8'h13][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_34 = _RANDOM[8'h13][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_35 = {_RANDOM[8'h13][31:30], _RANDOM[8'h14][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_36 = _RANDOM[8'h14][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_37 = _RANDOM[8'h14][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_38 = _RANDOM[8'h14][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_39 = _RANDOM[8'h14][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_40 = _RANDOM[8'h14][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_41 = _RANDOM[8'h14][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_42 = _RANDOM[8'h14][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_43 = {_RANDOM[8'h14][31:30], _RANDOM[8'h15][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_44 = _RANDOM[8'h15][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_45 = _RANDOM[8'h15][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_46 = _RANDOM[8'h15][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_47 = _RANDOM[8'h15][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_48 = _RANDOM[8'h15][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_49 = _RANDOM[8'h15][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_50 = _RANDOM[8'h15][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_51 = {_RANDOM[8'h15][31:30], _RANDOM[8'h16][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_52 = _RANDOM[8'h16][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_53 = _RANDOM[8'h16][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_54 = _RANDOM[8'h16][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_55 = _RANDOM[8'h16][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_56 = _RANDOM[8'h16][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_57 = _RANDOM[8'h16][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_58 = _RANDOM[8'h16][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_59 = {_RANDOM[8'h16][31:30], _RANDOM[8'h17][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_60 = _RANDOM[8'h17][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_61 = _RANDOM[8'h17][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_62 = _RANDOM[8'h17][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_63 = _RANDOM[8'h17][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_64 = _RANDOM[8'h17][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_65 = _RANDOM[8'h17][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_66 = _RANDOM[8'h17][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_67 = {_RANDOM[8'h17][31:30], _RANDOM[8'h18][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_68 = _RANDOM[8'h18][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_69 = _RANDOM[8'h18][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_70 = _RANDOM[8'h18][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_71 = _RANDOM[8'h18][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_72 = _RANDOM[8'h18][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_73 = _RANDOM[8'h18][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_74 = _RANDOM[8'h18][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_75 = {_RANDOM[8'h18][31:30], _RANDOM[8'h19][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_76 = _RANDOM[8'h19][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_77 = _RANDOM[8'h19][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_78 = _RANDOM[8'h19][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_79 = _RANDOM[8'h19][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_80 = _RANDOM[8'h19][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_81 = _RANDOM[8'h19][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_82 = _RANDOM[8'h19][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_83 = {_RANDOM[8'h19][31:30], _RANDOM[8'h1A][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_84 = _RANDOM[8'h1A][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_85 = _RANDOM[8'h1A][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_86 = _RANDOM[8'h1A][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_87 = _RANDOM[8'h1A][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_88 = _RANDOM[8'h1A][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_89 = _RANDOM[8'h1A][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_90 = _RANDOM[8'h1A][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_91 = {_RANDOM[8'h1A][31:30], _RANDOM[8'h1B][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_92 = _RANDOM[8'h1B][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_93 = _RANDOM[8'h1B][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_94 = _RANDOM[8'h1B][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_95 = _RANDOM[8'h1B][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_96 = _RANDOM[8'h1B][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_97 = _RANDOM[8'h1B][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_98 = _RANDOM[8'h1B][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_99 = {_RANDOM[8'h1B][31:30], _RANDOM[8'h1C][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_100 = _RANDOM[8'h1C][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_101 = _RANDOM[8'h1C][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_102 = _RANDOM[8'h1C][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_103 = _RANDOM[8'h1C][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_104 = _RANDOM[8'h1C][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_105 = _RANDOM[8'h1C][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_106 = _RANDOM[8'h1C][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_107 = {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_108 = _RANDOM[8'h1D][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_109 = _RANDOM[8'h1D][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_110 = _RANDOM[8'h1D][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_111 = _RANDOM[8'h1D][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_112 = _RANDOM[8'h1D][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_113 = _RANDOM[8'h1D][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_114 = _RANDOM[8'h1D][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_115 = {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_116 = _RANDOM[8'h1E][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_117 = _RANDOM[8'h1E][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_118 = _RANDOM[8'h1E][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_119 = _RANDOM[8'h1E][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_120 = _RANDOM[8'h1E][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_121 = _RANDOM[8'h1E][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_122 = _RANDOM[8'h1E][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_123 = {_RANDOM[8'h1E][31:30], _RANDOM[8'h1F][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_124 = _RANDOM[8'h1F][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_125 = _RANDOM[8'h1F][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_126 = _RANDOM[8'h1F][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_0_127 = _RANDOM[8'h1F][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_0 = _RANDOM[8'h1F][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_1 = _RANDOM[8'h1F][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_2 = _RANDOM[8'h1F][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_3 = {_RANDOM[8'h1F][31:30], _RANDOM[8'h20][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_4 = _RANDOM[8'h20][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_5 = _RANDOM[8'h20][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_6 = _RANDOM[8'h20][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_7 = _RANDOM[8'h20][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_8 = _RANDOM[8'h20][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_9 = _RANDOM[8'h20][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_10 = _RANDOM[8'h20][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_11 = {_RANDOM[8'h20][31:30], _RANDOM[8'h21][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_12 = _RANDOM[8'h21][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_13 = _RANDOM[8'h21][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_14 = _RANDOM[8'h21][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_15 = _RANDOM[8'h21][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_16 = _RANDOM[8'h21][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_17 = _RANDOM[8'h21][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_18 = _RANDOM[8'h21][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_19 = {_RANDOM[8'h21][31:30], _RANDOM[8'h22][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_20 = _RANDOM[8'h22][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_21 = _RANDOM[8'h22][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_22 = _RANDOM[8'h22][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_23 = _RANDOM[8'h22][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_24 = _RANDOM[8'h22][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_25 = _RANDOM[8'h22][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_26 = _RANDOM[8'h22][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_27 = {_RANDOM[8'h22][31:30], _RANDOM[8'h23][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_28 = _RANDOM[8'h23][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_29 = _RANDOM[8'h23][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_30 = _RANDOM[8'h23][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_31 = _RANDOM[8'h23][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_32 = _RANDOM[8'h23][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_33 = _RANDOM[8'h23][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_34 = _RANDOM[8'h23][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_35 = {_RANDOM[8'h23][31:30], _RANDOM[8'h24][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_36 = _RANDOM[8'h24][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_37 = _RANDOM[8'h24][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_38 = _RANDOM[8'h24][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_39 = _RANDOM[8'h24][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_40 = _RANDOM[8'h24][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_41 = _RANDOM[8'h24][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_42 = _RANDOM[8'h24][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_43 = {_RANDOM[8'h24][31:30], _RANDOM[8'h25][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_44 = _RANDOM[8'h25][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_45 = _RANDOM[8'h25][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_46 = _RANDOM[8'h25][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_47 = _RANDOM[8'h25][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_48 = _RANDOM[8'h25][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_49 = _RANDOM[8'h25][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_50 = _RANDOM[8'h25][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_51 = {_RANDOM[8'h25][31:30], _RANDOM[8'h26][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_52 = _RANDOM[8'h26][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_53 = _RANDOM[8'h26][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_54 = _RANDOM[8'h26][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_55 = _RANDOM[8'h26][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_56 = _RANDOM[8'h26][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_57 = _RANDOM[8'h26][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_58 = _RANDOM[8'h26][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_59 = {_RANDOM[8'h26][31:30], _RANDOM[8'h27][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_60 = _RANDOM[8'h27][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_61 = _RANDOM[8'h27][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_62 = _RANDOM[8'h27][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_63 = _RANDOM[8'h27][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_64 = _RANDOM[8'h27][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_65 = _RANDOM[8'h27][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_66 = _RANDOM[8'h27][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_67 = {_RANDOM[8'h27][31:30], _RANDOM[8'h28][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_68 = _RANDOM[8'h28][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_69 = _RANDOM[8'h28][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_70 = _RANDOM[8'h28][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_71 = _RANDOM[8'h28][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_72 = _RANDOM[8'h28][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_73 = _RANDOM[8'h28][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_74 = _RANDOM[8'h28][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_75 = {_RANDOM[8'h28][31:30], _RANDOM[8'h29][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_76 = _RANDOM[8'h29][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_77 = _RANDOM[8'h29][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_78 = _RANDOM[8'h29][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_79 = _RANDOM[8'h29][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_80 = _RANDOM[8'h29][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_81 = _RANDOM[8'h29][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_82 = _RANDOM[8'h29][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_83 = {_RANDOM[8'h29][31:30], _RANDOM[8'h2A][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_84 = _RANDOM[8'h2A][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_85 = _RANDOM[8'h2A][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_86 = _RANDOM[8'h2A][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_87 = _RANDOM[8'h2A][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_88 = _RANDOM[8'h2A][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_89 = _RANDOM[8'h2A][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_90 = _RANDOM[8'h2A][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_91 = {_RANDOM[8'h2A][31:30], _RANDOM[8'h2B][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_92 = _RANDOM[8'h2B][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_93 = _RANDOM[8'h2B][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_94 = _RANDOM[8'h2B][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_95 = _RANDOM[8'h2B][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_96 = _RANDOM[8'h2B][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_97 = _RANDOM[8'h2B][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_98 = _RANDOM[8'h2B][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_99 = {_RANDOM[8'h2B][31:30], _RANDOM[8'h2C][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_100 = _RANDOM[8'h2C][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_101 = _RANDOM[8'h2C][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_102 = _RANDOM[8'h2C][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_103 = _RANDOM[8'h2C][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_104 = _RANDOM[8'h2C][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_105 = _RANDOM[8'h2C][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_106 = _RANDOM[8'h2C][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_107 = {_RANDOM[8'h2C][31:30], _RANDOM[8'h2D][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_108 = _RANDOM[8'h2D][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_109 = _RANDOM[8'h2D][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_110 = _RANDOM[8'h2D][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_111 = _RANDOM[8'h2D][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_112 = _RANDOM[8'h2D][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_113 = _RANDOM[8'h2D][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_114 = _RANDOM[8'h2D][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_115 = {_RANDOM[8'h2D][31:30], _RANDOM[8'h2E][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_116 = _RANDOM[8'h2E][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_117 = _RANDOM[8'h2E][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_118 = _RANDOM[8'h2E][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_119 = _RANDOM[8'h2E][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_120 = _RANDOM[8'h2E][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_121 = _RANDOM[8'h2E][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_122 = _RANDOM[8'h2E][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_123 = {_RANDOM[8'h2E][31:30], _RANDOM[8'h2F][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_124 = _RANDOM[8'h2F][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_125 = _RANDOM[8'h2F][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_126 = _RANDOM[8'h2F][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - useAltOnNaCtrs_1_127 = _RANDOM[8'h2F][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 - s2_provideds_0 = _RANDOM[8'h32][0]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :924:7 - s2_provideds_1 = _RANDOM[8'h32][1]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :924:7 - s2_providers_0 = _RANDOM[8'h32][3:2]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :594:38, :924:7 - s2_providers_1 = _RANDOM[8'h32][5:4]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :594:38, :924:7 - s2_providerResps_0_ctr = _RANDOM[8'h32][8:6]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_providerResps_0_u = _RANDOM[8'h32][9]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_providerResps_0_unconf = _RANDOM[8'h32][10]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_providerResps_1_ctr = _RANDOM[8'h32][13:11]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_providerResps_1_u = _RANDOM[8'h32][14]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_providerResps_1_unconf = _RANDOM[8'h32][15]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 - s2_altUsed_0 = _RANDOM[8'h32][16]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :599:38, :924:7 - s2_altUsed_1 = _RANDOM[8'h32][17]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :599:38, :924:7 - s2_tageTakens_dup_0_0 = _RANDOM[8'h32][18]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_0_1 = _RANDOM[8'h32][19]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_1_0 = _RANDOM[8'h32][20]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_1_1 = _RANDOM[8'h32][21]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_2_0 = _RANDOM[8'h32][22]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_2_1 = _RANDOM[8'h32][23]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_3_0 = _RANDOM[8'h32][24]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_tageTakens_dup_3_1 = _RANDOM[8'h32][25]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 - s2_finalAltPreds_0 = _RANDOM[8'h32][26]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :601:38, :924:7 - s2_finalAltPreds_1 = _RANDOM[8'h32][27]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :601:38, :924:7 - s2_basecnts_0 = _RANDOM[8'h32][29:28]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :602:38, :924:7 - s2_basecnts_1 = _RANDOM[8'h32][31:30]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :602:38, :924:7 - resp_meta_providers_0_valid_r = _RANDOM[8'h33][2]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7 - resp_meta_providers_0_bits_r = _RANDOM[8'h33][4:3]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :668:49, :924:7 - resp_meta_providerResps_0_r_ctr = _RANDOM[8'h33][7:5]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 - resp_meta_providerResps_0_r_u = _RANDOM[8'h33][8]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 - resp_meta_providerResps_0_r_unconf = _RANDOM[8'h33][9]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 - allocatableSlots = _RANDOM[8'h33][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :679:16, :924:7 - resp_meta_allocates_0_r = _RANDOM[8'h33][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :686:40, :924:7 - resp_meta_altUsed_0_r = _RANDOM[8'h33][18]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :699:41, :924:7 - resp_meta_altDiffers_0_r = _RANDOM[8'h33][19]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :700:41, :924:7 - resp_meta_takens_0_r = _RANDOM[8'h33][20]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :702:41, :924:7 - resp_meta_basecnts_0_r = _RANDOM[8'h33][22:21]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :703:41, :924:7 - tage_enable_dup_REG = _RANDOM[8'h33][23]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :705:38, :924:7 - allocLFSR_lfsr = {_RANDOM[8'h33][31:24], _RANDOM[8'h34], _RANDOM[8'h35][23:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_providers_1_valid_r = _RANDOM[8'h35][24]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_providers_1_bits_r = _RANDOM[8'h35][26:25]; // src/main/scala/xiangshan/frontend/Tage.scala:668:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_providerResps_1_r_ctr = _RANDOM[8'h35][29:27]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_providerResps_1_r_u = _RANDOM[8'h35][30]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - resp_meta_providerResps_1_r_unconf = _RANDOM[8'h35][31]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - allocatableSlots_1 = _RANDOM[8'h36][3:0]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :924:7 - resp_meta_allocates_1_r = _RANDOM[8'h36][7:4]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40, :924:7 - resp_meta_altUsed_1_r = _RANDOM[8'h36][8]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :699:41, :924:7 - resp_meta_altDiffers_1_r = _RANDOM[8'h36][9]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :700:41, :924:7 - resp_meta_takens_1_r = _RANDOM[8'h36][10]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :702:41, :924:7 - resp_meta_basecnts_1_r = _RANDOM[8'h36][12:11]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :703:41, :924:7 - tage_enable_dup_REG_1 = _RANDOM[8'h36][13]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :705:38, :924:7 - allocLFSR_lfsr_1 = {_RANDOM[8'h36][31:14], _RANDOM[8'h37], _RANDOM[8'h38][13:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_mask_0_REG = _RANDOM[8'h38][14]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_takens_0_REG = _RANDOM[8'h38][15]; // src/main/scala/xiangshan/frontend/Tage.scala:835:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_alloc_0_REG = _RANDOM[8'h38][16]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_oldCtrs_0_REG = _RANDOM[8'h38][19:17]; // src/main/scala/xiangshan/frontend/Tage.scala:837:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_uMask_0_REG = _RANDOM[8'h38][20]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_us_0_REG = _RANDOM[8'h38][21]; // src/main/scala/xiangshan/frontend/Tage.scala:840:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_0_io_update_reset_u_0_REG = _RANDOM[8'h38][22]; // src/main/scala/xiangshan/frontend/Tage.scala:841:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 - tables_1_io_update_mask_0_REG = _RANDOM[8'h46][18]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_1_io_update_takens_0_REG = _RANDOM[8'h46][19]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_1_io_update_alloc_0_REG = _RANDOM[8'h46][20]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_1_io_update_oldCtrs_0_REG = _RANDOM[8'h46][23:21]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_1_io_update_uMask_0_REG = _RANDOM[8'h46][24]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 - tables_1_io_update_us_0_REG = _RANDOM[8'h46][25]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 - tables_1_io_update_reset_u_0_REG = _RANDOM[8'h46][26]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 - tables_2_io_update_mask_0_REG = _RANDOM[8'h54][22]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_2_io_update_takens_0_REG = _RANDOM[8'h54][23]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_2_io_update_alloc_0_REG = _RANDOM[8'h54][24]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_2_io_update_oldCtrs_0_REG = _RANDOM[8'h54][27:25]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_2_io_update_uMask_0_REG = _RANDOM[8'h54][28]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 - tables_2_io_update_us_0_REG = _RANDOM[8'h54][29]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 - tables_2_io_update_reset_u_0_REG = _RANDOM[8'h54][30]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 - tables_3_io_update_mask_0_REG = _RANDOM[8'h62][26]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_3_io_update_takens_0_REG = _RANDOM[8'h62][27]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_3_io_update_alloc_0_REG = _RANDOM[8'h62][28]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_3_io_update_oldCtrs_0_REG = _RANDOM[8'h62][31:29]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_3_io_update_uMask_0_REG = _RANDOM[8'h63][0]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :924:7 - tables_3_io_update_us_0_REG = _RANDOM[8'h63][1]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :840:48, :924:7 - tables_3_io_update_reset_u_0_REG = _RANDOM[8'h63][2]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :841:48, :924:7 - tables_0_io_update_mask_1_REG = _RANDOM[8'h70][30]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_0_io_update_takens_1_REG = _RANDOM[8'h70][31]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_0_io_update_alloc_1_REG = _RANDOM[8'h71][0]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :924:7 - tables_0_io_update_oldCtrs_1_REG = _RANDOM[8'h71][3:1]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :924:7 - tables_0_io_update_uMask_1_REG = _RANDOM[8'h71][4]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :924:7 - tables_0_io_update_us_1_REG = _RANDOM[8'h71][5]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:48, :924:7 - tables_0_io_update_reset_u_1_REG = _RANDOM[8'h71][6]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :841:48, :924:7 - tables_0_io_update_pc_REG_1 = {_RANDOM[8'h71][31:7], _RANDOM[8'h72][13:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:46, :924:7 - tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist = _RANDOM[8'h73][18:11]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist = _RANDOM[8'h75][6:0]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_1_io_update_mask_1_REG = _RANDOM[8'h7F][2]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_1_io_update_takens_1_REG = _RANDOM[8'h7F][3]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_1_io_update_alloc_1_REG = _RANDOM[8'h7F][4]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_1_io_update_oldCtrs_1_REG = _RANDOM[8'h7F][7:5]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_1_io_update_uMask_1_REG = _RANDOM[8'h7F][8]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 - tables_1_io_update_us_1_REG = _RANDOM[8'h7F][9]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 - tables_1_io_update_reset_u_1_REG = _RANDOM[8'h7F][10]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 - tables_1_io_update_pc_REG_1 = {_RANDOM[8'h7F][31:11], _RANDOM[8'h80][17:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 - tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist = _RANDOM[8'h81][14:8]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist = - {_RANDOM[8'h83][31:27], _RANDOM[8'h84][2:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist = _RANDOM[8'h84][29:19]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_2_io_update_mask_1_REG = _RANDOM[8'h8D][6]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_2_io_update_takens_1_REG = _RANDOM[8'h8D][7]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_2_io_update_alloc_1_REG = _RANDOM[8'h8D][8]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_2_io_update_oldCtrs_1_REG = _RANDOM[8'h8D][11:9]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_2_io_update_uMask_1_REG = _RANDOM[8'h8D][12]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 - tables_2_io_update_us_1_REG = _RANDOM[8'h8D][13]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 - tables_2_io_update_reset_u_1_REG = _RANDOM[8'h8D][14]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 - tables_2_io_update_pc_REG_1 = {_RANDOM[8'h8D][31:15], _RANDOM[8'h8E][21:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 - tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist = - {_RANDOM[8'h8E][31:22], _RANDOM[8'h8F][0]}; // src/main/scala/xiangshan/frontend/Tage.scala:843:46, :844:49, :924:7 - tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist = _RANDOM[8'h90][31:25]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist = _RANDOM[8'h92][14:7]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_3_io_update_mask_1_REG = _RANDOM[8'h9B][10]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 - tables_3_io_update_takens_1_REG = _RANDOM[8'h9B][11]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 - tables_3_io_update_alloc_1_REG = _RANDOM[8'h9B][12]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 - tables_3_io_update_oldCtrs_1_REG = _RANDOM[8'h9B][15:13]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 - tables_3_io_update_uMask_1_REG = _RANDOM[8'h9B][16]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 - tables_3_io_update_us_1_REG = _RANDOM[8'h9B][17]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 - tables_3_io_update_reset_u_1_REG = _RANDOM[8'h9B][18]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 - tables_3_io_update_pc_REG_1 = {_RANDOM[8'h9B][31:19], _RANDOM[8'h9C][25:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 - tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist = _RANDOM[8'h9D][15:5]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist = _RANDOM[8'h9F][11:4]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist = - {_RANDOM[8'h9F][31:28], _RANDOM[8'hA0][2:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 - REG_2_0 = _RANDOM[8'hA9][14]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :924:7 - REG_2_1 = _RANDOM[8'hA9][15]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :924:7 - REG_3_0 = _RANDOM[8'hA9][17:16]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :849:30, :924:7 - REG_3_1 = _RANDOM[8'hA9][19:18]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :849:30, :924:7 - bt_io_update_pc_REG = {_RANDOM[8'hA9][31:20], _RANDOM[8'hAA][26:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :850:29, :924:7 - REG_4_0 = _RANDOM[8'hAA][27]; // src/main/scala/xiangshan/frontend/Tage.scala:850:29, :851:33, :924:7 - REG_4_1 = _RANDOM[8'hAA][28]; // src/main/scala/xiangshan/frontend/Tage.scala:850:29, :851:33, :924:7 - scThresholds_0_ctr = _RANDOM[8'hAC][17:13]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_0_thres = _RANDOM[8'hAC][25:18]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_ctr = _RANDOM[8'hAC][30:26]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_thres = {_RANDOM[8'hAC][31], _RANDOM[8'hAD][6:0]}; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scTableSums_0 = _RANDOM[8'hAD][15:7]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scTableSums_1 = _RANDOM[8'hAD][24:16]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_tagePrvdCtrCentered_r = _RANDOM[8'hAD][27:25]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_0_ctrs_0_0 = {_RANDOM[8'hAD][31:28], _RANDOM[8'hAE][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_0_ctrs_0_1 = _RANDOM[8'hAE][7:2]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_ctrs_0_0 = _RANDOM[8'hAE][25:20]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_ctrs_0_1 = _RANDOM[8'hAE][31:26]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_2_ctrs_0_0 = _RANDOM[8'hAF][17:12]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_2_ctrs_0_1 = _RANDOM[8'hAF][23:18]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_3_ctrs_0_0 = _RANDOM[8'hB0][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_3_ctrs_0_1 = _RANDOM[8'hB0][15:10]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_tageTakens_0_r = _RANDOM[8'hB0][30]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :296:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_scUsed_0_r = _RANDOM[8'hB0][31]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_scPreds_0_r = _RANDOM[8'hB1][0]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_0 = _RANDOM[8'hB1][6:1]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_1 = _RANDOM[8'hB1][12:7]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_2 = _RANDOM[8'hB1][18:13]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_3 = _RANDOM[8'hB1][24:19]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_0 = _RANDOM[8'hB1][25]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_1 = _RANDOM[8'hB1][26]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_2 = _RANDOM[8'hB1][27]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_3 = _RANDOM[8'hB1][28]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - sc_enable_dup_REG = _RANDOM[8'hB1][29]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scTableSums_1_0 = {_RANDOM[8'hB1][31:30], _RANDOM[8'hB2][6:0]}; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scTableSums_1_1 = _RANDOM[8'hB2][15:7]; // src/main/scala/xiangshan/frontend/SC.scala:277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_tagePrvdCtrCentered_r_1 = _RANDOM[8'hB2][18:16]; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_0_ctrs_1_0 = {_RANDOM[8'hB2][31], _RANDOM[8'hB3][4:0]}; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_0_ctrs_1_1 = _RANDOM[8'hB3][10:5]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_1_ctrs_1_0 = _RANDOM[8'hB3][28:23]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_1_ctrs_1_1 = {_RANDOM[8'hB3][31:29], _RANDOM[8'hB4][2:0]}; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_2_ctrs_1_0 = _RANDOM[8'hB4][20:15]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_2_ctrs_1_1 = _RANDOM[8'hB4][26:21]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_3_ctrs_1_0 = _RANDOM[8'hB5][12:7]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s2_scResps_r_1_3_ctrs_1_1 = _RANDOM[8'hB5][18:13]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_tageTakens_1_r = _RANDOM[8'hB5][21]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :296:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_scUsed_1_r = _RANDOM[8'hB5][22]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - resp_meta_scMeta_scPreds_1_r = _RANDOM[8'hB5][23]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_1_0 = _RANDOM[8'hB5][29:24]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_1_1 = {_RANDOM[8'hB5][31:30], _RANDOM[8'hB6][3:0]}; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_1_2 = _RANDOM[8'hB6][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - r_1_3 = _RANDOM[8'hB6][15:10]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_0_1 = _RANDOM[8'hB6][16]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_1_1 = _RANDOM[8'hB6][17]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_2_1 = _RANDOM[8'hB6][18]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - s3_pred_dup_3_1 = _RANDOM[8'hB6][19]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - sc_enable_dup_REG_1 = _RANDOM[8'hB6][20]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_mask_0_REG = _RANDOM[8'hB6][21]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_tagePreds_0_REG = _RANDOM[8'hB6][22]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_takens_0_REG = _RANDOM[8'hB6][23]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_oldCtrs_0_REG = _RANDOM[8'hB6][29:24]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_mask_0_REG = _RANDOM[8'hBC][25]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_tagePreds_0_REG = _RANDOM[8'hBC][26]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_takens_0_REG = _RANDOM[8'hBC][27]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_oldCtrs_0_REG = {_RANDOM[8'hBC][31:28], _RANDOM[8'hBD][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_mask_0_REG = _RANDOM[8'hC2][29]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_tagePreds_0_REG = _RANDOM[8'hC2][30]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_takens_0_REG = _RANDOM[8'hC2][31]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_oldCtrs_0_REG = _RANDOM[8'hC3][5:0]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_mask_0_REG = _RANDOM[8'hC9][1]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_tagePreds_0_REG = _RANDOM[8'hC9][2]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_takens_0_REG = _RANDOM[8'hC9][3]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_oldCtrs_0_REG = _RANDOM[8'hC9][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_mask_1_REG = _RANDOM[8'hCF][5]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_tagePreds_1_REG = _RANDOM[8'hCF][6]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_takens_1_REG = _RANDOM[8'hCF][7]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_oldCtrs_1_REG = _RANDOM[8'hCF][13:8]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_0_io_update_pc_REG_1 = {_RANDOM[8'hCF][31:14], _RANDOM[8'hD0][20:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_mask_1_REG = _RANDOM[8'hD5][9]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_tagePreds_1_REG = _RANDOM[8'hD5][10]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_takens_1_REG = _RANDOM[8'hD5][11]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_oldCtrs_1_REG = _RANDOM[8'hD5][17:12]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_pc_REG_1 = {_RANDOM[8'hD5][31:18], _RANDOM[8'hD6][24:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist = _RANDOM[8'hD8][10:7]; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_mask_1_REG = _RANDOM[8'hDB][13]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_tagePreds_1_REG = _RANDOM[8'hDB][14]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_takens_1_REG = _RANDOM[8'hDB][15]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_oldCtrs_1_REG = _RANDOM[8'hDB][21:16]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_pc_REG_1 = {_RANDOM[8'hDB][31:22], _RANDOM[8'hDC][28:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist = - _RANDOM[8'hDE][22:15]; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_mask_1_REG = _RANDOM[8'hE1][17]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_tagePreds_1_REG = _RANDOM[8'hE1][18]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_takens_1_REG = _RANDOM[8'hE1][19]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_oldCtrs_1_REG = _RANDOM[8'hE1][25:20]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_pc_REG_1 = - {_RANDOM[8'hE1][31:26], _RANDOM[8'hE2], _RANDOM[8'hE3][0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist = - {_RANDOM[8'hE6][31:26], _RANDOM[8'hE7][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + for (logic [7:0] i = 8'h0; i < 8'hEA; i += 8'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + end // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s1_pc_dup_0 = {_RANDOM[8'h0], _RANDOM[8'h1][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + REG = _RANDOM[8'hF][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + REG_1 = _RANDOM[8'hF][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24}, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + bankTickCtrDistanceToTops_0 = _RANDOM[8'hF][20:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :926:7] + bankTickCtrDistanceToTops_1 = _RANDOM[8'hF][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :926:7] + bankTickCtrs_0 = {_RANDOM[8'hF][31:28], _RANDOM[8'h10][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/Tage.scala:562:45, :926:7] + bankTickCtrs_1 = _RANDOM[8'h10][9:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :926:7] + useAltOnNaCtrs_0_0 = _RANDOM[8'h10][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_1 = _RANDOM[8'h10][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_2 = _RANDOM[8'h10][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_3 = _RANDOM[8'h10][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_4 = _RANDOM[8'h10][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_5 = {_RANDOM[8'h10][31:30], _RANDOM[8'h11][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45, :563:31, :926:7] + useAltOnNaCtrs_0_6 = _RANDOM[8'h11][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_7 = _RANDOM[8'h11][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_8 = _RANDOM[8'h11][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_9 = _RANDOM[8'h11][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_10 = _RANDOM[8'h11][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_11 = _RANDOM[8'h11][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_12 = _RANDOM[8'h11][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_13 = {_RANDOM[8'h11][31:30], _RANDOM[8'h12][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_14 = _RANDOM[8'h12][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_15 = _RANDOM[8'h12][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_16 = _RANDOM[8'h12][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_17 = _RANDOM[8'h12][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_18 = _RANDOM[8'h12][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_19 = _RANDOM[8'h12][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_20 = _RANDOM[8'h12][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_21 = {_RANDOM[8'h12][31:30], _RANDOM[8'h13][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_22 = _RANDOM[8'h13][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_23 = _RANDOM[8'h13][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_24 = _RANDOM[8'h13][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_25 = _RANDOM[8'h13][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_26 = _RANDOM[8'h13][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_27 = _RANDOM[8'h13][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_28 = _RANDOM[8'h13][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_29 = {_RANDOM[8'h13][31:30], _RANDOM[8'h14][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_30 = _RANDOM[8'h14][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_31 = _RANDOM[8'h14][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_32 = _RANDOM[8'h14][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_33 = _RANDOM[8'h14][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_34 = _RANDOM[8'h14][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_35 = _RANDOM[8'h14][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_36 = _RANDOM[8'h14][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_37 = {_RANDOM[8'h14][31:30], _RANDOM[8'h15][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_38 = _RANDOM[8'h15][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_39 = _RANDOM[8'h15][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_40 = _RANDOM[8'h15][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_41 = _RANDOM[8'h15][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_42 = _RANDOM[8'h15][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_43 = _RANDOM[8'h15][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_44 = _RANDOM[8'h15][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_45 = {_RANDOM[8'h15][31:30], _RANDOM[8'h16][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_46 = _RANDOM[8'h16][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_47 = _RANDOM[8'h16][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_48 = _RANDOM[8'h16][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_49 = _RANDOM[8'h16][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_50 = _RANDOM[8'h16][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_51 = _RANDOM[8'h16][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_52 = _RANDOM[8'h16][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_53 = {_RANDOM[8'h16][31:30], _RANDOM[8'h17][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_54 = _RANDOM[8'h17][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_55 = _RANDOM[8'h17][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_56 = _RANDOM[8'h17][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_57 = _RANDOM[8'h17][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_58 = _RANDOM[8'h17][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_59 = _RANDOM[8'h17][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_60 = _RANDOM[8'h17][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_61 = {_RANDOM[8'h17][31:30], _RANDOM[8'h18][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_62 = _RANDOM[8'h18][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_63 = _RANDOM[8'h18][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_64 = _RANDOM[8'h18][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_65 = _RANDOM[8'h18][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_66 = _RANDOM[8'h18][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_67 = _RANDOM[8'h18][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_68 = _RANDOM[8'h18][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_69 = {_RANDOM[8'h18][31:30], _RANDOM[8'h19][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_70 = _RANDOM[8'h19][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_71 = _RANDOM[8'h19][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_72 = _RANDOM[8'h19][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_73 = _RANDOM[8'h19][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_74 = _RANDOM[8'h19][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_75 = _RANDOM[8'h19][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_76 = _RANDOM[8'h19][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_77 = {_RANDOM[8'h19][31:30], _RANDOM[8'h1A][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_78 = _RANDOM[8'h1A][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_79 = _RANDOM[8'h1A][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_80 = _RANDOM[8'h1A][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_81 = _RANDOM[8'h1A][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_82 = _RANDOM[8'h1A][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_83 = _RANDOM[8'h1A][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_84 = _RANDOM[8'h1A][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_85 = {_RANDOM[8'h1A][31:30], _RANDOM[8'h1B][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_86 = _RANDOM[8'h1B][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_87 = _RANDOM[8'h1B][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_88 = _RANDOM[8'h1B][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_89 = _RANDOM[8'h1B][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_90 = _RANDOM[8'h1B][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_91 = _RANDOM[8'h1B][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_92 = _RANDOM[8'h1B][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_93 = {_RANDOM[8'h1B][31:30], _RANDOM[8'h1C][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_94 = _RANDOM[8'h1C][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_95 = _RANDOM[8'h1C][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_96 = _RANDOM[8'h1C][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_97 = _RANDOM[8'h1C][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_98 = _RANDOM[8'h1C][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_99 = _RANDOM[8'h1C][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_100 = _RANDOM[8'h1C][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_101 = {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_102 = _RANDOM[8'h1D][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_103 = _RANDOM[8'h1D][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_104 = _RANDOM[8'h1D][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_105 = _RANDOM[8'h1D][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_106 = _RANDOM[8'h1D][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_107 = _RANDOM[8'h1D][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_108 = _RANDOM[8'h1D][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_109 = {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_110 = _RANDOM[8'h1E][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_111 = _RANDOM[8'h1E][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_112 = _RANDOM[8'h1E][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_113 = _RANDOM[8'h1E][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_114 = _RANDOM[8'h1E][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_115 = _RANDOM[8'h1E][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_116 = _RANDOM[8'h1E][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_117 = {_RANDOM[8'h1E][31:30], _RANDOM[8'h1F][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_118 = _RANDOM[8'h1F][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_119 = _RANDOM[8'h1F][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_120 = _RANDOM[8'h1F][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_121 = _RANDOM[8'h1F][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_122 = _RANDOM[8'h1F][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_123 = _RANDOM[8'h1F][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_124 = _RANDOM[8'h1F][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_125 = {_RANDOM[8'h1F][31:30], _RANDOM[8'h20][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_126 = _RANDOM[8'h20][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_0_127 = _RANDOM[8'h20][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_0 = _RANDOM[8'h20][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_1 = _RANDOM[8'h20][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_2 = _RANDOM[8'h20][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_3 = _RANDOM[8'h20][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_4 = _RANDOM[8'h20][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_5 = {_RANDOM[8'h20][31:30], _RANDOM[8'h21][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_6 = _RANDOM[8'h21][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_7 = _RANDOM[8'h21][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_8 = _RANDOM[8'h21][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_9 = _RANDOM[8'h21][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_10 = _RANDOM[8'h21][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_11 = _RANDOM[8'h21][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_12 = _RANDOM[8'h21][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_13 = {_RANDOM[8'h21][31:30], _RANDOM[8'h22][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_14 = _RANDOM[8'h22][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_15 = _RANDOM[8'h22][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_16 = _RANDOM[8'h22][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_17 = _RANDOM[8'h22][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_18 = _RANDOM[8'h22][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_19 = _RANDOM[8'h22][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_20 = _RANDOM[8'h22][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_21 = {_RANDOM[8'h22][31:30], _RANDOM[8'h23][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_22 = _RANDOM[8'h23][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_23 = _RANDOM[8'h23][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_24 = _RANDOM[8'h23][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_25 = _RANDOM[8'h23][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_26 = _RANDOM[8'h23][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_27 = _RANDOM[8'h23][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_28 = _RANDOM[8'h23][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_29 = {_RANDOM[8'h23][31:30], _RANDOM[8'h24][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_30 = _RANDOM[8'h24][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_31 = _RANDOM[8'h24][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_32 = _RANDOM[8'h24][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_33 = _RANDOM[8'h24][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_34 = _RANDOM[8'h24][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_35 = _RANDOM[8'h24][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_36 = _RANDOM[8'h24][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_37 = {_RANDOM[8'h24][31:30], _RANDOM[8'h25][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_38 = _RANDOM[8'h25][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_39 = _RANDOM[8'h25][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_40 = _RANDOM[8'h25][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_41 = _RANDOM[8'h25][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_42 = _RANDOM[8'h25][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_43 = _RANDOM[8'h25][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_44 = _RANDOM[8'h25][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_45 = {_RANDOM[8'h25][31:30], _RANDOM[8'h26][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_46 = _RANDOM[8'h26][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_47 = _RANDOM[8'h26][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_48 = _RANDOM[8'h26][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_49 = _RANDOM[8'h26][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_50 = _RANDOM[8'h26][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_51 = _RANDOM[8'h26][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_52 = _RANDOM[8'h26][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_53 = {_RANDOM[8'h26][31:30], _RANDOM[8'h27][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_54 = _RANDOM[8'h27][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_55 = _RANDOM[8'h27][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_56 = _RANDOM[8'h27][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_57 = _RANDOM[8'h27][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_58 = _RANDOM[8'h27][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_59 = _RANDOM[8'h27][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_60 = _RANDOM[8'h27][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_61 = {_RANDOM[8'h27][31:30], _RANDOM[8'h28][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_62 = _RANDOM[8'h28][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_63 = _RANDOM[8'h28][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_64 = _RANDOM[8'h28][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_65 = _RANDOM[8'h28][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_66 = _RANDOM[8'h28][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_67 = _RANDOM[8'h28][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_68 = _RANDOM[8'h28][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_69 = {_RANDOM[8'h28][31:30], _RANDOM[8'h29][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_70 = _RANDOM[8'h29][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_71 = _RANDOM[8'h29][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_72 = _RANDOM[8'h29][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_73 = _RANDOM[8'h29][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_74 = _RANDOM[8'h29][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_75 = _RANDOM[8'h29][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_76 = _RANDOM[8'h29][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_77 = {_RANDOM[8'h29][31:30], _RANDOM[8'h2A][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_78 = _RANDOM[8'h2A][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_79 = _RANDOM[8'h2A][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_80 = _RANDOM[8'h2A][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_81 = _RANDOM[8'h2A][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_82 = _RANDOM[8'h2A][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_83 = _RANDOM[8'h2A][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_84 = _RANDOM[8'h2A][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_85 = {_RANDOM[8'h2A][31:30], _RANDOM[8'h2B][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_86 = _RANDOM[8'h2B][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_87 = _RANDOM[8'h2B][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_88 = _RANDOM[8'h2B][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_89 = _RANDOM[8'h2B][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_90 = _RANDOM[8'h2B][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_91 = _RANDOM[8'h2B][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_92 = _RANDOM[8'h2B][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_93 = {_RANDOM[8'h2B][31:30], _RANDOM[8'h2C][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_94 = _RANDOM[8'h2C][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_95 = _RANDOM[8'h2C][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_96 = _RANDOM[8'h2C][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_97 = _RANDOM[8'h2C][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_98 = _RANDOM[8'h2C][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_99 = _RANDOM[8'h2C][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_100 = _RANDOM[8'h2C][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_101 = {_RANDOM[8'h2C][31:30], _RANDOM[8'h2D][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_102 = _RANDOM[8'h2D][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_103 = _RANDOM[8'h2D][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_104 = _RANDOM[8'h2D][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_105 = _RANDOM[8'h2D][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_106 = _RANDOM[8'h2D][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_107 = _RANDOM[8'h2D][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_108 = _RANDOM[8'h2D][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_109 = {_RANDOM[8'h2D][31:30], _RANDOM[8'h2E][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_110 = _RANDOM[8'h2E][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_111 = _RANDOM[8'h2E][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_112 = _RANDOM[8'h2E][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_113 = _RANDOM[8'h2E][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_114 = _RANDOM[8'h2E][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_115 = _RANDOM[8'h2E][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_116 = _RANDOM[8'h2E][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_117 = {_RANDOM[8'h2E][31:30], _RANDOM[8'h2F][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_118 = _RANDOM[8'h2F][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_119 = _RANDOM[8'h2F][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_120 = _RANDOM[8'h2F][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_121 = _RANDOM[8'h2F][17:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_122 = _RANDOM[8'h2F][21:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_123 = _RANDOM[8'h2F][25:22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_124 = _RANDOM[8'h2F][29:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_125 = {_RANDOM[8'h2F][31:30], _RANDOM[8'h30][1:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_126 = _RANDOM[8'h30][5:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + useAltOnNaCtrs_1_127 = _RANDOM[8'h30][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :926:7] + s2_provideds_0 = _RANDOM[8'h32][28]; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :926:7] + s2_provideds_1 = _RANDOM[8'h32][29]; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :926:7] + s2_providers_0 = _RANDOM[8'h32][31:30]; // @[src/main/scala/xiangshan/frontend/Tage.scala:593:38, :594:38, :926:7] + s2_providers_1 = _RANDOM[8'h33][1:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :926:7] + s2_providerResps_0_ctr = _RANDOM[8'h33][4:2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_providerResps_0_u = _RANDOM[8'h33][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_providerResps_0_unconf = _RANDOM[8'h33][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_providerResps_1_ctr = _RANDOM[8'h33][9:7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_providerResps_1_u = _RANDOM[8'h33][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_providerResps_1_unconf = _RANDOM[8'h33][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :595:38, :926:7] + s2_altUsed_0 = _RANDOM[8'h33][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :599:38, :926:7] + s2_altUsed_1 = _RANDOM[8'h33][13]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :599:38, :926:7] + s2_tageTakens_dup_0_0 = _RANDOM[8'h33][14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_0_1 = _RANDOM[8'h33][15]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_1_0 = _RANDOM[8'h33][16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_1_1 = _RANDOM[8'h33][17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_2_0 = _RANDOM[8'h33][18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_2_1 = _RANDOM[8'h33][19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_3_0 = _RANDOM[8'h33][20]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_tageTakens_dup_3_1 = _RANDOM[8'h33][21]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :600:58, :926:7] + s2_finalAltPreds_0 = _RANDOM[8'h33][22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :601:38, :926:7] + s2_finalAltPreds_1 = _RANDOM[8'h33][23]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :601:38, :926:7] + s2_basecnts_0 = _RANDOM[8'h33][25:24]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :602:38, :926:7] + s2_basecnts_1 = _RANDOM[8'h33][27:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :602:38, :926:7] + resp_meta_providers_0_valid_r = _RANDOM[8'h33][30]; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :667:49, :926:7] + resp_meta_providers_0_bits_r = {_RANDOM[8'h33][31], _RANDOM[8'h34][0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49, :926:7] + resp_meta_providerResps_0_r_ctr = _RANDOM[8'h34][3:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :669:49, :926:7] + resp_meta_providerResps_0_r_u = _RANDOM[8'h34][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :669:49, :926:7] + resp_meta_providerResps_0_r_unconf = _RANDOM[8'h34][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :669:49, :926:7] + allocatableSlots = _RANDOM[8'h34][9:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :679:16, :926:7] + resp_meta_allocates_0_r = _RANDOM[8'h34][13:10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :686:40, :926:7] + resp_meta_altUsed_0_r = _RANDOM[8'h34][14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :699:41, :926:7] + resp_meta_altDiffers_0_r = _RANDOM[8'h34][15]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :700:41, :926:7] + resp_meta_takens_0_r = _RANDOM[8'h34][16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :702:41, :926:7] + resp_meta_basecnts_0_r = _RANDOM[8'h34][18:17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :703:41, :926:7] + tage_enable_dup_REG = _RANDOM[8'h34][19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :705:38, :926:7] + allocLFSR_lfsr = {_RANDOM[8'h34][31:20], _RANDOM[8'h35], _RANDOM[8'h36][19:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_providers_1_valid_r = _RANDOM[8'h36][20]; // @[src/main/scala/xiangshan/frontend/Tage.scala:667:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_providers_1_bits_r = _RANDOM[8'h36][22:21]; // @[src/main/scala/xiangshan/frontend/Tage.scala:668:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_providerResps_1_r_ctr = _RANDOM[8'h36][25:23]; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_providerResps_1_r_u = _RANDOM[8'h36][26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_providerResps_1_r_unconf = _RANDOM[8'h36][27]; // @[src/main/scala/xiangshan/frontend/Tage.scala:669:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + allocatableSlots_1 = _RANDOM[8'h36][31:28]; // @[src/main/scala/xiangshan/frontend/Tage.scala:679:16, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + resp_meta_allocates_1_r = _RANDOM[8'h37][3:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :926:7] + resp_meta_altUsed_1_r = _RANDOM[8'h37][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :699:41, :926:7] + resp_meta_altDiffers_1_r = _RANDOM[8'h37][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :700:41, :926:7] + resp_meta_takens_1_r = _RANDOM[8'h37][6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :702:41, :926:7] + resp_meta_basecnts_1_r = _RANDOM[8'h37][8:7]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :703:41, :926:7] + tage_enable_dup_REG_1 = _RANDOM[8'h37][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :705:38, :926:7] + allocLFSR_lfsr_1 = {_RANDOM[8'h37][31:10], _RANDOM[8'h38], _RANDOM[8'h39][9:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:686:40, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_reset_u_0_REG = _RANDOM[8'h39][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_mask_0_REG = _RANDOM[8'h39][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_takens_0_r = _RANDOM[8'h39][12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_alloc_0_r = _RANDOM[8'h39][13]; // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_oldCtrs_0_r = _RANDOM[8'h39][16:14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_uMask_0_r = _RANDOM[8'h39][17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_0_io_update_us_0_r = _RANDOM[8'h39][18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45, :926:7, utility/src/main/scala/utility/LFSR64.scala:27:33] + tables_1_io_update_reset_u_0_REG = _RANDOM[8'h47][16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_1_io_update_mask_0_REG = _RANDOM[8'h47][17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_1_io_update_takens_0_r = _RANDOM[8'h47][18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_1_io_update_alloc_0_r = _RANDOM[8'h47][19]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_1_io_update_oldCtrs_0_r = _RANDOM[8'h47][22:20]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_1_io_update_uMask_0_r = _RANDOM[8'h47][23]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_1_io_update_us_0_r = _RANDOM[8'h47][24]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_2_io_update_reset_u_0_REG = _RANDOM[8'h55][22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_2_io_update_mask_0_REG = _RANDOM[8'h55][23]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_2_io_update_takens_0_r = _RANDOM[8'h55][24]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_2_io_update_alloc_0_r = _RANDOM[8'h55][25]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_2_io_update_oldCtrs_0_r = _RANDOM[8'h55][28:26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_2_io_update_uMask_0_r = _RANDOM[8'h55][29]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_2_io_update_us_0_r = _RANDOM[8'h55][30]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_3_io_update_reset_u_0_REG = _RANDOM[8'h63][28]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_3_io_update_mask_0_REG = _RANDOM[8'h63][29]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_3_io_update_takens_0_r = _RANDOM[8'h63][30]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_3_io_update_alloc_0_r = _RANDOM[8'h63][31]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_3_io_update_oldCtrs_0_r = _RANDOM[8'h64][2:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50, :926:7] + tables_3_io_update_uMask_0_r = _RANDOM[8'h64][3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50, :842:48, :926:7] + tables_3_io_update_us_0_r = _RANDOM[8'h64][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50, :843:45, :926:7] + tables_0_io_update_reset_u_1_REG = _RANDOM[8'h72][2]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_0_io_update_mask_1_REG = _RANDOM[8'h72][3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_0_io_update_takens_1_r = _RANDOM[8'h72][4]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_0_io_update_alloc_1_r = _RANDOM[8'h72][5]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_0_io_update_oldCtrs_1_r = _RANDOM[8'h72][8:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_0_io_update_uMask_1_r = _RANDOM[8'h72][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_0_io_update_us_1_r = _RANDOM[8'h72][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_0_io_update_pc_r_1 = {_RANDOM[8'h72][31:11], _RANDOM[8'h73][19:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :845:42, :926:7] + tables_0_io_update_folded_hist_r_1_hist_14_folded_hist = _RANDOM[8'h74][24:17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_0_io_update_folded_hist_r_1_hist_7_folded_hist = _RANDOM[8'h76][12:6]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_1_io_update_reset_u_1_REG = _RANDOM[8'h80][8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_1_io_update_mask_1_REG = _RANDOM[8'h80][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_1_io_update_takens_1_r = _RANDOM[8'h80][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_1_io_update_alloc_1_r = _RANDOM[8'h80][11]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_1_io_update_oldCtrs_1_r = _RANDOM[8'h80][14:12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_1_io_update_uMask_1_r = _RANDOM[8'h80][15]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_1_io_update_us_1_r = _RANDOM[8'h80][16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_1_io_update_pc_r_1 = {_RANDOM[8'h80][31:17], _RANDOM[8'h81][25:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :845:42, :926:7] + tables_1_io_update_folded_hist_r_1_hist_15_folded_hist = _RANDOM[8'h82][22:16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_1_io_update_folded_hist_r_1_hist_4_folded_hist = _RANDOM[8'h85][10:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_1_io_update_folded_hist_r_1_hist_1_folded_hist = + {_RANDOM[8'h85][31:27], _RANDOM[8'h86][5:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_2_io_update_reset_u_1_REG = _RANDOM[8'h8E][14]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_2_io_update_mask_1_REG = _RANDOM[8'h8E][15]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_2_io_update_takens_1_r = _RANDOM[8'h8E][16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_2_io_update_alloc_1_r = _RANDOM[8'h8E][17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_2_io_update_oldCtrs_1_r = _RANDOM[8'h8E][20:18]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_2_io_update_uMask_1_r = _RANDOM[8'h8E][21]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_2_io_update_us_1_r = _RANDOM[8'h8E][22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_2_io_update_pc_r_1 = {_RANDOM[8'h8E][31:23], _RANDOM[8'h8F]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :845:42, :926:7] + tables_2_io_update_folded_hist_r_1_hist_17_folded_hist = _RANDOM[8'h90][10:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_2_io_update_folded_hist_r_1_hist_9_folded_hist = _RANDOM[8'h92][9:3]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_2_io_update_folded_hist_r_1_hist_3_folded_hist = _RANDOM[8'h93][24:17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_3_io_update_reset_u_1_REG = _RANDOM[8'h9C][20]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :926:7] + tables_3_io_update_mask_1_REG = _RANDOM[8'h9C][21]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :926:7] + tables_3_io_update_takens_1_r = _RANDOM[8'h9C][22]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :838:49, :926:7] + tables_3_io_update_alloc_1_r = _RANDOM[8'h9C][23]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :926:7] + tables_3_io_update_oldCtrs_1_r = _RANDOM[8'h9C][26:24]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:50, :926:7] + tables_3_io_update_uMask_1_r = _RANDOM[8'h9C][27]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :842:48, :926:7] + tables_3_io_update_us_1_r = _RANDOM[8'h9C][28]; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:45, :926:7] + tables_3_io_update_pc_r_1 = + {_RANDOM[8'h9C][31:29], _RANDOM[8'h9D], _RANDOM[8'h9E][5:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48, :845:42, :926:7] + tables_3_io_update_folded_hist_r_1_hist_16_folded_hist = _RANDOM[8'h9E][27:17]; // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42, :846:51, :926:7] + tables_3_io_update_folded_hist_r_1_hist_8_folded_hist = _RANDOM[8'hA0][23:16]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + tables_3_io_update_folded_hist_r_1_hist_5_folded_hist = _RANDOM[8'hA1][14:8]; // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51, :926:7] + REG_2_0 = _RANDOM[8'hAA][26]; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31, :926:7] + REG_2_1 = _RANDOM[8'hAA][27]; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31, :926:7] + r_0 = _RANDOM[8'hAA][29:28]; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31, :851:32, :926:7] + r_1 = _RANDOM[8'hAA][31:30]; // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31, :851:32, :926:7] + bt_io_update_pc_r = {_RANDOM[8'hAB], _RANDOM[8'hAC][8:0]}; // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31, :926:7] + r_1_0 = _RANDOM[8'hAC][9]; // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31, :853:35, :926:7] + r_1_1 = _RANDOM[8'hAC][10]; // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31, :853:35, :926:7] + scThresholds_0_ctr = _RANDOM[8'hAD][31:27]; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_0_thres = _RANDOM[8'hAE][7:0]; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_ctr = _RANDOM[8'hAE][12:8]; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_thres = _RANDOM[8'hAE][20:13]; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scTableSums_0 = _RANDOM[8'hAE][29:21]; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scTableSums_1 = {_RANDOM[8'hAE][31:30], _RANDOM[8'hAF][6:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_tagePrvdCtrCentered_r = _RANDOM[8'hAF][9:7]; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_0_ctrs_0_0 = _RANDOM[8'hAF][15:10]; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_0_ctrs_0_1 = _RANDOM[8'hAF][21:16]; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_ctrs_0_0 = _RANDOM[8'hB0][7:2]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_ctrs_0_1 = _RANDOM[8'hB0][13:8]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_2_ctrs_0_0 = _RANDOM[8'hB0][31:26]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_2_ctrs_0_1 = _RANDOM[8'hB1][5:0]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_3_ctrs_0_0 = _RANDOM[8'hB1][23:18]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_3_ctrs_0_1 = _RANDOM[8'hB1][29:24]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_tageTakens_0_r = _RANDOM[8'hB2][12]; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_scUsed_0_r = _RANDOM[8'hB2][13]; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_scPreds_0_r = _RANDOM[8'hB2][14]; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_2_0 = _RANDOM[8'hB2][20:15]; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_2_1 = _RANDOM[8'hB2][26:21]; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_2_2 = {_RANDOM[8'hB2][31:27], _RANDOM[8'hB3][0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_2_3 = _RANDOM[8'hB3][6:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_0 = _RANDOM[8'hB3][7]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_1 = _RANDOM[8'hB3][8]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_2 = _RANDOM[8'hB3][9]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_3 = _RANDOM[8'hB3][10]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + sc_enable_dup_REG = _RANDOM[8'hB3][11]; // @[src/main/scala/xiangshan/frontend/SC.scala:299:40, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scTableSums_1_0 = _RANDOM[8'hB3][20:12]; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scTableSums_1_1 = _RANDOM[8'hB3][29:21]; // @[src/main/scala/xiangshan/frontend/SC.scala:277:37, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_tagePrvdCtrCentered_r_1 = {_RANDOM[8'hB3][31:30], _RANDOM[8'hB4][0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_0_ctrs_1_0 = _RANDOM[8'hB4][18:13]; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_0_ctrs_1_1 = _RANDOM[8'hB4][24:19]; // @[src/main/scala/xiangshan/frontend/SC.scala:278:61, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_1_ctrs_1_0 = _RANDOM[8'hB5][10:5]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_1_ctrs_1_1 = _RANDOM[8'hB5][16:11]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_2_ctrs_1_0 = {_RANDOM[8'hB5][31:29], _RANDOM[8'hB6][2:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_2_ctrs_1_1 = _RANDOM[8'hB6][8:3]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_3_ctrs_1_0 = _RANDOM[8'hB6][26:21]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s2_scResps_r_1_3_ctrs_1_1 = {_RANDOM[8'hB6][31:27], _RANDOM[8'hB7][0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_tageTakens_1_r = _RANDOM[8'hB7][3]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :296:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_scUsed_1_r = _RANDOM[8'hB7][4]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + resp_meta_scMeta_scPreds_1_r = _RANDOM[8'hB7][5]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_3_0 = _RANDOM[8'hB7][11:6]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_3_1 = _RANDOM[8'hB7][17:12]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_3_2 = _RANDOM[8'hB7][23:18]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + r_3_3 = _RANDOM[8'hB7][29:24]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_0_1 = _RANDOM[8'hB7][30]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_1_1 = _RANDOM[8'hB7][31]; // @[src/main/scala/xiangshan/frontend/SC.scala:283:41, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_2_1 = _RANDOM[8'hB8][0]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + s3_pred_dup_3_1 = _RANDOM[8'hB8][1]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + sc_enable_dup_REG_1 = _RANDOM[8'hB8][2]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_mask_0_REG = _RANDOM[8'hB8][3]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_tagePreds_0_r = _RANDOM[8'hB8][4]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_takens_0_r = _RANDOM[8'hB8][5]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_oldCtrs_0_r = _RANDOM[8'hB8][11:6]; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_mask_0_REG = _RANDOM[8'hBE][9]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_tagePreds_0_r = _RANDOM[8'hBE][10]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_takens_0_r = _RANDOM[8'hBE][11]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_oldCtrs_0_r = _RANDOM[8'hBE][17:12]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_mask_0_REG = _RANDOM[8'hC4][15]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_tagePreds_0_r = _RANDOM[8'hC4][16]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_takens_0_r = _RANDOM[8'hC4][17]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_oldCtrs_0_r = _RANDOM[8'hC4][23:18]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_mask_0_REG = _RANDOM[8'hCA][21]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_tagePreds_0_r = _RANDOM[8'hCA][22]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_takens_0_r = _RANDOM[8'hCA][23]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_oldCtrs_0_r = _RANDOM[8'hCA][29:24]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_mask_1_REG = _RANDOM[8'hD0][27]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_tagePreds_1_r = _RANDOM[8'hD0][28]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_takens_1_r = _RANDOM[8'hD0][29]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_oldCtrs_1_r = {_RANDOM[8'hD0][31:30], _RANDOM[8'hD1][3:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_0_io_update_pc_r_1 = {_RANDOM[8'hD1][31:4], _RANDOM[8'hD2][12:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:382:54, :383:46, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_mask_1_REG = _RANDOM[8'hD7][1]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_tagePreds_1_r = _RANDOM[8'hD7][2]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_takens_1_r = _RANDOM[8'hD7][3]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_oldCtrs_1_r = _RANDOM[8'hD7][9:4]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_pc_r_1 = {_RANDOM[8'hD7][31:10], _RANDOM[8'hD8][18:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :383:46, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist = _RANDOM[8'hDA][4:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_mask_1_REG = _RANDOM[8'hDD][7]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_tagePreds_1_r = _RANDOM[8'hDD][8]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_takens_1_r = _RANDOM[8'hDD][9]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_oldCtrs_1_r = _RANDOM[8'hDD][15:10]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_pc_r_1 = {_RANDOM[8'hDD][31:16], _RANDOM[8'hDE][24:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :383:46, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist = _RANDOM[8'hE0][18:11]; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_mask_1_REG = _RANDOM[8'hE3][13]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_tagePreds_1_r = _RANDOM[8'hE3][14]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :380:56, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_takens_1_r = _RANDOM[8'hE3][15]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :381:53, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_oldCtrs_1_r = _RANDOM[8'hE3][21:16]; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :382:54, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_pc_r_1 = {_RANDOM[8'hE3][31:22], _RANDOM[8'hE4][30:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:379:49, :383:46, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist = _RANDOM[8'hE8][31:24]; // @[src/main/scala/xiangshan/frontend/SC.scala:384:55, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_0_value_REG = _RANDOM[8'hE9][20:19]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_0_value_REG_1 = _RANDOM[8'hE9][22:21]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_1_value_REG = _RANDOM[8'hE9][24:23]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_1_value_REG_1 = _RANDOM[8'hE9][26:25]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_2_value_REG = _RANDOM[8'hE9][28:27]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + io_perf_2_value_REG_1 = _RANDOM[8'hE9][30:29]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Tage.scala:926:7] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - bankTickCtrDistanceToTops_0 = 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrDistanceToTops_1 = 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 - bankTickCtrs_0 = 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - bankTickCtrs_1 = 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 - useAltOnNaCtrs_0_0 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_1 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_2 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_3 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_4 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_5 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_6 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_7 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_8 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_9 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_10 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_11 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_12 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_13 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_14 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_15 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_16 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_17 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_18 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_19 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_20 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_21 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_22 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_23 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_24 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_25 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_26 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_27 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_28 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_29 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_30 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_31 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_32 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_33 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_34 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_35 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_36 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_37 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_38 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_39 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_40 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_41 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_42 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_43 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_44 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_45 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_46 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_47 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_48 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_49 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_50 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_51 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_52 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_53 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_54 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_55 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_56 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_57 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_58 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_59 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_60 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_61 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_62 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_63 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_64 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_65 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_66 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_67 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_68 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_69 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_70 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_71 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_72 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_73 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_74 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_75 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_76 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_77 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_78 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_79 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_80 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_81 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_82 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_83 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_84 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_85 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_86 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_87 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_88 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_89 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_90 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_91 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_92 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_93 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_94 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_95 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_96 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_97 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_98 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_99 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_100 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_101 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_102 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_103 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_104 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_105 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_106 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_107 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_108 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_109 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_110 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_111 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_112 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_113 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_114 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_115 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_116 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_117 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_118 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_119 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_120 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_121 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_122 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_123 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_124 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_125 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_126 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_0_127 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_0 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_1 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_2 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_3 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_4 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_5 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_6 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_7 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_8 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_9 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_10 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_11 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_12 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_13 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_14 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_15 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_16 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_17 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_18 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_19 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_20 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_21 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_22 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_23 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_24 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_25 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_26 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_27 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_28 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_29 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_30 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_31 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_32 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_33 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_34 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_35 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_36 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_37 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_38 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_39 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_40 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_41 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_42 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_43 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_44 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_45 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_46 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_47 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_48 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_49 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_50 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_51 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_52 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_53 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_54 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_55 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_56 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_57 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_58 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_59 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_60 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_61 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_62 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_63 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_64 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_65 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_66 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_67 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_68 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_69 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_70 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_71 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_72 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_73 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_74 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_75 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_76 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_77 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_78 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_79 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_80 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_81 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_82 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_83 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_84 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_85 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_86 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_87 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_88 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_89 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_90 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_91 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_92 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_93 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_94 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_95 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_96 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_97 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_98 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_99 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_100 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_101 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_102 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_103 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_104 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_105 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_106 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_107 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_108 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_109 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_110 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_111 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_112 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_113 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_114 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_115 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_116 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_117 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_118 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_119 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_120 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_121 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_122 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_123 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_124 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_125 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_126 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - useAltOnNaCtrs_1_127 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 - allocLFSR_lfsr = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 - allocLFSR_lfsr_1 = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 - scThresholds_0_ctr = 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - scThresholds_0_thres = 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 - scThresholds_1_ctr = 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 - scThresholds_1_thres = 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + bankTickCtrDistanceToTops_0 = 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrDistanceToTops_1 = 7'h7F; // @[src/main/scala/xiangshan/frontend/Tage.scala:561:58] + bankTickCtrs_0 = 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + bankTickCtrs_1 = 7'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:562:45] + useAltOnNaCtrs_0_0 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_1 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_2 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_3 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_4 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_5 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_6 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_7 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_8 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_9 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_10 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_11 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_12 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_13 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_14 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_15 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_16 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_17 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_18 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_19 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_20 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_21 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_22 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_23 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_24 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_25 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_26 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_27 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_28 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_29 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_30 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_31 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_32 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_33 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_34 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_35 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_36 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_37 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_38 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_39 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_40 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_41 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_42 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_43 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_44 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_45 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_46 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_47 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_48 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_49 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_50 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_51 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_52 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_53 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_54 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_55 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_56 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_57 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_58 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_59 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_60 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_61 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_62 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_63 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_64 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_65 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_66 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_67 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_68 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_69 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_70 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_71 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_72 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_73 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_74 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_75 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_76 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_77 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_78 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_79 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_80 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_81 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_82 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_83 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_84 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_85 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_86 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_87 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_88 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_89 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_90 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_91 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_92 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_93 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_94 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_95 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_96 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_97 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_98 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_99 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_100 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_101 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_102 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_103 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_104 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_105 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_106 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_107 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_108 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_109 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_110 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_111 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_112 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_113 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_114 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_115 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_116 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_117 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_118 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_119 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_120 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_121 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_122 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_123 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_124 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_125 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_126 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_0_127 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_0 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_1 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_2 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_3 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_4 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_5 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_6 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_7 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_8 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_9 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_10 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_11 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_12 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_13 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_14 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_15 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_16 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_17 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_18 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_19 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_20 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_21 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_22 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_23 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_24 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_25 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_26 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_27 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_28 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_29 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_30 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_31 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_32 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_33 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_34 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_35 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_36 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_37 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_38 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_39 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_40 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_41 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_42 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_43 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_44 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_45 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_46 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_47 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_48 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_49 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_50 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_51 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_52 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_53 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_54 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_55 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_56 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_57 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_58 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_59 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_60 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_61 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_62 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_63 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_64 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_65 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_66 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_67 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_68 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_69 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_70 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_71 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_72 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_73 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_74 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_75 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_76 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_77 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_78 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_79 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_80 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_81 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_82 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_83 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_84 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_85 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_86 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_87 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_88 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_89 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_90 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_91 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_92 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_93 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_94 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_95 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_96 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_97 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_98 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_99 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_100 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_101 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_102 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_103 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_104 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_105 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_106 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_107 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_108 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_109 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_110 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_111 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_112 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_113 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_114 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_115 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_116 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_117 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_118 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_119 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_120 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_121 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_122 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_123 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_124 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_125 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_126 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + useAltOnNaCtrs_1_127 = 4'h8; // @[src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14] + allocLFSR_lfsr = 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + allocLFSR_lfsr_1 = 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33] + scThresholds_0_ctr = 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + scThresholds_0_thres = 8'h6; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] + scThresholds_1_ctr = 5'h10; // @[src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52] + scThresholds_1_thres = 8'h6; // @[src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:926:7] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:926:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_2 reset_vector_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in (io_reset_vector), .io_out (_reset_vector_delay_io_out) ); - TageTable tables_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + TageTable tables_0 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] .clock (clock), .reset (reset), .io_req_ready (_tables_0_io_req_ready), @@ -5539,27 +5590,27 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resps_1_bits_ctr (_tables_0_io_resps_1_bits_ctr), .io_resps_1_bits_u (_tables_0_io_resps_1_bits_u), .io_resps_1_bits_unconf (_tables_0_io_resps_1_bits_unconf), - .io_update_pc (tables_0_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_pc (tables_0_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] .io_update_folded_hist_hist_14_folded_hist - (tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_0_io_update_folded_hist_r_1_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_7_folded_hist - (tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - .io_update_mask_0 (tables_0_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_mask_1 (tables_0_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_takens_0 (tables_0_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_takens_1 (tables_0_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_alloc_0 (tables_0_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_alloc_1 (tables_0_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_oldCtrs_0 (tables_0_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_oldCtrs_1 (tables_0_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_uMask_0 (tables_0_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_uMask_1 (tables_0_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_us_0 (tables_0_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_us_1 (tables_0_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_reset_u_0 (tables_0_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - .io_update_reset_u_1 (tables_0_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + (tables_0_io_update_folded_hist_r_1_hist_7_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + .io_update_mask_0 (tables_0_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_mask_1 (tables_0_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_takens_0 (tables_0_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_takens_1 (tables_0_io_update_takens_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_alloc_0 (tables_0_io_update_alloc_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_alloc_1 (tables_0_io_update_alloc_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_oldCtrs_0 (tables_0_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_oldCtrs_1 (tables_0_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_uMask_0 (tables_0_io_update_uMask_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_uMask_1 (tables_0_io_update_uMask_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_us_0 (tables_0_io_update_us_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_us_1 (tables_0_io_update_us_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_reset_u_0 (tables_0_io_update_reset_u_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + .io_update_reset_u_1 (tables_0_io_update_reset_u_1_REG) // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] ); - TageTable_1 tables_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + TageTable_1 tables_1 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] .clock (clock), .reset (reset), .io_req_ready (_tables_1_io_req_ready), @@ -5579,29 +5630,29 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resps_1_bits_ctr (_tables_1_io_resps_1_bits_ctr), .io_resps_1_bits_u (_tables_1_io_resps_1_bits_u), .io_resps_1_bits_unconf (_tables_1_io_resps_1_bits_unconf), - .io_update_pc (tables_1_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_pc (tables_1_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] .io_update_folded_hist_hist_15_folded_hist - (tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_1_io_update_folded_hist_r_1_hist_15_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_4_folded_hist - (tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_1_io_update_folded_hist_r_1_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_1_folded_hist - (tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - .io_update_mask_0 (tables_1_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_mask_1 (tables_1_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_takens_0 (tables_1_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_takens_1 (tables_1_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_alloc_0 (tables_1_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_alloc_1 (tables_1_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_oldCtrs_0 (tables_1_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_oldCtrs_1 (tables_1_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_uMask_0 (tables_1_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_uMask_1 (tables_1_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_us_0 (tables_1_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_us_1 (tables_1_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_reset_u_0 (tables_1_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - .io_update_reset_u_1 (tables_1_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + (tables_1_io_update_folded_hist_r_1_hist_1_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + .io_update_mask_0 (tables_1_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_mask_1 (tables_1_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_takens_0 (tables_1_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_takens_1 (tables_1_io_update_takens_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_alloc_0 (tables_1_io_update_alloc_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_alloc_1 (tables_1_io_update_alloc_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_oldCtrs_0 (tables_1_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_oldCtrs_1 (tables_1_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_uMask_0 (tables_1_io_update_uMask_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_uMask_1 (tables_1_io_update_uMask_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_us_0 (tables_1_io_update_us_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_us_1 (tables_1_io_update_us_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_reset_u_0 (tables_1_io_update_reset_u_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + .io_update_reset_u_1 (tables_1_io_update_reset_u_1_REG) // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] ); - TageTable_2 tables_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + TageTable_2 tables_2 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] .clock (clock), .reset (reset), .io_req_ready (_tables_2_io_req_ready), @@ -5621,29 +5672,29 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resps_1_bits_ctr (_tables_2_io_resps_1_bits_ctr), .io_resps_1_bits_u (_tables_2_io_resps_1_bits_u), .io_resps_1_bits_unconf (_tables_2_io_resps_1_bits_unconf), - .io_update_pc (tables_2_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_pc (tables_2_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] .io_update_folded_hist_hist_17_folded_hist - (tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_2_io_update_folded_hist_r_1_hist_17_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_9_folded_hist - (tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_2_io_update_folded_hist_r_1_hist_9_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_3_folded_hist - (tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - .io_update_mask_0 (tables_2_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_mask_1 (tables_2_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_takens_0 (tables_2_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_takens_1 (tables_2_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_alloc_0 (tables_2_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_alloc_1 (tables_2_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_oldCtrs_0 (tables_2_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_oldCtrs_1 (tables_2_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_uMask_0 (tables_2_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_uMask_1 (tables_2_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_us_0 (tables_2_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_us_1 (tables_2_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_reset_u_0 (tables_2_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - .io_update_reset_u_1 (tables_2_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + (tables_2_io_update_folded_hist_r_1_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + .io_update_mask_0 (tables_2_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_mask_1 (tables_2_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_takens_0 (tables_2_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_takens_1 (tables_2_io_update_takens_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_alloc_0 (tables_2_io_update_alloc_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_alloc_1 (tables_2_io_update_alloc_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_oldCtrs_0 (tables_2_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_oldCtrs_1 (tables_2_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_uMask_0 (tables_2_io_update_uMask_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_uMask_1 (tables_2_io_update_uMask_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_us_0 (tables_2_io_update_us_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_us_1 (tables_2_io_update_us_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_reset_u_0 (tables_2_io_update_reset_u_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + .io_update_reset_u_1 (tables_2_io_update_reset_u_1_REG) // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] ); - TageTable_3 tables_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + TageTable_3 tables_3 ( // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21] .clock (clock), .reset (reset), .io_req_ready (_tables_3_io_req_ready), @@ -5663,29 +5714,29 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resps_1_bits_ctr (_tables_3_io_resps_1_bits_ctr), .io_resps_1_bits_u (_tables_3_io_resps_1_bits_u), .io_resps_1_bits_unconf (_tables_3_io_resps_1_bits_unconf), - .io_update_pc (tables_3_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_pc (tables_3_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:845:42] .io_update_folded_hist_hist_16_folded_hist - (tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_3_io_update_folded_hist_r_1_hist_16_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_8_folded_hist - (tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + (tables_3_io_update_folded_hist_r_1_hist_8_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] .io_update_folded_hist_hist_5_folded_hist - (tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 - .io_update_mask_0 (tables_3_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_mask_1 (tables_3_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 - .io_update_takens_0 (tables_3_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_takens_1 (tables_3_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 - .io_update_alloc_0 (tables_3_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_alloc_1 (tables_3_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 - .io_update_oldCtrs_0 (tables_3_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_oldCtrs_1 (tables_3_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 - .io_update_uMask_0 (tables_3_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_uMask_1 (tables_3_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 - .io_update_us_0 (tables_3_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_us_1 (tables_3_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 - .io_update_reset_u_0 (tables_3_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 - .io_update_reset_u_1 (tables_3_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + (tables_3_io_update_folded_hist_r_1_hist_5_folded_hist), // @[src/main/scala/xiangshan/frontend/Tage.scala:846:51] + .io_update_mask_0 (tables_3_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_mask_1 (tables_3_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:837:48] + .io_update_takens_0 (tables_3_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_takens_1 (tables_3_io_update_takens_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:838:49] + .io_update_alloc_0 (tables_3_io_update_alloc_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_alloc_1 (tables_3_io_update_alloc_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:839:48] + .io_update_oldCtrs_0 (tables_3_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_oldCtrs_1 (tables_3_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:840:50] + .io_update_uMask_0 (tables_3_io_update_uMask_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_uMask_1 (tables_3_io_update_uMask_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:842:48] + .io_update_us_0 (tables_3_io_update_us_0_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_us_1 (tables_3_io_update_us_1_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:843:45] + .io_update_reset_u_0 (tables_3_io_update_reset_u_0_REG), // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] + .io_update_reset_u_1 (tables_3_io_update_reset_u_1_REG) // @[src/main/scala/xiangshan/frontend/Tage.scala:836:48] ); - TageBTable bt ( // src/main/scala/xiangshan/frontend/Tage.scala:557:19 + TageBTable bt ( // @[src/main/scala/xiangshan/frontend/Tage.scala:557:19] .clock (clock), .reset (reset), .io_req_ready (_bt_io_req_ready), @@ -5693,15 +5744,15 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_req_bits (io_in_bits_s0_pc_1), .io_s1_cnt_0 (_bt_io_s1_cnt_0), .io_s1_cnt_1 (_bt_io_s1_cnt_1), - .io_update_mask_0 (REG_2_0), // src/main/scala/xiangshan/frontend/Tage.scala:848:31 - .io_update_mask_1 (REG_2_1), // src/main/scala/xiangshan/frontend/Tage.scala:848:31 - .io_update_pc (bt_io_update_pc_REG), // src/main/scala/xiangshan/frontend/Tage.scala:850:29 - .io_update_cnt_0 (REG_3_0), // src/main/scala/xiangshan/frontend/Tage.scala:849:30 - .io_update_cnt_1 (REG_3_1), // src/main/scala/xiangshan/frontend/Tage.scala:849:30 - .io_update_takens_0 (REG_4_0), // src/main/scala/xiangshan/frontend/Tage.scala:851:33 - .io_update_takens_1 (REG_4_1) // src/main/scala/xiangshan/frontend/Tage.scala:851:33 + .io_update_mask_0 (REG_2_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31] + .io_update_mask_1 (REG_2_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:850:31] + .io_update_pc (bt_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/Tage.scala:852:31] + .io_update_cnt_0 (r_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:851:32] + .io_update_cnt_1 (r_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:851:32] + .io_update_takens_0 (r_1_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:853:35] + .io_update_takens_1 (r_1_1) // @[src/main/scala/xiangshan/frontend/Tage.scala:853:35] ); - SCTable scTables_0 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + SCTable scTables_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -5710,17 +5761,17 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resp_ctrs_0_1 (_scTables_0_io_resp_ctrs_0_1), .io_resp_ctrs_1_0 (_scTables_0_io_resp_ctrs_1_0), .io_resp_ctrs_1_1 (_scTables_0_io_resp_ctrs_1_1), - .io_update_pc (scTables_0_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 - .io_update_mask_0 (scTables_0_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_mask_1 (scTables_0_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_oldCtrs_0 (scTables_0_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_oldCtrs_1 (scTables_0_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_tagePreds_0 (scTables_0_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_tagePreds_1 (scTables_0_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_takens_0 (scTables_0_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 - .io_update_takens_1 (scTables_0_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + .io_update_pc (scTables_0_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] + .io_update_mask_0 (scTables_0_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_mask_1 (scTables_0_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_oldCtrs_0 (scTables_0_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_oldCtrs_1 (scTables_0_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_tagePreds_0 (scTables_0_io_update_tagePreds_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_tagePreds_1 (scTables_0_io_update_tagePreds_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_takens_0 (scTables_0_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + .io_update_takens_1 (scTables_0_io_update_takens_1_r) // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] ); - SCTable_1 scTables_1 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + SCTable_1 scTables_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -5731,19 +5782,19 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resp_ctrs_0_1 (_scTables_1_io_resp_ctrs_0_1), .io_resp_ctrs_1_0 (_scTables_1_io_resp_ctrs_1_0), .io_resp_ctrs_1_1 (_scTables_1_io_resp_ctrs_1_1), - .io_update_pc (scTables_1_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_pc (scTables_1_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] .io_update_folded_hist_hist_12_folded_hist - (scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 - .io_update_mask_0 (scTables_1_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_mask_1 (scTables_1_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_oldCtrs_0 (scTables_1_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_oldCtrs_1 (scTables_1_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_tagePreds_0 (scTables_1_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_tagePreds_1 (scTables_1_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_takens_0 (scTables_1_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 - .io_update_takens_1 (scTables_1_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + (scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + .io_update_mask_0 (scTables_1_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_mask_1 (scTables_1_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_oldCtrs_0 (scTables_1_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_oldCtrs_1 (scTables_1_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_tagePreds_0 (scTables_1_io_update_tagePreds_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_tagePreds_1 (scTables_1_io_update_tagePreds_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_takens_0 (scTables_1_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + .io_update_takens_1 (scTables_1_io_update_takens_1_r) // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] ); - SCTable_2 scTables_2 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + SCTable_2 scTables_2 ( // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -5754,19 +5805,19 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resp_ctrs_0_1 (_scTables_2_io_resp_ctrs_0_1), .io_resp_ctrs_1_0 (_scTables_2_io_resp_ctrs_1_0), .io_resp_ctrs_1_1 (_scTables_2_io_resp_ctrs_1_1), - .io_update_pc (scTables_2_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_pc (scTables_2_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] .io_update_folded_hist_hist_11_folded_hist - (scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 - .io_update_mask_0 (scTables_2_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_mask_1 (scTables_2_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_oldCtrs_0 (scTables_2_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_oldCtrs_1 (scTables_2_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_tagePreds_0 (scTables_2_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_tagePreds_1 (scTables_2_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_takens_0 (scTables_2_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 - .io_update_takens_1 (scTables_2_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + (scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + .io_update_mask_0 (scTables_2_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_mask_1 (scTables_2_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_oldCtrs_0 (scTables_2_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_oldCtrs_1 (scTables_2_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_tagePreds_0 (scTables_2_io_update_tagePreds_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_tagePreds_1 (scTables_2_io_update_tagePreds_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_takens_0 (scTables_2_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + .io_update_takens_1 (scTables_2_io_update_takens_1_r) // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] ); - SCTable_3 scTables_3 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + SCTable_3 scTables_3 ( // @[src/main/scala/xiangshan/frontend/SC.scala:217:23] .clock (clock), .reset (reset), .io_req_valid (io_s0_fire_3), @@ -5777,44 +5828,44 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 .io_resp_ctrs_0_1 (_scTables_3_io_resp_ctrs_0_1), .io_resp_ctrs_1_0 (_scTables_3_io_resp_ctrs_1_0), .io_resp_ctrs_1_1 (_scTables_3_io_resp_ctrs_1_1), - .io_update_pc (scTables_3_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_pc (scTables_3_io_update_pc_r_1), // @[src/main/scala/xiangshan/frontend/SC.scala:383:46] .io_update_folded_hist_hist_2_folded_hist - (scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 - .io_update_mask_0 (scTables_3_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_mask_1 (scTables_3_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 - .io_update_oldCtrs_0 (scTables_3_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_oldCtrs_1 (scTables_3_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 - .io_update_tagePreds_0 (scTables_3_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_tagePreds_1 (scTables_3_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 - .io_update_takens_0 (scTables_3_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 - .io_update_takens_1 (scTables_3_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + (scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/SC.scala:384:55] + .io_update_mask_0 (scTables_3_io_update_mask_0_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_mask_1 (scTables_3_io_update_mask_1_REG), // @[src/main/scala/xiangshan/frontend/SC.scala:379:49] + .io_update_oldCtrs_0 (scTables_3_io_update_oldCtrs_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_oldCtrs_1 (scTables_3_io_update_oldCtrs_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:382:54] + .io_update_tagePreds_0 (scTables_3_io_update_tagePreds_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_tagePreds_1 (scTables_3_io_update_tagePreds_1_r), // @[src/main/scala/xiangshan/frontend/SC.scala:380:56] + .io_update_takens_0 (scTables_3_io_update_takens_0_r), // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] + .io_update_takens_1 (scTables_3_io_update_takens_1_r) // @[src/main/scala/xiangshan/frontend/SC.scala:381:53] ); assign io_out_s2_full_pred_0_br_taken_mask_0 = - tage_enable_dup_REG & s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG & s2_tageTakens_dup_0_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_0_br_taken_mask_1 = - tage_enable_dup_REG_1 & s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG_1 & s2_tageTakens_dup_0_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_1_br_taken_mask_0 = - tage_enable_dup_REG & s2_tageTakens_dup_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG & s2_tageTakens_dup_1_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_1_br_taken_mask_1 = - tage_enable_dup_REG_1 & s2_tageTakens_dup_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG_1 & s2_tageTakens_dup_1_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_2_br_taken_mask_0 = - tage_enable_dup_REG & s2_tageTakens_dup_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG & s2_tageTakens_dup_2_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_2_br_taken_mask_1 = - tage_enable_dup_REG_1 & s2_tageTakens_dup_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG_1 & s2_tageTakens_dup_2_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_3_br_taken_mask_0 = - tage_enable_dup_REG & s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + tage_enable_dup_REG & s2_tageTakens_dup_3_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] assign io_out_s2_full_pred_3_br_taken_mask_1 = - tage_enable_dup_REG_1 & s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 - assign io_out_s3_full_pred_0_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_0; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_0_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_0_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_1_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_1_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_1_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_2_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_2; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_2_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_2_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_3_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_3; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 - assign io_out_s3_full_pred_3_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + tage_enable_dup_REG_1 & s2_tageTakens_dup_3_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :926:7] + assign io_out_s3_full_pred_0_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_0; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_0_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_0_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_1_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_1_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_1_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_2_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_2; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_2_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_2_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_3_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_3; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] + assign io_out_s3_full_pred_3_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_3_1; // @[src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :926:7] assign io_out_last_stage_meta = - {131'h0, + {135'h0, resp_meta_providers_1_valid_r, resp_meta_providers_1_bits_r, resp_meta_providers_0_valid_r, @@ -5841,16 +5892,19 @@ module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 resp_meta_scMeta_scUsed_0_r, resp_meta_scMeta_scPreds_1_r, resp_meta_scMeta_scPreds_0_r, - r_1_3, - r_1_2, - r_1_1, - r_1_0, - r_3, - r_2, - r_1, - r_0}; // src/main/scala/xiangshan/frontend/SC.scala:296:40, :297:40, :298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:606:26, :667:49, :668:49, :669:49, :686:40, :699:41, :700:41, :702:41, :703:41, :924:7 + r_3_3, + r_3_2, + r_3_1, + r_3_0, + r_2_3, + r_2_2, + r_2_1, + r_2_0}; // @[src/main/scala/xiangshan/frontend/SC.scala:296:40, :297:40, :298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:606:26, :667:49, :668:49, :669:49, :686:40, :699:41, :700:41, :702:41, :703:41, :926:7] assign io_s1_ready = _tables_0_io_req_ready & _tables_1_io_req_ready & _tables_2_io_req_ready - & _tables_3_io_req_ready & _bt_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :557:19, :854:60, :924:7 + & _tables_3_io_req_ready & _bt_io_req_ready; // @[src/main/scala/xiangshan/frontend/Tage.scala:549:21, :557:19, :856:60, :926:7] + assign io_perf_0_value = {4'h0, io_perf_0_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :926:7] + assign io_perf_1_value = {4'h0, io_perf_1_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :926:7] + assign io_perf_2_value = {4'h0, io_perf_2_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :926:7] endmodule diff --git a/rtl/TageSC/array_4.sv b/rtl/TageSC/array_4.sv index 22347ed..98acdbd 100644 --- a/rtl/TageSC/array_4.sv +++ b/rtl/TageSC/array_4.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,7 +55,7 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_4( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_4( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, @@ -65,7 +65,7 @@ module array_4( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 input [15:0] RW0_wmask ); - array_4_ext array_4_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_4_ext array_4_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), diff --git a/rtl/TageSC/array_5.sv b/rtl/TageSC/array_5.sv index 1cdac7c..c2e6940 100644 --- a/rtl/TageSC/array_5.sv +++ b/rtl/TageSC/array_5.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,7 +55,7 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_5( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_5( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [8:0] RW0_addr, input RW0_en, input RW0_clk, @@ -65,7 +65,7 @@ module array_5( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 input [1:0] RW0_wmask ); - array_5_ext array_5_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_5_ext array_5_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), diff --git a/rtl/TageSC/array_6.sv b/rtl/TageSC/array_6.sv index e0e1c02..f676f55 100644 --- a/rtl/TageSC/array_6.sv +++ b/rtl/TageSC/array_6.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,7 +55,7 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_6( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_6( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [8:0] R0_addr, input R0_en, input R0_clk, @@ -67,7 +67,7 @@ module array_6( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 input [7:0] W0_mask ); - array_6_ext array_6_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_6_ext array_6_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), diff --git a/rtl/TageSC/array_7.sv b/rtl/TageSC/array_7.sv index 540116e..59beef0 100644 --- a/rtl/TageSC/array_7.sv +++ b/rtl/TageSC/array_7.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,7 +55,7 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module array_7( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 +module array_7( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] input [7:0] R0_addr, input R0_en, input R0_clk, @@ -67,7 +67,7 @@ module array_7( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 input [3:0] W0_mask ); - array_7_ext array_7_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + array_7_ext array_7_ext ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), diff --git a/rtl/TageSC/data_mem_0_8x3.sv b/rtl/TageSC/data_mem_0_8x3.sv index 1dc4ba6..c1a624a 100644 --- a/rtl/TageSC/data_mem_0_8x3.sv +++ b/rtl/TageSC/data_mem_0_8x3.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_mem_0_8x3( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +module data_mem_0_8x3( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] input [2:0] R0_addr, input R0_en, input R0_clk, @@ -67,23 +67,23 @@ module data_mem_0_8x3( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 input [2:0] W0_data ); - reg [2:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & 1'h1) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr] <= W0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [2:0] Memory[0:7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + always @(posedge W0_clk) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & 1'h1) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr] <= W0_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef ENABLE_INITIAL_MEM_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + reg [31:0] _RANDOM_MEM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `ifdef RANDOMIZE_MEM_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin - _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[i[2:0]] = _RANDOM_MEM[2:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + _RANDOM_MEM = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[i[2:0]] = _RANDOM_MEM[2:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + end // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 3'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R0_data = R0_en ? Memory[R0_addr] : 3'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] endmodule diff --git a/rtl/TageSC/data_mem_16x12.sv b/rtl/TageSC/data_mem_16x12.sv index 48bbe85..feb1068 100644 --- a/rtl/TageSC/data_mem_16x12.sv +++ b/rtl/TageSC/data_mem_16x12.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_mem_16x12( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +module data_mem_16x12( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] input [3:0] R0_addr, input R0_en, input R0_clk, @@ -72,26 +72,26 @@ module data_mem_16x12( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 input [1:0] W0_mask ); - reg [11:0] Memory[0:15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [11:0] Memory[0:15]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + always @(posedge W0_clk) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & W0_mask[0]) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & W0_mask[1]) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef ENABLE_INITIAL_MEM_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + reg [31:0] _RANDOM_MEM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `ifdef RANDOMIZE_MEM_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin - _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[i[3:0]] = _RANDOM_MEM[11:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + _RANDOM_MEM = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[i[3:0]] = _RANDOM_MEM[11:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + end // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - assign R1_data = R1_en ? Memory[R1_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R0_data = R0_en ? Memory[R0_addr] : 12'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + assign R1_data = R1_en ? Memory[R1_addr] : 12'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] endmodule diff --git a/rtl/TageSC/data_mem_8x4.sv b/rtl/TageSC/data_mem_8x4.sv index 540a7d9..ffd55f9 100644 --- a/rtl/TageSC/data_mem_8x4.sv +++ b/rtl/TageSC/data_mem_8x4.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -56,7 +56,7 @@ `endif // not def SYNTHESIS // VCS coverage exclude_file -module data_mem_8x4( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +module data_mem_8x4( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] input [2:0] R0_addr, input R0_en, input R0_clk, @@ -72,26 +72,26 @@ module data_mem_8x4( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 input [1:0] W0_mask ); - reg [3:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [3:0] Memory[0:7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + always @(posedge W0_clk) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & W0_mask[0]) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + if (W0_en & W0_mask[1]) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef ENABLE_INITIAL_MEM_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + reg [31:0] _RANDOM_MEM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + `ifdef RANDOMIZE_MEM_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin - _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - Memory[i[2:0]] = _RANDOM_MEM[3:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + _RANDOM_MEM = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + Memory[i[2:0]] = _RANDOM_MEM[3:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + end // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] `endif // RANDOMIZE_MEM_INIT end // initial `endif // ENABLE_INITIAL_MEM_ - assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - assign R1_data = R1_en ? Memory[R1_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + assign R1_data = R1_en ? Memory[R1_addr] : 4'bx; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] endmodule diff --git a/rtl/Tage_SC.txt b/rtl/Tage_SC.txt index 7eba1fe..111fe70 100644 --- a/rtl/Tage_SC.txt +++ b/rtl/Tage_SC.txt @@ -1,30 +1,30 @@ -./rtl/TageSC/SRAMTemplate_31.sv -./rtl/TageSC/data_mem_0_8x3.sv -./rtl/TageSC/SCTable.sv -./rtl/TageSC/SRAMTemplate_11.sv -./rtl/TageSC/CAMTemplate_32.sv -./rtl/TageSC/array_6.sv -./rtl/TageSC/SCTable_1.sv -./rtl/TageSC/array_5.sv -./rtl/TageSC/TageTable_1.sv -./rtl/TageSC/FoldedSRAMTemplate_1.sv -./rtl/TageSC/SRAMTemplate_10.sv -./rtl/TageSC/SRAMTemplate_30.sv -./rtl/TageSC/FoldedSRAMTemplate.sv -./rtl/TageSC/CAMTemplate_33.sv -./rtl/TageSC/data_mem_16x12.sv -./rtl/TageSC/TageBTable.sv -./rtl/TageSC/TageTable_3.sv -./rtl/TageSC/data_mem_8x4.sv -./rtl/TageSC/array_4.sv -./rtl/TageSC/TageTable_2.sv -./rtl/TageSC/TageTable.sv -./rtl/TageSC/array_7.sv -./rtl/TageSC/SCTable_2.sv -./rtl/TageSC/FoldedSRAMTemplate_20.sv ./rtl/TageSC/CAMTemplate.sv -./rtl/TageSC/Tage_SC.sv +./rtl/TageSC/CAMTemplate_32.sv +./rtl/TageSC/CAMTemplate_33.sv +./rtl/TageSC/FoldedSRAMTemplate.sv +./rtl/TageSC/FoldedSRAMTemplate_1.sv +./rtl/TageSC/FoldedSRAMTemplate_20.sv +./rtl/TageSC/SCTable.sv +./rtl/TageSC/SCTable_1.sv +./rtl/TageSC/SCTable_2.sv ./rtl/TageSC/SCTable_3.sv +./rtl/TageSC/SRAMTemplate_14.sv +./rtl/TageSC/SRAMTemplate_15.sv +./rtl/TageSC/SRAMTemplate_34.sv +./rtl/TageSC/SRAMTemplate_35.sv +./rtl/TageSC/TageBTable.sv +./rtl/TageSC/TageTable.sv +./rtl/TageSC/TageTable_1.sv +./rtl/TageSC/TageTable_2.sv +./rtl/TageSC/TageTable_3.sv +./rtl/TageSC/Tage_SC.sv +./rtl/TageSC/array_4.sv +./rtl/TageSC/array_5.sv +./rtl/TageSC/array_6.sv +./rtl/TageSC/array_7.sv +./rtl/TageSC/data_mem_0_8x3.sv +./rtl/TageSC/data_mem_16x12.sv +./rtl/TageSC/data_mem_8x4.sv # ./rtl/WrBypass/WrBypass.sv ./rtl/WrBypass/WrBypass_32.sv diff --git a/rtl/WrBypass/WrBypass.sv b/rtl/WrBypass/WrBypass.sv index 13c7a8c..6ce07b4 100644 --- a/rtl/WrBypass/WrBypass.sv +++ b/rtl/WrBypass/WrBypass.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,114 +55,113 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [2:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [2:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [8:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [2:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit_data_0_valid, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [2:0] io_hit_data_0_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_7_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] wire [2:0] _hit_idx_T_2 = - {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 - wire [2:0] data_mem_io_hit_data_0_bits_MPORT_addr = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] + wire [2:0] hit_idx = {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, |(_hit_idx_T_2[2:1]), - _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 - | hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 - reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + | hits_oh_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29] + reg [6:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] wire [2:0] enq_idx = {state_reg[6], state_reg[6] ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} - : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire [2:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - wire _GEN = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_0 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_1 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_2 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_3 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_4 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_5 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - always @(posedge clock or posedge reset) begin - if (reset) begin - valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + wire _GEN = enq_idx == 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_0 = enq_idx == 3'h1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_1 = enq_idx == 3'h2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_2 = enq_idx == 3'h3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_3 = enq_idx == 3'h4; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_4 = enq_idx == 3'h5; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_5 = enq_idx == 3'h6; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 7'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h0 | valids_0_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_1_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h1 | valids_1_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_2_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h2 | valids_2_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_3_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h3 | valids_3_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_4_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h4 | valids_4_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_5_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h5 | valids_5_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_6_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h6 | valids_6_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 - valids_7_0 <= (&data_mem_io_hit_data_0_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (io_wen) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + if (hit) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= hit_idx == 3'h0 | valids_0_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_1_0 <= hit_idx == 3'h1 | valids_1_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_2_0 <= hit_idx == 3'h2 | valids_2_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_3_0 <= hit_idx == 3'h3 | valids_3_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_4_0 <= hit_idx == 3'h4 | valids_4_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_5_0 <= hit_idx == 3'h5 | valids_5_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_6_0 <= hit_idx == 3'h6 | valids_6_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] + valids_7_0 <= (&hit_idx) | valids_7_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30] end - else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= _GEN | ~_GEN & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 - valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= _GEN | ~_GEN & valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] + valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30] end state_reg <= {~(state_reg_touch_way_sized[2]), @@ -183,72 +182,72 @@ module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 : state_reg[1], state_reg_touch_way_sized[1] ? state_reg[0] - : ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + : ~(state_reg_touch_way_sized[0])}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end - ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 7'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), @@ -259,24 +258,24 @@ module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_0_8x3 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_0_8x3 data_mem_0_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (io_hit_data_0_bits), - .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), .W0_data (io_write_data_0) ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] assign io_hit_data_0_valid = hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 - & valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 + & valids_6_0 | hits_oh_7 & valids_7_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83] endmodule diff --git a/rtl/WrBypass/WrBypass_32.sv b/rtl/WrBypass/WrBypass_32.sv index 9e3abdc..1a045a6 100644 --- a/rtl/WrBypass/WrBypass_32.sv +++ b/rtl/WrBypass/WrBypass_32.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,162 +55,159 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_32( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [10:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_32( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [10:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_1, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input io_write_way_mask_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input io_write_way_mask_1, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit_data_0_valid, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_0_bits, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit_data_1_valid, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_1_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire [3:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - wire [3:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [3:0] _data_mem_ext_R0_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + wire [3:0] _data_mem_ext_R1_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_7_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_7_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] wire [2:0] _hit_idx_T_2 = - {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 - wire [2:0] data_mem_io_hit_data_1_bits_MPORT_addr = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] + wire [2:0] hit_idx = {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, |(_hit_idx_T_2[2:1]), - _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 - | hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 - reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + | hits_oh_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29] + reg [6:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] wire [2:0] enq_idx = {state_reg[6], state_reg[6] ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} - : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire [2:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - wire _GEN_6 = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_7 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_8 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_9 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_10 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_11 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_12 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - always @(posedge clock or posedge reset) begin - if (reset) begin - valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire _GEN = hit_idx == 3'h0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_0 = hit_idx == 3'h1; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_1 = hit_idx == 3'h2; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_2 = hit_idx == 3'h3; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_3 = hit_idx == 3'h4; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_4 = hit_idx == 3'h5; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_5 = hit_idx == 3'h6; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + wire _GEN_6 = enq_idx == 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_7 = enq_idx == 3'h1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_8 = enq_idx == 3'h2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_9 = enq_idx == 3'h3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_10 = enq_idx == 3'h4; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_11 = enq_idx == 3'h5; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_12 = enq_idx == 3'h6; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 7'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_7_0 <= - io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_7_1 <= - io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (io_wen) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + if (hit) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_7_0 <= io_write_way_mask_0 & (&hit_idx) | valids_7_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_7_1 <= io_write_way_mask_1 & (&hit_idx) | valids_7_1; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] end - else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] end state_reg <= {~(state_reg_touch_way_sized[2]), @@ -231,89 +228,89 @@ module WrBypass_32( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 : state_reg[1], state_reg_touch_way_sized[1] ? state_reg[0] - : ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + : ~(state_reg_touch_way_sized[0])}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end - ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] ever_written_7 <= - io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 7'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_32 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_32 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), @@ -324,35 +321,35 @@ module WrBypass_32( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_8x4 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_8x4 data_mem_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (_data_mem_ext_R0_data), - .R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R1_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R1_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R1_clk (clock), .R1_data (_data_mem_ext_R1_data), - .W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), - .W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .W0_data ({io_write_data_1, io_write_data_0}), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] assign io_hit_data_0_valid = hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 - & valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 - assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + & valids_6_0 | hits_oh_7 & valids_7_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83] + assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21] assign io_hit_data_1_valid = hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 - & valids_6_1 | hits_oh_7 & valids_7_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 - assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + & valids_6_1 | hits_oh_7 & valids_7_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83] + assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21] endmodule diff --git a/rtl/WrBypass/WrBypass_33.sv b/rtl/WrBypass/WrBypass_33.sv index de0d07d..c6618e2 100644 --- a/rtl/WrBypass/WrBypass_33.sv +++ b/rtl/WrBypass/WrBypass_33.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,109 +55,109 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [5:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [5:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [5:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [5:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_33( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [7:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [5:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [5:0] io_write_data_1, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input io_write_way_mask_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input io_write_way_mask_1, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit_data_0_valid, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [5:0] io_hit_data_0_bits, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit_data_1_valid, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [5:0] io_hit_data_1_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire [11:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - wire [11:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_15_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg valids_15_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [11:0] _data_mem_ext_R0_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + wire [11:0] _data_mem_ext_R1_data; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_8; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_9; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_10; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_11; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_12; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_13; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_14; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_15; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_7_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_7_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_8_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_8_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_9_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_9_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_10_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_10_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_11_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_11_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_12_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_12_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_13_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_13_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_14_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_14_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_15_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg valids_15_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_8; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_9; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_10; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_11; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_12; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_13; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_14; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_15; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] wire [6:0] _hit_idx_T_2 = {hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9} - | {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 - wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 - wire [3:0] data_mem_io_hit_data_1_bits_MPORT_addr = + | {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] + wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] + wire [3:0] hit_idx = {|{hits_oh_15, hits_oh_14, hits_oh_13, @@ -168,12 +168,12 @@ module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 hits_oh_8}, |(_hit_idx_T_2[6:3]), |(_hit_idx_T_4[2:1]), - _hit_idx_T_4[2] | _hit_idx_T_4[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + _hit_idx_T_4[2] | _hit_idx_T_4[0]}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 | hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12 - | hits_oh_13 | hits_oh_14 | hits_oh_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 - reg [14:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + | hits_oh_13 | hits_oh_14 | hits_oh_15; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29] + reg [14:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] wire [3:0] enq_idx = {state_reg[14], state_reg[14] @@ -184,162 +184,159 @@ module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 : {state_reg[6], state_reg[6] ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} - : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h0; // src/main/scala/chisel3/util/OneHot.scala:32:{10,14}, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_6 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h7; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_7 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h8; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_8 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h9; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_9 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hA; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_10 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hB; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_11 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hC; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_12 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hD; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire _GEN_13 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hE; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 - wire [3:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - wire _GEN_14 = enq_idx == 4'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:98:31 - wire _GEN_15 = enq_idx == 4'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_16 = enq_idx == 4'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_17 = enq_idx == 4'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_18 = enq_idx == 4'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_19 = enq_idx == 4'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_20 = enq_idx == 4'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_21 = enq_idx == 4'h7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_22 = enq_idx == 4'h8; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_23 = enq_idx == 4'h9; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_24 = enq_idx == 4'hA; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_25 = enq_idx == 4'hB; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_26 = enq_idx == 4'hC; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_27 = enq_idx == 4'hD; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - wire _GEN_28 = enq_idx == 4'hE; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 - always @(posedge clock or posedge reset) begin - if (reset) begin - valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_8 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_9 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_10 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_11 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_12 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_13 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_14 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_15 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire _GEN = hit_idx == 4'h0; // @[src/main/scala/chisel3/util/OneHot.scala:32:{10,14}, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_0 = hit_idx == 4'h1; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_1 = hit_idx == 4'h2; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_2 = hit_idx == 4'h3; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_3 = hit_idx == 4'h4; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_4 = hit_idx == 4'h5; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_5 = hit_idx == 4'h6; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_6 = hit_idx == 4'h7; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_7 = hit_idx == 4'h8; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_8 = hit_idx == 4'h9; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_9 = hit_idx == 4'hA; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_10 = hit_idx == 4'hB; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_11 = hit_idx == 4'hC; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_12 = hit_idx == 4'hD; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire _GEN_13 = hit_idx == 4'hE; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30] + wire [3:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + wire _GEN_14 = enq_idx == 4'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:98:31] + wire _GEN_15 = enq_idx == 4'h1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_16 = enq_idx == 4'h2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_17 = enq_idx == 4'h3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_18 = enq_idx == 4'h4; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_19 = enq_idx == 4'h5; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_20 = enq_idx == 4'h6; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_21 = enq_idx == 4'h7; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_22 = enq_idx == 4'h8; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_23 = enq_idx == 4'h9; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_24 = enq_idx == 4'hA; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_25 = enq_idx == 4'hB; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_26 = enq_idx == 4'hC; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_27 = enq_idx == 4'hD; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + wire _GEN_28 = enq_idx == 4'hE; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_8 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_9 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_10 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_11 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_12 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_13 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_14 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_15 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 15'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_15_0 <= - io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 - valids_15_1 <= - io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (io_wen) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + if (hit) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_15_0 <= io_write_way_mask_0 & (&hit_idx) | valids_15_0; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] + valids_15_1 <= io_write_way_mask_1 & (&hit_idx) | valids_15_1; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30] end - else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 - valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 - valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29] + valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] + valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30] end state_reg <= {~(state_reg_touch_way_sized[3]), @@ -384,147 +381,147 @@ module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 : state_reg[1], state_reg_touch_way_sized[1] ? state_reg[0] - : ~(state_reg_touch_way_sized[0])}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + : ~(state_reg_touch_way_sized[0])}}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end - ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] ever_written_15 <= - io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - end // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = _RANDOM[1'h0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 = _RANDOM[1'h0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = _RANDOM[1'h0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 = _RANDOM[1'h0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = _RANDOM[1'h0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 = _RANDOM[1'h0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = _RANDOM[1'h0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 = _RANDOM[1'h0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = _RANDOM[1'h0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 = _RANDOM[1'h0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = _RANDOM[1'h0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 = _RANDOM[1'h0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = _RANDOM[1'h0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 = _RANDOM[1'h0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = _RANDOM[1'h0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 = _RANDOM[1'h0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_0 = _RANDOM[1'h0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_1 = _RANDOM[1'h0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_0 = _RANDOM[1'h0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_1 = _RANDOM[1'h0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_0 = _RANDOM[1'h0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_1 = _RANDOM[1'h0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_0 = _RANDOM[1'h0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_1 = _RANDOM[1'h0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_0 = _RANDOM[1'h0][24]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_1 = _RANDOM[1'h0][25]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_0 = _RANDOM[1'h0][26]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_1 = _RANDOM[1'h0][27]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_0 = _RANDOM[1'h0][28]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_1 = _RANDOM[1'h0][29]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_0 = _RANDOM[1'h0][30]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_1 = _RANDOM[1'h0][31]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = _RANDOM[1'h1][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = _RANDOM[1'h1][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = _RANDOM[1'h1][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = _RANDOM[1'h1][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 = _RANDOM[1'h1][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 = _RANDOM[1'h1][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 = _RANDOM[1'h1][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 = _RANDOM[1'h1][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_8 = _RANDOM[1'h1][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_9 = _RANDOM[1'h1][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_10 = _RANDOM[1'h1][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_11 = _RANDOM[1'h1][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_12 = _RANDOM[1'h1][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_13 = _RANDOM[1'h1][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_14 = _RANDOM[1'h1][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_15 = _RANDOM[1'h1][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = _RANDOM[1'h1][30:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + _RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + end // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = _RANDOM[1'h0][0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 = _RANDOM[1'h0][1]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = _RANDOM[1'h0][2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 = _RANDOM[1'h0][3]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = _RANDOM[1'h0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 = _RANDOM[1'h0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = _RANDOM[1'h0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 = _RANDOM[1'h0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = _RANDOM[1'h0][8]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 = _RANDOM[1'h0][9]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = _RANDOM[1'h0][10]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 = _RANDOM[1'h0][11]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = _RANDOM[1'h0][12]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 = _RANDOM[1'h0][13]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = _RANDOM[1'h0][14]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 = _RANDOM[1'h0][15]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_0 = _RANDOM[1'h0][16]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_1 = _RANDOM[1'h0][17]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_0 = _RANDOM[1'h0][18]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_1 = _RANDOM[1'h0][19]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_0 = _RANDOM[1'h0][20]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_1 = _RANDOM[1'h0][21]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_0 = _RANDOM[1'h0][22]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_1 = _RANDOM[1'h0][23]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_0 = _RANDOM[1'h0][24]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_1 = _RANDOM[1'h0][25]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_0 = _RANDOM[1'h0][26]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_1 = _RANDOM[1'h0][27]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_0 = _RANDOM[1'h0][28]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_1 = _RANDOM[1'h0][29]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_0 = _RANDOM[1'h0][30]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_1 = _RANDOM[1'h0][31]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = _RANDOM[1'h1][0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = _RANDOM[1'h1][1]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = _RANDOM[1'h1][2]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = _RANDOM[1'h1][3]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 = _RANDOM[1'h1][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 = _RANDOM[1'h1][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 = _RANDOM[1'h1][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 = _RANDOM[1'h1][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_8 = _RANDOM[1'h1][8]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_9 = _RANDOM[1'h1][9]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_10 = _RANDOM[1'h1][10]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_11 = _RANDOM[1'h1][11]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_12 = _RANDOM[1'h1][12]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_13 = _RANDOM[1'h1][13]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_14 = _RANDOM[1'h1][14]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_15 = _RANDOM[1'h1][15]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = _RANDOM[1'h1][30:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_8_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_9_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_10_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_11_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_12_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_13_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_14_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - valids_15_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_8 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_9 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_10 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_11 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_12 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_13 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_14 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_15 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + valids_0_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_0_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_1_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_2_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_3_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_4_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_5_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_6_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_7_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_8_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_9_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_10_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_11_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_12_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_13_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_14_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + valids_15_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_4 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_5 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_6 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_7 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_8 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_9 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_10 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_11 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_12 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_13 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_14 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_15 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 15'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_33 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_33 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), @@ -543,41 +540,41 @@ module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 .io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13), .io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14), .io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_16x12 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_16x12 data_mem_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (_data_mem_ext_R0_data), - .R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R1_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R1_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R1_clk (clock), .R1_data (_data_mem_ext_R1_data), - .W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), - .W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .W0_data ({io_write_data_1, io_write_data_0}), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] assign io_hit_data_0_valid = hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 & valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9 & valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12 & valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15 - & valids_15_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 - assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + & valids_15_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83] + assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21] assign io_hit_data_1_valid = hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 & valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9 & valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12 & valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15 - & valids_15_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 - assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + & valids_15_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83] + assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21] endmodule diff --git a/rtl/WrBypass/WrBypass_41.sv b/rtl/WrBypass/WrBypass_41.sv index 420c0ae..9257dbd 100644 --- a/rtl/WrBypass/WrBypass_41.sv +++ b/rtl/WrBypass/WrBypass_41.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,105 +55,103 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_41( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_41( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [7:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_0_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = - {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = - _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 - reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 - wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire [1:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - always @(posedge clock or posedge reset) begin - if (reset) begin - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29] + reg [2:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + if (io_wen) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] state_reg <= {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], - state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_41 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_41 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_0_4x2 data_mem_0_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (io_hit_data_0_bits), - .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), .W0_data (io_write_data_0) ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] endmodule diff --git a/rtl/WrBypass/WrBypass_43.sv b/rtl/WrBypass/WrBypass_43.sv index b3782c0..e55c343 100644 --- a/rtl/WrBypass/WrBypass_43.sv +++ b/rtl/WrBypass/WrBypass_43.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,105 +55,103 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module WrBypass_43( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - input clock, - input reset, - input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 - output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +module WrBypass_43( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + input io_wen, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [8:0] io_write_idx, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + input [1:0] io_write_data_0, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output io_hit, // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] + output [1:0] io_hit_data_0_bits // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] ); - wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 - reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 - wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 - wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = - {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire _idx_tag_cam_io_r_resp_0_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + wire _idx_tag_cam_io_r_resp_0_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] + reg ever_written_0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + reg ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:57:29] + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83] + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83] wire hit = - _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 - reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 - wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 - wire [1:0] state_reg_touch_way_sized = - hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 - always @(posedge clock or posedge reset) begin - if (reset) begin - ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29] + reg [2:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13] + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg <= 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 - ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 - if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + else begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31] + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31] + if (io_wen) // @[src/main/scala/xiangshan/frontend/WrBypass.scala:34:14] state_reg <= {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], - state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37] end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 - state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + ever_written_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + ever_written_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29] + state_reg = 3'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CAMTemplate_43 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + CAMTemplate_43 idx_tag_cam ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:53:27] .clock (clock), .io_r_req_0_idx (io_write_idx), .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), - .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_valid (io_wen & ~hit), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}] .io_w_bits_data_idx (io_write_idx), - .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + .io_w_bits_index (enq_idx) // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12] ); - data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 - .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 - .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + data_mem_0_4x2 data_mem_0_ext ( // @[src/main/scala/xiangshan/frontend/WrBypass.scala:54:21] + .R0_addr (hit_idx), // @[src/main/scala/chisel3/util/OneHot.scala:32:10] + .R0_en (1'h1), // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7] .R0_clk (clock), .R0_data (io_hit_data_0_bits), - .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_addr (hit ? hit_idx : enq_idx), // @[rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29] .W0_en (io_wen), .W0_clk (clock), .W0_data (io_write_data_0) ); - assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit = hit; // @[src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29] endmodule diff --git a/rtl/common/Composer.sv b/rtl/common/Composer.sv index 7f5bb6b..d7dd151 100644 --- a/rtl/common/Composer.sv +++ b/rtl/common/Composer.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,563 +55,640 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 - input clock, - input reset, - input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [4:0] io_out_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s3_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s3_redirect_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_full_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [4:0] io_redirect_bits_cfiUpdate_NOS_value // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module Composer( // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + input clock, // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + input reset, // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_spec_info_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_spec_info_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_spec_info_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [4:0] io_out_last_stage_spec_info_NOS_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_last_stage_spec_info_topAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_ubtb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_btb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_tage_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_sc_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_ras_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s3_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s3_redirect_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_s1_ready, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_cfi_idx_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_cfi_idx_bits, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_jmp_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_mispred_mask_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_old_entry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_full_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_level, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_redirect_bits_cfiUpdate_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isRVC, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_pd_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_redirect_bits_cfiUpdate_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_redirect_bits_cfiUpdate_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_redirect_bits_cfiUpdate_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [4:0] io_redirect_bits_cfiUpdate_NOS_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [5:0] io_perf_0_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_1_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_2_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_3_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_4_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_5_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_6_value // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] ); - wire _ras_io_ctrl_delay_io_out_ras_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ftb_io_ctrl_delay_io_out_btb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _tage_io_ctrl_delay_io_out_tage_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _tage_io_ctrl_delay_io_out_sc_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ubtb_io_ctrl_delay_io_out_ubtb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ittage_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [38:0] _ittage_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [218:0] _ittage_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [11:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [1:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [19:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [1:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [3:0] _ittage_io_out_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire _ittage_io_out_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/Parameters.scala:113:26 - wire [218:0] _ras_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:112:23 - wire _tage_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire [218:0] _tage_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire _tage_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:111:24 - wire [218:0] _ubtb_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:109:23 - wire _ftb_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [38:0] _ftb_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [218:0] _ftb_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [11:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [1:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [19:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [1:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire [3:0] _ftb_io_out_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_out_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/Parameters.scala:108:23 - wire _ftb_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:108:23 - FTB ftb ( // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ras_io_ctrl_delay_io_out_ras_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ftb_io_ctrl_delay_io_out_btb_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _tage_io_ctrl_delay_io_out_tage_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _tage_io_ctrl_delay_io_out_sc_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ubtb_io_ctrl_delay_io_out_ubtb_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_is_call; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_is_ret; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_is_call; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_is_ret; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [40:0] _ittage_io_out_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [222:0] _ittage_io_out_last_stage_meta; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_valid; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [11:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [1:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [19:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [1:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [3:0] _ittage_io_out_last_stage_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_carry; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_isCall; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_isRet; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_isJalr; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire _ittage_io_out_last_stage_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/Parameters.scala:133:26] + wire [222:0] _ras_io_out_last_stage_meta; // @[src/main/scala/xiangshan/Parameters.scala:132:23] + wire _tage_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire [222:0] _tage_io_out_last_stage_meta; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire _tage_io_s1_ready; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire [5:0] _tage_io_perf_0_value; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire [5:0] _tage_io_perf_1_value; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire [5:0] _tage_io_perf_2_value; // @[src/main/scala/xiangshan/Parameters.scala:131:24] + wire [222:0] _ubtb_io_out_last_stage_meta; // @[src/main/scala/xiangshan/Parameters.scala:129:23] + wire [5:0] _ubtb_io_perf_0_value; // @[src/main/scala/xiangshan/Parameters.scala:129:23] + wire [5:0] _ubtb_io_perf_1_value; // @[src/main/scala/xiangshan/Parameters.scala:129:23] + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_is_call; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_is_ret; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_is_call; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_is_ret; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [40:0] _ftb_io_out_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [222:0] _ftb_io_out_last_stage_meta; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_valid; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [11:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [1:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [19:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [1:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [3:0] _ftb_io_out_last_stage_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_carry; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_isCall; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_isRet; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_isJalr; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_out_last_stage_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire _ftb_io_s1_ready; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [5:0] _ftb_io_perf_0_value; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + wire [5:0] _ftb_io_perf_1_value; // @[src/main/scala/xiangshan/Parameters.scala:128:23] + reg [5:0] io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_2_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_3_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_3_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_4_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_4_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_5_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_5_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_6_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_6_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_0_value_REG <= _ubtb_io_perf_0_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:129:23] + io_perf_0_value_REG_1 <= io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_1_value_REG <= _ubtb_io_perf_1_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:129:23] + io_perf_1_value_REG_1 <= io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_2_value_REG <= _tage_io_perf_0_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:131:24] + io_perf_2_value_REG_1 <= io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_3_value_REG <= _tage_io_perf_1_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:131:24] + io_perf_3_value_REG_1 <= io_perf_3_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_4_value_REG <= _tage_io_perf_2_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:131:24] + io_perf_4_value_REG_1 <= io_perf_4_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_5_value_REG <= _ftb_io_perf_0_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:128:23] + io_perf_5_value_REG_1 <= io_perf_5_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_6_value_REG <= _ftb_io_perf_1_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/Parameters.scala:128:23] + io_perf_6_value_REG_1 <= io_perf_6_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:18]; // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + initial begin // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + for (logic [4:0] i = 5'h0; i < 5'h13; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + end // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_0_value_REG = _RANDOM[5'hF][19:14]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_0_value_REG_1 = _RANDOM[5'hF][25:20]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_1_value_REG = _RANDOM[5'hF][31:26]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_1_value_REG_1 = _RANDOM[5'h10][5:0]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_2_value_REG = _RANDOM[5'h10][11:6]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_2_value_REG_1 = _RANDOM[5'h10][17:12]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_3_value_REG = _RANDOM[5'h10][23:18]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_3_value_REG_1 = _RANDOM[5'h10][29:24]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_4_value_REG = {_RANDOM[5'h10][31:30], _RANDOM[5'h11][3:0]}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_4_value_REG_1 = _RANDOM[5'h11][9:4]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_5_value_REG = _RANDOM[5'h11][15:10]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_5_value_REG_1 = _RANDOM[5'h11][21:16]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_6_value_REG = _RANDOM[5'h11][27:22]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + io_perf_6_value_REG_1 = {_RANDOM[5'h11][31:28], _RANDOM[5'h12][1:0]}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Composer.scala:26:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FTB ftb ( // @[src/main/scala/xiangshan/Parameters.scala:128:23] .clock (clock), .reset (reset), .io_reset_vector (io_reset_vector), @@ -620,37 +697,37 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 - (_tage_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 - (_tage_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 - (_tage_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 - (_tage_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 - (_tage_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 - (_tage_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 - (_tage_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 - (_tage_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s2_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 - (_tage_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 - (_tage_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 - (_tage_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 - (_tage_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 - (_tage_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 - (_tage_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 - (_tage_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 - (_tage_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + (_tage_io_out_s3_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:131:24] .io_out_s2_full_pred_0_br_taken_mask_0 (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), .io_out_s2_full_pred_0_br_taken_mask_1 @@ -887,7 +964,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_last_stage_ftb_entry_always_taken_1 (_ftb_io_out_last_stage_ftb_entry_always_taken_1), .io_ctrl_btb_enable - (_ftb_io_ctrl_delay_io_out_btb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ftb_io_ctrl_delay_io_out_btb_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_s0_fire_0 (io_s0_fire_0), .io_s0_fire_1 (io_s0_fire_1), .io_s0_fire_2 (io_s0_fire_2), @@ -940,9 +1017,11 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 (io_update_bits_ftb_entry_always_taken_1), .io_update_bits_old_entry (io_update_bits_old_entry), .io_update_bits_meta - ({122'h0, io_update_bits_meta[218:122]}) // src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31 + ({126'h0, io_update_bits_meta[222:126]}), // @[src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31] + .io_perf_0_value (_ftb_io_perf_0_value), + .io_perf_1_value (_ftb_io_perf_1_value) ); - FauFTB ubtb ( // src/main/scala/xiangshan/Parameters.scala:109:23 + FauFTB ubtb ( // @[src/main/scala/xiangshan/Parameters.scala:129:23] .clock (clock), .reset (reset), .io_reset_vector (io_reset_vector), @@ -1000,7 +1079,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_s1_full_pred_3_is_br_sharing (io_out_s1_full_pred_3_is_br_sharing), .io_out_s1_full_pred_3_hit (io_out_s1_full_pred_3_hit), .io_out_last_stage_meta (_ubtb_io_out_last_stage_meta), - .io_ctrl_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_s0_fire_0 (io_s0_fire_0), .io_s0_fire_1 (io_s0_fire_1), .io_s0_fire_2 (io_s0_fire_2), @@ -1030,9 +1109,12 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_update_bits_ftb_entry_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), .io_update_bits_ftb_entry_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), .io_update_bits_br_taken_mask_0 (io_update_bits_br_taken_mask_0), - .io_update_bits_br_taken_mask_1 (io_update_bits_br_taken_mask_1) + .io_update_bits_br_taken_mask_1 (io_update_bits_br_taken_mask_1), + .io_update_bits_meta ({217'h0, io_update_bits_meta[222:217]}), // @[src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31] + .io_perf_0_value (_ubtb_io_perf_0_value), + .io_perf_1_value (_ubtb_io_perf_1_value) ); - Tage_SC tage ( // src/main/scala/xiangshan/Parameters.scala:111:24 + Tage_SC tage ( // @[src/main/scala/xiangshan/Parameters.scala:131:24] .clock (clock), .reset (reset), .io_reset_vector (io_reset_vector), @@ -1102,9 +1184,9 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_last_stage_meta (_tage_io_out_last_stage_meta), .io_ctrl_tage_enable - (_tage_io_ctrl_delay_io_out_tage_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_tage_io_ctrl_delay_io_out_tage_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_ctrl_sc_enable - (_tage_io_ctrl_delay_io_out_sc_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_tage_io_ctrl_delay_io_out_sc_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_s0_fire_0 (io_s0_fire_0), .io_s0_fire_1 (io_s0_fire_1), .io_s0_fire_3 (io_s0_fire_3), @@ -1166,9 +1248,12 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_update_bits_mispred_mask_1 (io_update_bits_mispred_mask_1), .io_update_bits_meta - ({125'h0, io_update_bits_meta[218:125]}) // src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31 + ({129'h0, io_update_bits_meta[222:129]}), // @[src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31] + .io_perf_0_value (_tage_io_perf_0_value), + .io_perf_1_value (_tage_io_perf_1_value), + .io_perf_2_value (_tage_io_perf_2_value) ); - RAS ras ( // src/main/scala/xiangshan/Parameters.scala:112:23 + RAS ras ( // @[src/main/scala/xiangshan/Parameters.scala:132:23] .clock (clock), .reset (reset), .io_reset_vector (io_reset_vector), @@ -1177,247 +1262,247 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 - (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 - (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 - (_ittage_io_out_s2_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 - (_ittage_io_out_s2_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 - (_ittage_io_out_s2_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 - (_ittage_io_out_s2_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target - (_ittage_io_out_s2_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 - (_ittage_io_out_s2_full_pred_0_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 - (_ittage_io_out_s2_full_pred_0_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr - (_ittage_io_out_s2_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing - (_ittage_io_out_s2_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_0_hit - (_ittage_io_out_s2_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_0_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 - (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 - (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 - (_ittage_io_out_s2_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 - (_ittage_io_out_s2_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 - (_ittage_io_out_s2_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 - (_ittage_io_out_s2_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target - (_ittage_io_out_s2_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 - (_ittage_io_out_s2_full_pred_1_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 - (_ittage_io_out_s2_full_pred_1_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr - (_ittage_io_out_s2_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing - (_ittage_io_out_s2_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_1_hit - (_ittage_io_out_s2_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_1_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 - (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 - (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 - (_ittage_io_out_s2_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 - (_ittage_io_out_s2_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 - (_ittage_io_out_s2_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 - (_ittage_io_out_s2_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target - (_ittage_io_out_s2_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 - (_ittage_io_out_s2_full_pred_2_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 - (_ittage_io_out_s2_full_pred_2_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr - (_ittage_io_out_s2_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr - (_ittage_io_out_s2_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_is_jalr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_is_call - (_ittage_io_out_s2_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_is_call), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_is_ret - (_ittage_io_out_s2_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_is_ret), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call - (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing - (_ittage_io_out_s2_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_2_hit - (_ittage_io_out_s2_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_2_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 - (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 - (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 - (_ittage_io_out_s2_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 - (_ittage_io_out_s2_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 - (_ittage_io_out_s2_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 - (_ittage_io_out_s2_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target - (_ittage_io_out_s2_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 - (_ittage_io_out_s2_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 - (_ittage_io_out_s2_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr - (_ittage_io_out_s2_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr - (_ittage_io_out_s2_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing - (_ittage_io_out_s2_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s2_full_pred_3_hit - (_ittage_io_out_s2_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s2_full_pred_3_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 - (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 - (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 - (_ittage_io_out_s3_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 - (_ittage_io_out_s3_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 - (_ittage_io_out_s3_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 - (_ittage_io_out_s3_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target - (_ittage_io_out_s3_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr - (_ittage_io_out_s3_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr - (_ittage_io_out_s3_full_pred_0_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing - (_ittage_io_out_s3_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_0_hit - (_ittage_io_out_s3_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_0_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 - (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 - (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 - (_ittage_io_out_s3_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 - (_ittage_io_out_s3_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 - (_ittage_io_out_s3_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 - (_ittage_io_out_s3_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target - (_ittage_io_out_s3_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr - (_ittage_io_out_s3_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr - (_ittage_io_out_s3_full_pred_1_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing - (_ittage_io_out_s3_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_1_hit - (_ittage_io_out_s3_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_1_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 - (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 - (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 - (_ittage_io_out_s3_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 - (_ittage_io_out_s3_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 - (_ittage_io_out_s3_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 - (_ittage_io_out_s3_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target - (_ittage_io_out_s3_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr - (_ittage_io_out_s3_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr - (_ittage_io_out_s3_full_pred_2_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr - (_ittage_io_out_s3_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_is_jalr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_is_call - (_ittage_io_out_s3_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_is_call), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_is_ret - (_ittage_io_out_s3_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_is_ret), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing - (_ittage_io_out_s3_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_2_hit - (_ittage_io_out_s3_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_2_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 - (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 - (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 - (_ittage_io_out_s3_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 - (_ittage_io_out_s3_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 - (_ittage_io_out_s3_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 - (_ittage_io_out_s3_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target - (_ittage_io_out_s3_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 - (_ittage_io_out_s3_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 - (_ittage_io_out_s3_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr - (_ittage_io_out_s3_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr - (_ittage_io_out_s3_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing - (_ittage_io_out_s3_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_s3_full_pred_3_hit - (_ittage_io_out_s3_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_s3_full_pred_3_hit), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_valid - (_ittage_io_out_last_stage_ftb_entry_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_valid), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset - (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower - (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat - (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing - (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid - (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset - (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower - (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat - (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing - (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid - (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr - (_ittage_io_out_last_stage_ftb_entry_pftAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_carry - (_ittage_io_out_last_stage_ftb_entry_carry), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_carry), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall - (_ittage_io_out_last_stage_ftb_entry_isCall), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_isCall), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet - (_ittage_io_out_last_stage_ftb_entry_isRet), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_isRet), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr - (_ittage_io_out_last_stage_ftb_entry_isJalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_isJalr), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call - (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 - (_ittage_io_out_last_stage_ftb_entry_always_taken_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 - (_ittage_io_out_last_stage_ftb_entry_always_taken_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + (_ittage_io_out_last_stage_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/Parameters.scala:133:26] .io_out_s2_pc_0 (io_out_s2_pc_0), .io_out_s2_pc_1 (io_out_s2_pc_1), .io_out_s2_pc_2 (io_out_s2_pc_2), @@ -1659,7 +1744,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_last_stage_ftb_entry_always_taken_1 (io_out_last_stage_ftb_entry_always_taken_1), .io_ctrl_ras_enable - (_ras_io_ctrl_delay_io_out_ras_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ras_io_ctrl_delay_io_out_ras_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_s0_fire_0 (io_s0_fire_0), .io_s0_fire_1 (io_s0_fire_1), .io_s0_fire_2 (io_s0_fire_2), @@ -1718,7 +1803,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_redirect_bits_cfiUpdate_NOS_value (io_redirect_bits_cfiUpdate_NOS_value) ); - ITTage ittage ( // src/main/scala/xiangshan/Parameters.scala:113:26 + ITTage ittage ( // @[src/main/scala/xiangshan/Parameters.scala:133:26] .clock (clock), .reset (reset), .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), @@ -1739,247 +1824,247 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_in_bits_folded_hist_3_hist_2_folded_hist (io_in_bits_folded_hist_3_hist_2_folded_hist), .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 - (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 - (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 - (_ftb_io_out_s2_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 - (_ftb_io_out_s2_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 - (_ftb_io_out_s2_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 - (_ftb_io_out_s2_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target - (_ftb_io_out_s2_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 - (_ftb_io_out_s2_full_pred_0_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 - (_ftb_io_out_s2_full_pred_0_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr - (_ftb_io_out_s2_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing - (_ftb_io_out_s2_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_0_hit - (_ftb_io_out_s2_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_0_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 - (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 - (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 - (_ftb_io_out_s2_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 - (_ftb_io_out_s2_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 - (_ftb_io_out_s2_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 - (_ftb_io_out_s2_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target - (_ftb_io_out_s2_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 - (_ftb_io_out_s2_full_pred_1_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 - (_ftb_io_out_s2_full_pred_1_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr - (_ftb_io_out_s2_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing - (_ftb_io_out_s2_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_1_hit - (_ftb_io_out_s2_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_1_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 - (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 - (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 - (_ftb_io_out_s2_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 - (_ftb_io_out_s2_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 - (_ftb_io_out_s2_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 - (_ftb_io_out_s2_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target - (_ftb_io_out_s2_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 - (_ftb_io_out_s2_full_pred_2_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 - (_ftb_io_out_s2_full_pred_2_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr - (_ftb_io_out_s2_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr - (_ftb_io_out_s2_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_is_jalr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_is_call - (_ftb_io_out_s2_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_is_call), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_is_ret - (_ftb_io_out_s2_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_is_ret), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call - (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing - (_ftb_io_out_s2_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_2_hit - (_ftb_io_out_s2_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_2_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 - (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 - (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 - (_ftb_io_out_s2_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 - (_ftb_io_out_s2_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 - (_ftb_io_out_s2_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 - (_ftb_io_out_s2_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target - (_ftb_io_out_s2_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 - (_ftb_io_out_s2_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 - (_ftb_io_out_s2_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr - (_ftb_io_out_s2_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr - (_ftb_io_out_s2_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing - (_ftb_io_out_s2_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s2_full_pred_3_hit - (_ftb_io_out_s2_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s2_full_pred_3_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 - (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 - (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 - (_ftb_io_out_s3_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 - (_ftb_io_out_s3_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 - (_ftb_io_out_s3_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 - (_ftb_io_out_s3_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target - (_ftb_io_out_s3_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr - (_ftb_io_out_s3_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr - (_ftb_io_out_s3_full_pred_0_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing - (_ftb_io_out_s3_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_0_hit - (_ftb_io_out_s3_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_0_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 - (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 - (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 - (_ftb_io_out_s3_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 - (_ftb_io_out_s3_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 - (_ftb_io_out_s3_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 - (_ftb_io_out_s3_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target - (_ftb_io_out_s3_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr - (_ftb_io_out_s3_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr - (_ftb_io_out_s3_full_pred_1_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing - (_ftb_io_out_s3_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_1_hit - (_ftb_io_out_s3_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_1_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 - (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 - (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 - (_ftb_io_out_s3_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 - (_ftb_io_out_s3_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 - (_ftb_io_out_s3_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 - (_ftb_io_out_s3_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target - (_ftb_io_out_s3_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr - (_ftb_io_out_s3_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr - (_ftb_io_out_s3_full_pred_2_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr - (_ftb_io_out_s3_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_is_jalr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_is_call - (_ftb_io_out_s3_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_is_call), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_is_ret - (_ftb_io_out_s3_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_is_ret), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing - (_ftb_io_out_s3_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_2_hit - (_ftb_io_out_s3_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_2_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 - (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 - (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 - (_ftb_io_out_s3_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_slot_valids_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 - (_ftb_io_out_s3_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_slot_valids_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 - (_ftb_io_out_s3_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_targets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 - (_ftb_io_out_s3_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_targets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target - (_ftb_io_out_s3_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_jalr_target), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 - (_ftb_io_out_s3_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_offsets_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 - (_ftb_io_out_s3_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_offsets_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr - (_ftb_io_out_s3_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_fallThroughAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr - (_ftb_io_out_s3_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_fallThroughErr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing - (_ftb_io_out_s3_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_is_br_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_s3_full_pred_3_hit - (_ftb_io_out_s3_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_s3_full_pred_3_hit), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_valid - (_ftb_io_out_last_stage_ftb_entry_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_valid), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset - (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower - (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat - (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing - (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid - (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset - (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower - (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat - (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing - (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid - (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr - (_ftb_io_out_last_stage_ftb_entry_pftAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_carry - (_ftb_io_out_last_stage_ftb_entry_carry), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_carry), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall - (_ftb_io_out_last_stage_ftb_entry_isCall), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_isCall), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet - (_ftb_io_out_last_stage_ftb_entry_isRet), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_isRet), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr - (_ftb_io_out_last_stage_ftb_entry_isJalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_isJalr), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call - (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 - (_ftb_io_out_last_stage_ftb_entry_always_taken_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 - (_ftb_io_out_last_stage_ftb_entry_always_taken_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + (_ftb_io_out_last_stage_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/Parameters.scala:128:23] .io_out_s2_full_pred_0_br_taken_mask_0 (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), .io_out_s2_full_pred_0_br_taken_mask_1 @@ -2267,11 +2352,11 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_update_bits_mispred_mask_2 (io_update_bits_mispred_mask_2), .io_update_bits_meta - ({25'h0, io_update_bits_meta[218:25]}), // src/main/scala/xiangshan/frontend/Composer.scala:59:22, :77:27, :78:31 + ({25'h0, io_update_bits_meta[222:25]}), // @[src/main/scala/xiangshan/frontend/Composer.scala:59:22, :77:27, :78:31] .io_update_bits_full_target (io_update_bits_full_target) ); - DelayN_1 ubtb_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_1 ubtb_io_ctrl_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in_ubtb_enable (io_ctrl_ubtb_enable), .io_in_btb_enable (io_ctrl_btb_enable), @@ -2284,7 +2369,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_sc_enable (/* unused */), .io_out_ras_enable (/* unused */) ); - DelayN_1 tage_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_1 tage_io_ctrl_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in_ubtb_enable (io_ctrl_ubtb_enable), .io_in_btb_enable (io_ctrl_btb_enable), @@ -2297,7 +2382,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_sc_enable (_tage_io_ctrl_delay_io_out_sc_enable), .io_out_ras_enable (/* unused */) ); - DelayN_1 ftb_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_1 ftb_io_ctrl_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in_ubtb_enable (io_ctrl_ubtb_enable), .io_in_btb_enable (io_ctrl_btb_enable), @@ -2310,7 +2395,7 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 .io_out_sc_enable (/* unused */), .io_out_ras_enable (/* unused */) ); - DelayN_1 ras_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_1 ras_io_ctrl_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in_ubtb_enable (io_ctrl_ubtb_enable), .io_in_btb_enable (io_ctrl_btb_enable), @@ -2327,8 +2412,15 @@ module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 {_ubtb_io_out_last_stage_meta[5:0], _tage_io_out_last_stage_meta[87:0], _ftb_io_out_last_stage_meta[2:0], - _ittage_io_out_last_stage_meta[96:0], - _ras_io_out_last_stage_meta[24:0]}; // src/main/scala/xiangshan/Parameters.scala:108:23, :109:23, :111:24, :112:23, :113:26, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :59:64, :72:26 - assign io_s1_ready = _tage_io_s1_ready & _ftb_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:108:23, :111:24, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :68:57 + _ittage_io_out_last_stage_meta[100:0], + _ras_io_out_last_stage_meta[24:0]}; // @[src/main/scala/xiangshan/Parameters.scala:128:23, :129:23, :131:24, :132:23, :133:26, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :59:64, :72:26] + assign io_s1_ready = _tage_io_s1_ready & _ftb_io_s1_ready; // @[src/main/scala/xiangshan/Parameters.scala:128:23, :131:24, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :68:57] + assign io_perf_0_value = io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_1_value = io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_2_value = io_perf_2_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_3_value = io_perf_3_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_4_value = io_perf_4_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_5_value = io_perf_5_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] + assign io_perf_6_value = io_perf_6_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/Composer.scala:26:7] endmodule diff --git a/rtl/common/DelayNWithValid.sv b/rtl/common/DelayNWithValid.sv new file mode 100644 index 0000000..b7b1d07 --- /dev/null +++ b/rtl/common/DelayNWithValid.sv @@ -0,0 +1,107 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayNWithValid( // @[utility/src/main/scala/utility/Hold.scala:106:7] + input clock, // @[utility/src/main/scala/utility/Hold.scala:106:7] + input reset, // @[utility/src/main/scala/utility/Hold.scala:106:7] + input [40:0] io_in_bits, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [40:0] io_out_bits // @[utility/src/main/scala/utility/Hold.scala:107:14] +); + + reg valid_REG; // @[utility/src/main/scala/utility/Hold.scala:117:25] + reg [40:0] data; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [40:0] res_bits; // @[utility/src/main/scala/utility/Hold.scala:121:27] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG <= 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25] + else // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG <= io_in_valid; // @[utility/src/main/scala/utility/Hold.scala:117:25] + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + if (io_in_valid) // @[utility/src/main/scala/utility/Hold.scala:107:14] + data <= io_in_bits; // @[utility/src/main/scala/utility/Hold.scala:121:27] + if (valid_REG) // @[utility/src/main/scala/utility/Hold.scala:117:25] + res_bits <= data; // @[utility/src/main/scala/utility/Hold.scala:121:27] + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // @[utility/src/main/scala/utility/Hold.scala:106:7] + initial begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:106:7] + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:106:7] + end // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG = _RANDOM[2'h0][0]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25] + data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + `endif // RANDOMIZE_REG_INIT + if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG = 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25] + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_bits = res_bits; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] +endmodule + diff --git a/rtl/common/DelayNWithValid_1.sv b/rtl/common/DelayNWithValid_1.sv new file mode 100644 index 0000000..8242920 --- /dev/null +++ b/rtl/common/DelayNWithValid_1.sv @@ -0,0 +1,271 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayNWithValid_1( // @[utility/src/main/scala/utility/Hold.scala:106:7] + input clock, // @[utility/src/main/scala/utility/Hold.scala:106:7] + input reset, // @[utility/src/main/scala/utility/Hold.scala:106:7] + input io_in_bits_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [3:0] io_in_bits_brSlots_0_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [11:0] io_in_bits_brSlots_0_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [1:0] io_in_bits_brSlots_0_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_brSlots_0_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_brSlots_0_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [3:0] io_in_bits_tailSlot_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [19:0] io_in_bits_tailSlot_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [1:0] io_in_bits_tailSlot_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_tailSlot_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_tailSlot_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input [3:0] io_in_bits_pftAddr, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_carry, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_isCall, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_isRet, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_isJalr, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_last_may_be_rvi_call, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_always_taken_0, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_bits_always_taken_1, // @[utility/src/main/scala/utility/Hold.scala:107:14] + input io_in_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [3:0] io_out_bits_brSlots_0_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [11:0] io_out_bits_brSlots_0_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [1:0] io_out_bits_brSlots_0_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_brSlots_0_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_brSlots_0_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [3:0] io_out_bits_tailSlot_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [19:0] io_out_bits_tailSlot_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [1:0] io_out_bits_tailSlot_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_tailSlot_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_tailSlot_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output [3:0] io_out_bits_pftAddr, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_carry, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_isCall, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_isRet, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_isJalr, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_last_may_be_rvi_call, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_always_taken_0, // @[utility/src/main/scala/utility/Hold.scala:107:14] + output io_out_bits_always_taken_1 // @[utility/src/main/scala/utility/Hold.scala:107:14] +); + + reg valid_REG; // @[utility/src/main/scala/utility/Hold.scala:117:25] + reg data_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] data_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [11:0] data_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [1:0] data_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] data_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [19:0] data_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [1:0] data_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] data_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg data_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] res_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [11:0] res_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [1:0] res_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] res_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [19:0] res_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [1:0] res_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg [3:0] res_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27] + reg res_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27] + always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG <= 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25] + else // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG <= io_in_valid; // @[utility/src/main/scala/utility/Hold.scala:117:25] + end // always @(posedge, posedge) + always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + if (io_in_valid) begin // @[utility/src/main/scala/utility/Hold.scala:107:14] + data_valid <= io_in_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_brSlots_0_offset <= io_in_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_brSlots_0_lower <= io_in_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_brSlots_0_tarStat <= io_in_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_brSlots_0_sharing <= io_in_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_brSlots_0_valid <= io_in_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_tailSlot_offset <= io_in_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_tailSlot_lower <= io_in_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_tailSlot_tarStat <= io_in_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_tailSlot_sharing <= io_in_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_tailSlot_valid <= io_in_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_pftAddr <= io_in_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_carry <= io_in_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_isCall <= io_in_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_isRet <= io_in_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_isJalr <= io_in_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_last_may_be_rvi_call <= io_in_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_always_taken_0 <= io_in_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27] + data_always_taken_1 <= io_in_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27] + end + if (valid_REG) begin // @[utility/src/main/scala/utility/Hold.scala:117:25] + res_bits_valid <= data_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_brSlots_0_offset <= data_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_brSlots_0_lower <= data_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_brSlots_0_tarStat <= data_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_brSlots_0_sharing <= data_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_brSlots_0_valid <= data_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_tailSlot_offset <= data_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_tailSlot_lower <= data_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_tailSlot_tarStat <= data_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_tailSlot_sharing <= data_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_tailSlot_valid <= data_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_pftAddr <= data_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_carry <= data_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_isCall <= data_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_isRet <= data_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_isJalr <= data_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_last_may_be_rvi_call <= data_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_always_taken_0 <= data_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27] + res_bits_always_taken_1 <= data_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27] + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // @[utility/src/main/scala/utility/Hold.scala:106:7] + initial begin // @[utility/src/main/scala/utility/Hold.scala:106:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:106:7] + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:106:7] + end // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG = _RANDOM[2'h0][0]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25] + data_valid = _RANDOM[2'h0][1]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_brSlots_0_offset = _RANDOM[2'h0][5:2]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_brSlots_0_lower = _RANDOM[2'h0][17:6]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_brSlots_0_tarStat = _RANDOM[2'h0][19:18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_brSlots_0_sharing = _RANDOM[2'h0][20]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_brSlots_0_valid = _RANDOM[2'h0][21]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_tailSlot_offset = _RANDOM[2'h0][25:22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27] + data_tailSlot_tarStat = _RANDOM[2'h1][15:14]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_tailSlot_sharing = _RANDOM[2'h1][16]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_tailSlot_valid = _RANDOM[2'h1][17]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_pftAddr = _RANDOM[2'h1][21:18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_carry = _RANDOM[2'h1][22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_isCall = _RANDOM[2'h1][23]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_isRet = _RANDOM[2'h1][24]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_isJalr = _RANDOM[2'h1][25]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_last_may_be_rvi_call = _RANDOM[2'h1][26]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_always_taken_0 = _RANDOM[2'h1][27]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + data_always_taken_1 = _RANDOM[2'h1][28]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_valid = _RANDOM[2'h1][30]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_brSlots_0_sharing = _RANDOM[2'h2][17]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_brSlots_0_valid = _RANDOM[2'h2][18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_tailSlot_offset = _RANDOM[2'h2][22:19]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_tailSlot_sharing = _RANDOM[2'h3][13]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_tailSlot_valid = _RANDOM[2'h3][14]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_pftAddr = _RANDOM[2'h3][18:15]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_carry = _RANDOM[2'h3][19]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_isCall = _RANDOM[2'h3][20]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_isRet = _RANDOM[2'h3][21]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_isJalr = _RANDOM[2'h3][22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_always_taken_0 = _RANDOM[2'h3][24]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + res_bits_always_taken_1 = _RANDOM[2'h3][25]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + `endif // RANDOMIZE_REG_INIT + if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7] + valid_REG = 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25] + end // initial + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7] + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_bits_valid = res_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_pftAddr = res_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_carry = res_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_isCall = res_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_isRet = res_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_isJalr = res_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_always_taken_0 = res_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] + assign io_out_bits_always_taken_1 = res_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27] +endmodule + diff --git a/rtl/common/DelayN_2.sv b/rtl/common/DelayN_2.sv index f5d4e31..26e8649 100644 --- a/rtl/common/DelayN_2.sv +++ b/rtl/common/DelayN_2.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,48 +55,48 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module DelayN_2( // utility/src/main/scala/utility/Hold.scala:83:7 - input clock, - input [35:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14 - output [35:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14 +module DelayN_2( // @[utility/src/main/scala/utility/Hold.scala:86:7] + input clock, // @[utility/src/main/scala/utility/Hold.scala:86:7] + input [35:0] io_in, // @[utility/src/main/scala/utility/Hold.scala:87:14] + output [35:0] io_out // @[utility/src/main/scala/utility/Hold.scala:87:14] ); - reg [35:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18 - reg [35:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 - reg [35:0] REG_2; // utility/src/main/scala/utility/Hold.scala:90:18 - reg [35:0] REG_3; // utility/src/main/scala/utility/Hold.scala:90:18 - reg [35:0] REG_4; // utility/src/main/scala/utility/Hold.scala:90:18 - always @(posedge clock) begin - REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18 - REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18 - REG_2 <= REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 - REG_3 <= REG_2; // utility/src/main/scala/utility/Hold.scala:90:18 - REG_4 <= REG_3; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [35:0] REG; // @[utility/src/main/scala/utility/Hold.scala:93:18] + reg [35:0] REG_1; // @[utility/src/main/scala/utility/Hold.scala:93:18] + reg [35:0] REG_2; // @[utility/src/main/scala/utility/Hold.scala:93:18] + reg [35:0] REG_3; // @[utility/src/main/scala/utility/Hold.scala:93:18] + reg [35:0] REG_4; // @[utility/src/main/scala/utility/Hold.scala:93:18] + always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:86:7] + REG <= io_in; // @[utility/src/main/scala/utility/Hold.scala:93:18] + REG_1 <= REG; // @[utility/src/main/scala/utility/Hold.scala:93:18] + REG_2 <= REG_1; // @[utility/src/main/scala/utility/Hold.scala:93:18] + REG_3 <= REG_2; // @[utility/src/main/scala/utility/Hold.scala:93:18] + REG_4 <= REG_3; // @[utility/src/main/scala/utility/Hold.scala:93:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/Hold.scala:83:7 - initial begin // utility/src/main/scala/utility/Hold.scala:83:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + logic [31:0] _RANDOM[0:5]; // @[utility/src/main/scala/utility/Hold.scala:86:7] + initial begin // @[utility/src/main/scala/utility/Hold.scala:86:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:86:7] for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 - end // utility/src/main/scala/utility/Hold.scala:83:7 - REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 - REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 - REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 - REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 - REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + _RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:86:7] + end // @[utility/src/main/scala/utility/Hold.scala:86:7] + REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] + REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] + REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] + REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] + REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_out = REG_4; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out = REG_4; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] endmodule diff --git a/rtl/common/DelayN_4.sv b/rtl/common/DelayN_4.sv index 245ced5..aa54492 100644 --- a/rtl/common/DelayN_4.sv +++ b/rtl/common/DelayN_4.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,39 +55,37 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module DelayN_4( // utility/src/main/scala/utility/Hold.scala:83:7 - input clock, - input [38:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14 - output [38:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14 +module DelayN_4( // @[utility/src/main/scala/utility/Hold.scala:86:7] + input clock, // @[utility/src/main/scala/utility/Hold.scala:86:7] + input io_in, // @[utility/src/main/scala/utility/Hold.scala:87:14] + output io_out // @[utility/src/main/scala/utility/Hold.scala:87:14] ); - reg [38:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18 - reg [38:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 - always @(posedge clock) begin - REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18 - REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG; // @[utility/src/main/scala/utility/Hold.scala:93:18] + reg REG_1; // @[utility/src/main/scala/utility/Hold.scala:93:18] + always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:86:7] + REG <= io_in; // @[utility/src/main/scala/utility/Hold.scala:93:18] + REG_1 <= REG; // @[utility/src/main/scala/utility/Hold.scala:93:18] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 - `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 - `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] + `FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/Hold.scala:83:7 - initial begin // utility/src/main/scala/utility/Hold.scala:83:7 - `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 - `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/Hold.scala:86:7] + initial begin // @[utility/src/main/scala/utility/Hold.scala:86:7] + `ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] + `INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 - end // utility/src/main/scala/utility/Hold.scala:83:7 - REG = {_RANDOM[2'h0], _RANDOM[2'h1][6:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 - REG_1 = {_RANDOM[2'h1][31:7], _RANDOM[2'h2][13:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + `ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:86:7] + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:86:7] + REG = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] + REG_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] `endif // RANDOMIZE_REG_INIT end // initial - `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 - `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] + `FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_out = REG_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out = REG_1; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18] endmodule diff --git a/rtl/common/Predictor.sv b/rtl/common/Predictor.sv index 429e379..79a8b78 100644 --- a/rtl/common/Predictor.sv +++ b/rtl/common/Predictor.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,1901 +55,1903 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - input clock, - input reset, - input io_bpu_to_ftq_resp_ready, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [5:0] io_bpu_to_ftq_resp_bits_s2_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [5:0] io_bpu_to_ftq_resp_bits_s3_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [218:0] io_bpu_to_ftq_resp_bits_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [2:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [1:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [38:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [11:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [19:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [2:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_shift, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [38:0] io_ftq_to_bpu_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [11:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [19:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [3:0] io_ftq_to_bpu_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [218:0] io_ftq_to_bpu_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [38:0] io_ftq_to_bpu_update_bits_full_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ftq_to_bpu_enq_ptr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [5:0] io_ftq_to_bpu_enq_ptr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 - input [35:0] io_reset_vector // src/main/scala/xiangshan/frontend/BPU.scala:222:14 +module Predictor( // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + input clock, // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + input reset, // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + input io_bpu_to_ftq_resp_ready, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s1_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s2_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_valid_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_hasRedirect_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [5:0] io_bpu_to_ftq_resp_bits_s2_ftq_idx_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s3_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_valid_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_hasRedirect_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [5:0] io_bpu_to_ftq_resp_bits_s3_ftq_idx_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [222:0] io_bpu_to_ftq_resp_bits_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [2:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [40:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [11:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [19:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_level, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [40:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [2:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [40:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_shift, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [40:0] io_ftq_to_bpu_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [11:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [19:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_cfi_idx_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [3:0] io_ftq_to_bpu_update_bits_cfi_idx_bits, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_jmp_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_mispred_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_mispred_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_mispred_mask_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_update_bits_old_entry, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [222:0] io_ftq_to_bpu_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [40:0] io_ftq_to_bpu_update_bits_full_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ftq_to_bpu_enq_ptr_flag, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [5:0] io_ftq_to_bpu_enq_ptr_value, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ctrl_ubtb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ctrl_btb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ctrl_tage_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ctrl_sc_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input io_ctrl_ras_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + output [5:0] io_perf_0_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_1_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_2_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_3_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_4_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_5_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_6_value // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] ); - wire s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 - wire s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 - wire s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 - wire s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:605:28 - wire s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:605:28 - wire s1_fire_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - wire s1_fire_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - wire s1_fire_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - wire s1_fire_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - wire _ghv_write_datas_255_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_254_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_253_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_252_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_251_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_250_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_249_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_248_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_247_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_246_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_245_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_244_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_243_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_242_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_241_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_240_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_239_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_238_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_237_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_236_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_235_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_234_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_233_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_232_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_231_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_230_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_229_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_228_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_227_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_226_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_225_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_224_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_223_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_222_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_221_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_220_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_219_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_218_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_217_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_216_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_215_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_214_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_213_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_212_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_211_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_210_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_209_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_208_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_207_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_206_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_205_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_204_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_203_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_202_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_201_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_200_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_199_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_198_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_197_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_196_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_195_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_194_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_193_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_192_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_191_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_190_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_189_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_188_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_187_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_186_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_185_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_184_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_183_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_182_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_181_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_180_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_179_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_178_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_177_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_176_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_175_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_174_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_173_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_172_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_171_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_170_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_169_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_168_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_167_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_166_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_165_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_164_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_163_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_162_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_161_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_160_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_159_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_158_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_157_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_156_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_155_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_154_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_153_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_152_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_151_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_150_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_149_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_148_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_147_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_146_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_145_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_144_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_143_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_142_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_141_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_140_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_139_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_138_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_137_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_136_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_135_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_134_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_133_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_132_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_131_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_130_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_129_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_128_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_127_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_126_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_125_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_124_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_123_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_122_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_121_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_120_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_119_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_118_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_117_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_116_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_115_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_114_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_113_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_112_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_111_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_110_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_109_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_108_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_107_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_106_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_105_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_104_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_103_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_102_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_101_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_100_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_99_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_98_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_97_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_96_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_95_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_94_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_93_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_92_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_91_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_90_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_89_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_88_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_87_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_86_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_85_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_84_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_83_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_82_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_81_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_80_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_79_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_78_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_77_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_76_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_75_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_74_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_73_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_72_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_71_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_70_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_69_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_68_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_67_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_66_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_65_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_64_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_63_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_62_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_61_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_60_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_59_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_58_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_57_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_56_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_55_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_54_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_53_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_52_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_51_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_50_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_49_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_48_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_47_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_46_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_45_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_44_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_43_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_42_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_41_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_40_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_39_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_38_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_37_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_36_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_35_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_34_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_33_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_32_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_31_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_30_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_29_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_28_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_27_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_26_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_25_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_24_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_23_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_22_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_21_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_20_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_19_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_18_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_17_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_16_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_15_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_14_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_13_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_12_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_11_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_10_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_9_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_8_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_7_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_6_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_5_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_4_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _ghv_write_datas_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [2:0] _s0_last_br_num_oh_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [2:0] _s0_last_br_num_oh_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [2:0] _s0_last_br_num_oh_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ghist_ptr_dup_3_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_ghist_ptr_dup_3_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ghist_ptr_dup_2_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_ghist_ptr_dup_2_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ghist_ptr_dup_1_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_ghist_ptr_dup_1_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire _s0_ghist_ptr_dup_0_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_ghist_ptr_dup_0_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [3:0] _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [3:0] _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [3:0] _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [38:0] _s0_pc_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [38:0] _s0_pc_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [38:0] _s0_pc_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [38:0] _s0_pc_dup_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - wire [38:0] _predictors_io_out_s1_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire [38:0] _predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _predictors_io_s1_ready; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 - wire _ctrl_delay_io_out_ubtb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ctrl_delay_io_out_btb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ctrl_delay_io_out_tage_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ctrl_delay_io_out_sc_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - wire _ctrl_delay_io_out_ras_enable; // utility/src/main/scala/utility/Hold.scala:97:23 - reg s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - reg s2_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - reg s3_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - reg [38:0] s0_pc_reg_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 - reg [38:0] s0_pc_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 - reg [38:0] s0_pc_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 - reg [38:0] s0_pc_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 - reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:277:24 - reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:277:16 - reg [10:0] s0_folded_gh_reg_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [3:0] s0_folded_gh_reg_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [3:0] s0_folded_gh_reg_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [3:0] s0_folded_gh_reg_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [8:0] s0_folded_gh_reg_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [6:0] s0_folded_gh_reg_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s0_folded_gh_reg_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [7:0] s0_folded_gh_reg_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - reg [10:0] s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [3:0] s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [3:0] s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [3:0] s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [8:0] s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [6:0] s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [7:0] s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 - reg [10:0] s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [3:0] s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [3:0] s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [3:0] s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [8:0] s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [6:0] s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [7:0] s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 - reg [10:0] s3_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [3:0] s3_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [3:0] s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [3:0] s3_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [8:0] s3_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [6:0] s3_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [10:0] s3_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [7:0] s3_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 - reg [2:0] s0_last_br_num_oh_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 - reg [2:0] s0_last_br_num_oh_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 - reg [2:0] s0_last_br_num_oh_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 - reg [2:0] s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 - reg [2:0] s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 - reg [2:0] s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 - reg [2:0] s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 - reg [2:0] s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 - reg [2:0] s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 - reg [2:0] s3_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 - reg [2:0] s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 - reg [2:0] s3_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 - reg ghv_0; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_1; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_2; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_3; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_4; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_5; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_6; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_7; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_8; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_9; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_10; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_11; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_12; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_13; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_14; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_15; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_16; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_17; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_18; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_19; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_20; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_21; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_22; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_23; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_24; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_25; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_26; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_27; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_28; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_29; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_30; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_31; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_32; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_33; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_34; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_35; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_36; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_37; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_38; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_39; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_40; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_41; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_42; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_43; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_44; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_45; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_46; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_47; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_48; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_49; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_50; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_51; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_52; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_53; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_54; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_55; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_56; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_57; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_58; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_59; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_60; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_61; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_62; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_63; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_64; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_65; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_66; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_67; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_68; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_69; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_70; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_71; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_72; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_73; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_74; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_75; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_76; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_77; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_78; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_79; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_80; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_81; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_82; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_83; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_84; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_85; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_86; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_87; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_88; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_89; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_90; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_91; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_92; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_93; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_94; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_95; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_96; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_97; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_98; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_99; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_100; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_101; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_102; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_103; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_104; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_105; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_106; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_107; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_108; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_109; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_110; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_111; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_112; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_113; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_114; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_115; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_116; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_117; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_118; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_119; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_120; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_121; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_122; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_123; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_124; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_125; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_126; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_127; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_128; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_129; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_130; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_131; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_132; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_133; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_134; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_135; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_136; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_137; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_138; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_139; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_140; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_141; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_142; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_143; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_144; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_145; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_146; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_147; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_148; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_149; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_150; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_151; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_152; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_153; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_154; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_155; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_156; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_157; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_158; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_159; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_160; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_161; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_162; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_163; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_164; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_165; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_166; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_167; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_168; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_169; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_170; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_171; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_172; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_173; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_174; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_175; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_176; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_177; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_178; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_179; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_180; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_181; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_182; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_183; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_184; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_185; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_186; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_187; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_188; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_189; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_190; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_191; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_192; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_193; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_194; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_195; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_196; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_197; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_198; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_199; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_200; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_201; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_202; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_203; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_204; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_205; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_206; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_207; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_208; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_209; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_210; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_211; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_212; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_213; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_214; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_215; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_216; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_217; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_218; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_219; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_220; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_221; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_222; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_223; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_224; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_225; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_226; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_227; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_228; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_229; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_230; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_231; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_232; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_233; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_234; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_235; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_236; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_237; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_238; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_239; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_240; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_241; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_242; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_243; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_244; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_245; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_246; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_247; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_248; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_249; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_250; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_251; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_252; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_253; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_254; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg ghv_255; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 - reg s0_ghist_ptr_reg_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg [7:0] s0_ghist_ptr_reg_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg s0_ghist_ptr_reg_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg [7:0] s0_ghist_ptr_reg_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg s0_ghist_ptr_reg_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg [7:0] s0_ghist_ptr_reg_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg s0_ghist_ptr_reg_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg [7:0] s0_ghist_ptr_reg_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - reg s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg [7:0] s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg [7:0] s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg [7:0] s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg [7:0] s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 - reg s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg [7:0] s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg [7:0] s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg [7:0] s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg [7:0] s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 - reg s3_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg [7:0] s3_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg s3_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg [7:0] s3_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg [7:0] s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg s3_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg [7:0] s3_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 - reg do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [38:0] do_redirect_dup_3_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [3:0] do_redirect_dup_3_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [1:0] do_redirect_dup_3_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [4:0] do_redirect_dup_3_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [3:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [2:0] do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [7:0] do_redirect_dup_3_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [38:0] do_redirect_dup_3_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg [1:0] thisBrNumOH_dup_shiftAmount; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - reg do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - wire s2_flush_dup_3 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 + wire s3_redirect_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28] + wire s3_redirect_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28] + wire s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28] + wire s2_redirect_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28] + wire s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28] + wire s1_fire_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + wire s1_fire_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + wire s1_fire_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + wire s1_fire_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + wire _ghv_write_datas_255_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_254_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_253_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_252_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_251_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_250_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_249_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_248_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_247_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_246_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_245_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_244_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_243_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_242_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_241_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_240_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_239_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_238_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_237_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_236_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_235_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_234_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_233_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_232_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_231_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_230_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_229_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_228_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_227_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_226_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_225_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_224_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_223_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_222_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_221_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_220_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_219_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_218_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_217_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_216_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_215_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_214_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_213_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_212_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_211_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_210_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_209_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_208_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_207_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_206_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_205_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_204_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_203_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_202_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_201_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_200_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_199_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_198_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_197_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_196_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_195_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_194_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_193_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_192_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_191_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_190_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_189_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_188_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_187_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_186_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_185_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_184_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_183_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_182_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_181_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_180_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_179_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_178_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_177_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_176_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_175_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_174_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_173_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_172_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_171_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_170_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_169_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_168_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_167_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_166_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_165_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_164_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_163_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_162_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_161_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_160_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_159_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_158_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_157_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_156_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_155_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_154_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_153_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_152_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_151_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_150_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_149_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_148_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_147_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_146_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_145_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_144_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_143_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_142_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_141_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_140_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_139_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_138_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_137_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_136_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_135_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_134_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_133_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_132_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_131_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_130_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_129_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_128_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_127_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_126_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_125_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_124_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_123_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_122_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_121_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_120_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_119_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_118_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_117_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_116_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_115_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_114_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_113_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_112_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_111_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_110_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_109_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_108_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_107_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_106_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_105_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_104_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_103_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_102_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_101_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_100_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_99_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_98_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_97_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_96_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_95_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_94_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_93_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_92_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_91_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_90_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_89_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_88_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_87_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_86_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_85_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_84_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_83_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_82_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_81_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_80_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_79_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_78_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_77_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_76_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_75_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_74_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_73_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_72_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_71_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_70_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_69_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_68_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_67_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_66_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_65_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_64_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_63_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_62_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_61_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_60_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_59_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_58_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_57_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_56_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_55_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_54_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_53_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_52_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_51_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_50_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_49_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_48_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_47_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_46_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_45_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_44_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_43_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_42_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_41_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_40_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_39_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_38_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_37_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_36_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_35_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_34_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_33_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_32_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_31_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_30_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_29_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_28_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_27_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_26_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_25_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_24_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_23_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_22_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_21_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_20_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_19_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_18_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_17_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_16_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_15_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_14_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_13_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_12_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_11_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_10_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_9_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_8_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_7_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_6_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_5_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_4_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_3_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_2_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_1_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _ghv_write_datas_0_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [2:0] _s0_last_br_num_oh_dup_3_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [2:0] _s0_last_br_num_oh_dup_2_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [2:0] _s0_last_br_num_oh_dup_1_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ghist_ptr_dup_3_ppm_out_res_flag; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_ghist_ptr_dup_3_ppm_out_res_value; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ghist_ptr_dup_2_ppm_out_res_flag; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_ghist_ptr_dup_2_ppm_out_res_value; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ghist_ptr_dup_1_ppm_out_res_flag; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_ghist_ptr_dup_1_ppm_out_res_value; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire _s0_ghist_ptr_dup_0_ppm_out_res_flag; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_ghist_ptr_dup_0_ppm_out_res_value; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [3:0] _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [3:0] _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [3:0] _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [40:0] _s0_pc_dup_3_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [40:0] _s0_pc_dup_2_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [40:0] _s0_pc_dup_1_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [40:0] _s0_pc_dup_0_ppm_out_res; // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + wire [35:0] _reset_vector_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire [40:0] _predictors_io_out_s1_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s1_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [40:0] _predictors_io_out_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _predictors_io_s1_ready; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_4_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_5_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire [5:0] _predictors_io_perf_6_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] + wire _ctrl_delay_io_out_ubtb_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ctrl_delay_io_out_btb_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ctrl_delay_io_out_tage_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ctrl_delay_io_out_sc_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + wire _ctrl_delay_io_out_ras_enable; // @[utility/src/main/scala/utility/Hold.scala:100:23] + reg s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + reg s2_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + reg s3_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + reg [40:0] s0_pc_reg_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] + reg [40:0] s0_pc_reg_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] + reg [40:0] s0_pc_reg_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] + reg [40:0] s0_pc_reg_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] + reg REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:278:24] + reg REG_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:278:16] + reg [10:0] s0_folded_gh_reg_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [3:0] s0_folded_gh_reg_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [3:0] s0_folded_gh_reg_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [3:0] s0_folded_gh_reg_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [8:0] s0_folded_gh_reg_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [6:0] s0_folded_gh_reg_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s0_folded_gh_reg_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [7:0] s0_folded_gh_reg_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + reg [10:0] s1_folded_gh_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [3:0] s1_folded_gh_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [3:0] s1_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [3:0] s1_folded_gh_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [8:0] s1_folded_gh_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [6:0] s1_folded_gh_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s1_folded_gh_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [7:0] s1_folded_gh_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35] + reg [10:0] s2_folded_gh_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [3:0] s2_folded_gh_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [3:0] s2_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [3:0] s2_folded_gh_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [8:0] s2_folded_gh_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [6:0] s2_folded_gh_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s2_folded_gh_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [7:0] s2_folded_gh_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35] + reg [10:0] s3_folded_gh_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [3:0] s3_folded_gh_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [3:0] s3_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [3:0] s3_folded_gh_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [8:0] s3_folded_gh_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [6:0] s3_folded_gh_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [10:0] s3_folded_gh_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [7:0] s3_folded_gh_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:289:35] + reg [2:0] s0_last_br_num_oh_reg_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] + reg [2:0] s0_last_br_num_oh_reg_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] + reg [2:0] s0_last_br_num_oh_reg_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] + reg [2:0] s1_last_br_num_oh_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40] + reg [2:0] s1_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40] + reg [2:0] s1_last_br_num_oh_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40] + reg [2:0] s2_last_br_num_oh_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40] + reg [2:0] s2_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40] + reg [2:0] s2_last_br_num_oh_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40] + reg [2:0] s3_last_br_num_oh_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:295:40] + reg [2:0] s3_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:295:40] + reg [2:0] s3_last_br_num_oh_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:295:40] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:301:46] + reg ghv_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_4; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_5; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_6; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_7; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_8; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_9; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_10; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_11; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_12; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_13; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_15; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_16; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_17; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_18; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_19; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_20; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_21; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_22; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_23; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_24; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_25; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_26; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_27; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_28; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_29; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_30; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_31; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_32; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_33; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_34; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_35; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_36; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_37; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_38; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_39; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_40; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_41; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_42; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_43; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_44; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_45; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_46; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_47; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_48; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_49; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_50; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_51; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_52; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_53; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_54; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_55; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_56; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_57; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_58; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_59; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_60; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_61; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_62; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_63; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_64; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_65; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_66; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_67; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_68; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_69; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_70; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_71; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_72; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_73; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_74; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_75; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_76; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_77; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_78; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_79; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_80; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_81; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_82; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_83; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_84; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_85; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_86; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_87; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_88; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_89; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_90; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_91; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_92; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_93; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_94; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_95; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_96; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_97; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_98; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_99; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_100; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_101; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_102; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_103; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_104; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_105; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_106; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_107; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_108; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_109; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_110; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_111; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_112; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_113; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_114; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_115; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_116; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_117; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_118; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_119; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_120; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_121; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_122; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_123; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_124; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_125; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_126; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_127; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_128; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_129; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_130; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_131; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_132; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_133; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_134; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_135; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_136; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_137; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_138; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_139; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_140; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_141; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_142; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_143; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_144; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_145; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_146; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_147; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_148; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_149; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_150; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_151; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_152; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_153; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_154; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_155; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_156; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_157; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_158; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_159; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_160; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_161; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_162; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_163; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_164; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_165; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_166; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_167; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_168; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_169; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_170; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_171; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_172; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_173; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_174; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_175; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_176; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_177; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_178; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_179; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_180; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_181; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_182; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_183; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_184; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_185; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_186; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_187; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_188; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_189; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_190; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_191; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_192; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_193; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_194; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_195; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_196; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_197; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_198; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_199; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_200; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_201; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_202; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_203; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_204; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_205; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_206; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_207; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_208; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_209; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_210; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_211; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_212; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_213; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_214; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_215; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_216; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_217; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_218; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_219; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_220; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_221; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_222; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_223; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_224; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_225; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_226; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_227; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_228; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_229; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_230; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_231; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_232; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_233; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_234; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_235; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_236; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_237; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_238; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_239; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_240; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_241; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_242; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_243; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_244; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_245; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_246; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_247; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_248; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_249; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_250; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_251; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_252; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_253; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_254; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg ghv_255; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20] + reg s0_ghist_ptr_reg_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg [7:0] s0_ghist_ptr_reg_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg s0_ghist_ptr_reg_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg [7:0] s0_ghist_ptr_reg_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg s0_ghist_ptr_reg_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg [7:0] s0_ghist_ptr_reg_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg s0_ghist_ptr_reg_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg [7:0] s0_ghist_ptr_reg_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + reg s1_ghist_ptr_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg [7:0] s1_ghist_ptr_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg s1_ghist_ptr_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg [7:0] s1_ghist_ptr_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg s1_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg [7:0] s1_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg s1_ghist_ptr_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg [7:0] s1_ghist_ptr_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35] + reg s2_ghist_ptr_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg [7:0] s2_ghist_ptr_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg s2_ghist_ptr_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg [7:0] s2_ghist_ptr_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg s2_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg [7:0] s2_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg s2_ghist_ptr_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg [7:0] s2_ghist_ptr_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35] + reg s3_ghist_ptr_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg [7:0] s3_ghist_ptr_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg s3_ghist_ptr_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg [7:0] s3_ghist_ptr_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg s3_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg [7:0] s3_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg s3_ghist_ptr_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg [7:0] s3_ghist_ptr_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35] + reg do_redirect_dup_next_valid_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + reg do_redirect_dup_next_bits_r_level; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [40:0] do_redirect_dup_next_bits_r_cfiUpdate_pc; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [3:0] do_redirect_dup_next_bits_r_cfiUpdate_ssp; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [1:0] do_redirect_dup_next_bits_r_cfiUpdate_sctr; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_NOS_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [3:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [2:0] do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [40:0] do_redirect_dup_next_bits_r_cfiUpdate_target; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_taken; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg [1:0] do_redirect_dup_next_bits_r_cfiUpdate_shift; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + reg do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + wire s2_flush_dup_3 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :685:28] wire s0_fire_dup_0 = - _predictors_io_s1_ready & (s1_fire_dup_0 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + _predictors_io_s1_ready & (s1_fire_dup_0 | ~s1_valid_dup_3); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :366:{25,28}, :368:36, :375:60] wire s0_fire_dup_1 = - _predictors_io_s1_ready & (s1_fire_dup_1 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + _predictors_io_s1_ready & (s1_fire_dup_1 | ~s1_valid_dup_3); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :366:{25,28}, :368:36, :375:60] wire s0_fire_dup_2 = - _predictors_io_s1_ready & (s1_fire_dup_2 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + _predictors_io_s1_ready & (s1_fire_dup_2 | ~s1_valid_dup_3); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :366:{25,28}, :368:36, :375:60] wire s0_fire_dup_3 = - _predictors_io_s1_ready & (s1_fire_dup_3 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 - assign s1_fire_dup_0 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 - assign s1_fire_dup_1 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 - assign s1_fire_dup_2 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 - assign s1_fire_dup_3 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 - wire [8:0] _GEN = {s1_ghist_ptr_dup_0_flag, s1_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = - 9'(_GEN - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = - 9'(_GEN + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = - 9'(_GEN + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_0 = {s1_ghist_ptr_dup_1_flag, s1_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = - 9'(_GEN_0 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = - 9'(_GEN_0 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = - 9'(_GEN_0 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_1 = {s1_ghist_ptr_dup_2_flag, s1_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = - 9'(_GEN_1 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = - 9'(_GEN_1 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = - 9'(_GEN_1 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_2 = {s1_ghist_ptr_dup_3_flag, s1_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = - 9'(_GEN_2 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = - 9'(_GEN_2 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = - 9'(_GEN_2 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire _s1_ghv_wdatas_WIRE_44494_1 = + _predictors_io_s1_ready & (s1_fire_dup_3 | ~s1_valid_dup_3); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :366:{25,28}, :368:36, :375:60] + assign s1_fire_dup_0 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :375:60] + assign s1_fire_dup_1 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :375:60] + assign s1_fire_dup_2 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :375:60] + assign s1_fire_dup_3 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :375:60] + wire [8:0] _GEN = {s1_ghist_ptr_dup_0_flag, s1_ghist_ptr_dup_0_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_0 = {s1_ghist_ptr_dup_1_flag, s1_ghist_ptr_dup_1_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_0 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_0 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_0 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_1 = {s1_ghist_ptr_dup_2_flag, s1_ghist_ptr_dup_2_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_1 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_1 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_1 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_2 = {s1_ghist_ptr_dup_3_flag, s1_ghist_ptr_dup_3_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_2 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_2 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_2 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire _s1_ghv_wdatas_T_190528 = _predictors_io_out_s1_full_pred_0_slot_valids_1 - & _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_0 = + & _predictors_io_out_s1_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s1_predicted_ghist_ptr_dup_T_4 = ~_predictors_io_out_s1_full_pred_0_hit - | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _cfiIndex_bits_WIRE_18_0 = + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_T_190528); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire s1_pred_info_takenMask_0_0 = _predictors_io_out_s1_full_pred_0_slot_valids_0 - & _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_94 = _predictors_io_out_s1_full_pred_0_is_br_sharing - & _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_1 = + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s1_predicted_ghist_ptr_dup_T_32 = _predictors_io_out_s1_full_pred_0_slot_valids_0 - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_2 = - _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_predicted_fh_dup_WIRE_21_1 = + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_ghist_ptr_dup_T_60 = + _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_ghv_wdatas_T_190589 = _predictors_io_out_s1_full_pred_1_slot_valids_1 - & _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_0 = + & _predictors_io_out_s1_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s1_predicted_ghist_ptr_dup_T_65 = ~_predictors_io_out_s1_full_pred_1_hit - | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _cfiIndex_bits_WIRE_22_0 = + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire s1_pred_info_takenMask_1_0 = _predictors_io_out_s1_full_pred_1_slot_valids_0 - & _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_115 = _predictors_io_out_s1_full_pred_1_is_br_sharing - & _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_1 = + & _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s1_predicted_ghist_ptr_dup_T_93 = _predictors_io_out_s1_full_pred_1_slot_valids_0 - & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit - | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_2 = - _s1_predicted_fh_dup_WIRE_21_1 - & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_predicted_fh_dup_WIRE_35_1 = + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_ghist_ptr_dup_T_121 = + _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_ghv_wdatas_T_190650 = _predictors_io_out_s1_full_pred_2_slot_valids_1 - & _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_0 = + & _predictors_io_out_s1_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s1_predicted_ghist_ptr_dup_T_126 = ~_predictors_io_out_s1_full_pred_2_hit - | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _cfiIndex_bits_WIRE_26_0 = + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire s1_pred_info_takenMask_2_0 = _predictors_io_out_s1_full_pred_2_slot_valids_0 - & _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_136 = _predictors_io_out_s1_full_pred_2_is_br_sharing - & _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_1 = + & _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s1_predicted_ghist_ptr_dup_T_154 = _predictors_io_out_s1_full_pred_2_slot_valids_0 - & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit - | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_2 = - _s1_predicted_fh_dup_WIRE_35_1 - & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_predicted_fh_dup_WIRE_49_1 = + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_ghist_ptr_dup_T_182 = + _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_ghv_wdatas_T_190711 = _predictors_io_out_s1_full_pred_3_slot_valids_1 - & _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_0 = + & _predictors_io_out_s1_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s1_predicted_ghist_ptr_dup_T_187 = ~_predictors_io_out_s1_full_pred_3_hit - | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _cfiIndex_bits_WIRE_30_0 = + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire s1_pred_info_takenMask_3_0 = _predictors_io_out_s1_full_pred_3_slot_valids_0 - & _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_157 = _predictors_io_out_s1_full_pred_3_is_br_sharing - & _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_1 = + & _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s1_predicted_ghist_ptr_dup_T_215 = _predictors_io_out_s1_full_pred_3_slot_valids_0 - & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit - | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_2 = - _s1_predicted_fh_dup_WIRE_49_1 - & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_possible_predicted_fhs_dup_WIRE_4_1 = + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_ghist_ptr_dup_T_243 = + _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_possible_predicted_fhs_dup_T_11 = _predictors_io_out_s1_full_pred_1_slot_valids_0 & _predictors_io_out_s1_full_pred_1_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_1_hit | _s1_predicted_fh_dup_WIRE_21_1 + & _predictors_io_out_s1_full_pred_1_hit | _s1_ghv_wdatas_T_190589 & _predictors_io_out_s1_full_pred_1_br_taken_mask_1 - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} - wire _s1_possible_predicted_fhs_dup_WIRE_4_2 = + & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :494:{74,90}] + wire _s1_possible_predicted_fhs_dup_T_17 = _predictors_io_out_s1_full_pred_2_slot_valids_0 & _predictors_io_out_s1_full_pred_2_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_2_hit | _s1_predicted_fh_dup_WIRE_35_1 + & _predictors_io_out_s1_full_pred_2_hit | _s1_ghv_wdatas_T_190650 & _predictors_io_out_s1_full_pred_2_br_taken_mask_1 - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} - wire _s1_possible_predicted_fhs_dup_WIRE_4_3 = + & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :494:{74,90}] + wire _s1_possible_predicted_fhs_dup_T_23 = _predictors_io_out_s1_full_pred_3_slot_valids_0 & _predictors_io_out_s1_full_pred_3_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_3_hit | _s1_predicted_fh_dup_WIRE_49_1 + & _predictors_io_out_s1_full_pred_3_hit | _s1_ghv_wdatas_T_190711 & _predictors_io_out_s1_full_pred_3_br_taken_mask_1 - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} + & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :494:{74,90}] wire _s1_possible_predicted_fhs_dup_T_271 = - _s1_possible_predicted_fhs_dup_WIRE_4_1 + _s1_possible_predicted_fhs_dup_T_11 & (~_predictors_io_out_s1_full_pred_1_hit - | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 - | _s1_predicted_fh_dup_WIRE_21_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589)); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 - = - _s1_possible_predicted_fhs_dup_WIRE_4_1 - & _predictors_io_out_s1_full_pred_1_slot_valids_0 - & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit - | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 = + _s1_possible_predicted_fhs_dup_T_11 & _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 - = - _s1_possible_predicted_fhs_dup_WIRE_4_1 & _s1_predicted_fh_dup_WIRE_21_1 - & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 = + _s1_possible_predicted_fhs_dup_T_11 & _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :494:90] wire _s1_possible_predicted_fhs_dup_T_274 = - _s1_possible_predicted_fhs_dup_WIRE_4_2 + _s1_possible_predicted_fhs_dup_T_17 & (~_predictors_io_out_s1_full_pred_2_hit - | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 - | _s1_predicted_fh_dup_WIRE_35_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650)); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 - = - _s1_possible_predicted_fhs_dup_WIRE_4_2 - & _predictors_io_out_s1_full_pred_2_slot_valids_0 - & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit - | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 = + _s1_possible_predicted_fhs_dup_T_17 & _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 - = - _s1_possible_predicted_fhs_dup_WIRE_4_2 & _s1_predicted_fh_dup_WIRE_35_1 - & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 = + _s1_possible_predicted_fhs_dup_T_17 & _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :494:90] wire _s1_possible_predicted_fhs_dup_T_277 = - _s1_possible_predicted_fhs_dup_WIRE_4_3 + _s1_possible_predicted_fhs_dup_T_23 & (~_predictors_io_out_s1_full_pred_3_hit - | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 - | _s1_predicted_fh_dup_WIRE_49_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711)); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 - = - _s1_possible_predicted_fhs_dup_WIRE_4_3 - & _predictors_io_out_s1_full_pred_3_slot_valids_0 - & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit - | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 = + _s1_possible_predicted_fhs_dup_T_23 & _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37}, :494:90] wire - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - = - _s1_possible_predicted_fhs_dup_WIRE_4_3 & _s1_predicted_fh_dup_WIRE_49_1 - & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 - wire _s1_predicted_fh_dup_WIRE_56_1_0 = + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 = + _s1_possible_predicted_fhs_dup_T_23 & _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :494:90] + wire _s1_predicted_fh_dup_T_65 = ~_predictors_io_out_s1_full_pred_1_hit - | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s1_predicted_fh_dup_WIRE_56_1_1 = + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s1_predicted_fh_dup_T_93 = _predictors_io_out_s1_full_pred_1_slot_valids_0 - & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit - | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_fh_dup_WIRE_56_1_2 = - _s1_predicted_fh_dup_WIRE_21_1 - & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_predicted_fh_dup_WIRE_56_2_0 = + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_fh_dup_T_121 = + _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_predicted_fh_dup_T_126 = ~_predictors_io_out_s1_full_pred_2_hit - | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s1_predicted_fh_dup_WIRE_56_2_1 = + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s1_predicted_fh_dup_T_154 = _predictors_io_out_s1_full_pred_2_slot_valids_0 - & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit - | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_fh_dup_WIRE_56_2_2 = - _s1_predicted_fh_dup_WIRE_35_1 - & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s1_predicted_fh_dup_WIRE_56_3_0 = + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_fh_dup_T_182 = + _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s1_predicted_fh_dup_T_187 = ~_predictors_io_out_s1_full_pred_3_hit - | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s1_predicted_fh_dup_WIRE_56_3_1 = + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s1_predicted_fh_dup_T_215 = _predictors_io_out_s1_full_pred_3_slot_valids_0 - & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit - | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s1_predicted_fh_dup_WIRE_56_3_2 = - _s1_predicted_fh_dup_WIRE_49_1 - & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s1_predicted_fh_dup_T_243 = + _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] wire [255:0] _GEN_3 = {{ghv_255}, {ghv_254}, @@ -2206,1580 +2208,1580 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 {ghv_3}, {ghv_2}, {ghv_1}, - {ghv_0}}; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + {ghv_0}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = - _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = - _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = - _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = - _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = - _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = - _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = - _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s1_pred_info_takenMask_0_1 = _predictors_io_out_s1_full_pred_0_slot_valids_1 - & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _GEN_4 = + & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _GEN_4 = _predictors_io_out_s1_full_pred_0_hit - ? 39'h0 - : 39'(_predictors_io_out_s1_pc_0 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_0 + 41'h20); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] wire s1_pred_info_takenMask_1_1 = _predictors_io_out_s1_full_pred_1_slot_valids_1 - & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _GEN_5 = + & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _GEN_5 = _predictors_io_out_s1_full_pred_1_hit - ? 39'h0 - : 39'(_predictors_io_out_s1_pc_1 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_1 + 41'h20); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] wire s1_pred_info_takenMask_2_1 = _predictors_io_out_s1_full_pred_2_slot_valids_1 - & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _GEN_6 = + & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _GEN_6 = _predictors_io_out_s1_full_pred_2_hit - ? 39'h0 - : 39'(_predictors_io_out_s1_pc_2 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_2 + 41'h20); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] wire s1_pred_info_takenMask_3_1 = _predictors_io_out_s1_full_pred_3_slot_valids_1 - & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _GEN_7 = + & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _GEN_7 = _predictors_io_out_s1_full_pred_3_hit - ? 39'h0 - : 39'(_predictors_io_out_s1_pc_3 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_3 + 41'h20); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] wire _GEN_8 = - _predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + _predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:41] wire _GEN_9 = - _cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_10 = _GEN_9 | ~_s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_10 = _GEN_9 | ~_s1_ghv_wdatas_T_190589; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :489:{34,37}] wire _GEN_11 = - _predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + _predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:41] wire _GEN_12 = - _cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_13 = _GEN_12 | ~_s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_13 = _GEN_12 | ~_s1_ghv_wdatas_T_190650; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :489:{34,37}] wire _GEN_14 = - _predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + _predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:41] wire _GEN_15 = - _cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_16 = _GEN_15 | ~_s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_16 = _GEN_15 | ~_s1_ghv_wdatas_T_190711; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :489:{34,37}] wire _ghv_wens_0_T = ~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_1_T = s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_2_T = s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_3_T = s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_4_T = s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_5_T = s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_6_T = s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_7_T = s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_8_T = s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_9_T = s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_10_T = s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_11_T = s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_12_T = s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_13_T = s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_14_T = s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_15_T = s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_16_T = s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_17_T = s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_18_T = s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_19_T = s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_20_T = s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_21_T = s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_22_T = s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_23_T = s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_24_T = s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_25_T = s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_26_T = s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_27_T = s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_28_T = s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_29_T = s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_30_T = s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_31_T = s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_32_T = s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_33_T = s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_34_T = s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_35_T = s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_36_T = s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_37_T = s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_38_T = s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_39_T = s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_40_T = s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_41_T = s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_42_T = s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_43_T = s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_44_T = s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_45_T = s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_46_T = s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_47_T = s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_48_T = s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_49_T = s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_50_T = s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_51_T = s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_52_T = s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_53_T = s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_54_T = s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_55_T = s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_56_T = s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_57_T = s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_58_T = s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_59_T = s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_60_T = s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_61_T = s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_62_T = s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_63_T = s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_64_T = s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_65_T = s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_66_T = s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_67_T = s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_68_T = s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_69_T = s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_70_T = s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_71_T = s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_72_T = s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_73_T = s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_74_T = s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_75_T = s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_76_T = s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_77_T = s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_78_T = s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_79_T = s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_80_T = s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_81_T = s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_82_T = s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_83_T = s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_84_T = s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_85_T = s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_86_T = s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_87_T = s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_88_T = s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_89_T = s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_90_T = s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_91_T = s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_92_T = s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_93_T = s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_94_T = s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_95_T = s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_96_T = s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_97_T = s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_98_T = s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_99_T = s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_100_T = s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_101_T = s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_102_T = s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_103_T = s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_104_T = s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_105_T = s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_106_T = s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_107_T = s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_108_T = s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_109_T = s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_110_T = s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_111_T = s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_112_T = s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_113_T = s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_114_T = s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_115_T = s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_116_T = s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_117_T = s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_118_T = s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_119_T = s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_120_T = s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_121_T = s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_122_T = s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_123_T = s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_124_T = s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_125_T = s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_126_T = s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_127_T = s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_128_T = s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_129_T = s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_130_T = s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_131_T = s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_132_T = s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_133_T = s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_134_T = s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_135_T = s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_136_T = s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_137_T = s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_138_T = s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_139_T = s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_140_T = s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_141_T = s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_142_T = s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_143_T = s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_144_T = s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_145_T = s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_146_T = s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_147_T = s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_148_T = s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_149_T = s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_150_T = s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_151_T = s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_152_T = s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_153_T = s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_154_T = s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_155_T = s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_156_T = s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_157_T = s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_158_T = s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_159_T = s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_160_T = s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_161_T = s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_162_T = s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_163_T = s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_164_T = s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_165_T = s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_166_T = s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_167_T = s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_168_T = s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_169_T = s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_170_T = s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_171_T = s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_172_T = s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_173_T = s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_174_T = s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_175_T = s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_176_T = s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_177_T = s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_178_T = s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_179_T = s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_180_T = s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_181_T = s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_182_T = s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_183_T = s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_184_T = s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_185_T = s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_186_T = s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_187_T = s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_188_T = s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_189_T = s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_190_T = s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_191_T = s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_192_T = s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_193_T = s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_194_T = s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_195_T = s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_196_T = s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_197_T = s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_198_T = s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_199_T = s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_200_T = s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_201_T = s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_202_T = s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_203_T = s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_204_T = s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_205_T = s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_206_T = s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_207_T = s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_208_T = s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_209_T = s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_210_T = s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_211_T = s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_212_T = s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_213_T = s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_214_T = s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_215_T = s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_216_T = s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_217_T = s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_218_T = s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_219_T = s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_220_T = s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_221_T = s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_222_T = s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_223_T = s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_224_T = s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_225_T = s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_226_T = s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_227_T = s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_228_T = s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_229_T = s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_230_T = s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_231_T = s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_232_T = s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_233_T = s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_234_T = s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_235_T = s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_236_T = s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_237_T = s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_238_T = s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_239_T = s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_240_T = s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_241_T = s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_242_T = s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_243_T = s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_244_T = s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_245_T = s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_246_T = s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_247_T = s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_248_T = s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_249_T = s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_250_T = s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_251_T = s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_252_T = s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_253_T = s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_254_T = s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s1_valid_dup_3 | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_255_T = (&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 - & s1_valid_dup_3 | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 - wire [8:0] _GEN_17 = {s2_ghist_ptr_dup_0_flag, s2_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = - 9'(_GEN_17 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = - 9'(_GEN_17 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = - 9'(_GEN_17 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_18 = {s2_ghist_ptr_dup_1_flag, s2_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = - 9'(_GEN_18 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = - 9'(_GEN_18 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = - 9'(_GEN_18 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_19 = {s2_ghist_ptr_dup_2_flag, s2_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = - 9'(_GEN_19 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = - 9'(_GEN_19 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = - 9'(_GEN_19 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_20 = {s2_ghist_ptr_dup_3_flag, s2_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = - 9'(_GEN_20 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = - 9'(_GEN_20 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = - 9'(_GEN_20 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 = + & s1_valid_dup_3 | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :324:35, :495:{58,129}, :517:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] + wire [8:0] _GEN_17 = {s2_ghist_ptr_dup_0_flag, s2_ghist_ptr_dup_0_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_17 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_17 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_17 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_18 = {s2_ghist_ptr_dup_1_flag, s2_ghist_ptr_dup_1_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_18 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_18 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_18 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_19 = {s2_ghist_ptr_dup_2_flag, s2_ghist_ptr_dup_2_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_19 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_19 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_19 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_20 = {s2_ghist_ptr_dup_3_flag, s2_ghist_ptr_dup_3_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_20 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_20 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_20 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 = _predictors_io_out_s2_full_pred_0_slot_valids_1 - & _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_0 = + & _predictors_io_out_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s2_predicted_ghist_ptr_dup_T_4 = ~_predictors_io_out_s2_full_pred_0_hit | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_66 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _cfiIndex_bits_T_261 = _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_262 = _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + & _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 = _predictors_io_out_s2_full_pred_0_br_taken_mask_1 - & _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_1 = + & _predictors_io_out_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:475:27] + wire _s2_predicted_ghist_ptr_dup_T_32 = _predictors_io_out_s2_full_pred_0_slot_valids_0 - & (_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1) - & _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) - & _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 = + & (_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56) + & _predictors_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_ghist_ptr_dup_T_60 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _predictors_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 = _predictors_io_out_s2_full_pred_1_slot_valids_1 - & _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_0 = + & _predictors_io_out_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s2_predicted_ghist_ptr_dup_T_65 = ~_predictors_io_out_s2_full_pred_1_hit | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_74 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _cfiIndex_bits_T_282 = _predictors_io_out_s2_full_pred_1_slot_valids_0 - & _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_283 = _predictors_io_out_s2_full_pred_1_is_br_sharing - & _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_1 = + & _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s2_predicted_ghist_ptr_dup_T_93 = _predictors_io_out_s2_full_pred_1_slot_valids_0 - & (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) - & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 - & ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit) - & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 = + & (_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_ghist_ptr_dup_T_121 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 = _predictors_io_out_s2_full_pred_2_slot_valids_1 - & _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_0 = + & _predictors_io_out_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s2_predicted_ghist_ptr_dup_T_126 = ~_predictors_io_out_s2_full_pred_2_hit | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_82 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _cfiIndex_bits_T_303 = _predictors_io_out_s2_full_pred_2_slot_valids_0 - & _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_304 = _predictors_io_out_s2_full_pred_2_is_br_sharing - & _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_1 = + & _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s2_predicted_ghist_ptr_dup_T_154 = _predictors_io_out_s2_full_pred_2_slot_valids_0 - & (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) - & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 - & ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit) - & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 = + & (_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_ghist_ptr_dup_T_182 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 = _predictors_io_out_s2_full_pred_3_slot_valids_1 - & _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_0 = + & _predictors_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s2_predicted_ghist_ptr_dup_T_187 = ~_predictors_io_out_s2_full_pred_3_hit | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_90 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _cfiIndex_bits_T_324 = _predictors_io_out_s2_full_pred_3_slot_valids_0 - & _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _cfiIndex_bits_T_325 = _predictors_io_out_s2_full_pred_3_is_br_sharing - & _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_1 = + & _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s2_predicted_ghist_ptr_dup_T_215 = _predictors_io_out_s2_full_pred_3_slot_valids_0 - & (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) - & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 - & ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit) - & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_predicted_fh_dup_WIRE_56_1_0 = + & (_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_ghist_ptr_dup_T_243 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_predicted_fh_dup_T_65 = ~_predictors_io_out_s2_full_pred_1_hit | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s2_predicted_fh_dup_WIRE_56_1_1 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s2_predicted_fh_dup_T_93 = _predictors_io_out_s2_full_pred_1_slot_valids_0 - & (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) - & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_fh_dup_WIRE_56_1_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 - & ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit) - & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_predicted_fh_dup_WIRE_56_2_0 = + & (_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_fh_dup_T_121 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_predicted_fh_dup_T_126 = ~_predictors_io_out_s2_full_pred_2_hit | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s2_predicted_fh_dup_WIRE_56_2_1 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s2_predicted_fh_dup_T_154 = _predictors_io_out_s2_full_pred_2_slot_valids_0 - & (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) - & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_fh_dup_WIRE_56_2_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 - & ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit) - & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s2_predicted_fh_dup_WIRE_56_3_0 = + & (_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_fh_dup_T_182 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s2_predicted_fh_dup_T_187 = ~_predictors_io_out_s2_full_pred_3_hit | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s2_predicted_fh_dup_WIRE_56_3_1 = + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s2_predicted_fh_dup_T_215 = _predictors_io_out_s2_full_pred_3_slot_valids_0 - & (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) - & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s2_predicted_fh_dup_WIRE_56_3_2 = - _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 - & ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit) - & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + & (_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s2_predicted_fh_dup_T_243 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = - _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = - _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = - _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = - _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = - _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = - _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = - _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - reg previous_s1_pred_info_hit_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_hit_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_hit_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_hit_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [38:0] previous_s1_pred_info_target_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [38:0] previous_s1_pred_info_target_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [38:0] previous_s1_pred_info_target_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [38:0] previous_s1_pred_info_target_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_0_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_1_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_2_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_lastBrPosOH_3_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_taken_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_taken_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg previous_s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [3:0] previous_s1_pred_info_cfiIndex_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [3:0] previous_s1_pred_info_cfiIndex_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [3:0] previous_s1_pred_info_cfiIndex_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - reg [3:0] previous_s1_pred_info_cfiIndex_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 - wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 = - 39'(_predictors_io_out_s2_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 = - 39'(_predictors_io_out_s2_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 = - 39'(_predictors_io_out_s2_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 = - 39'(_predictors_io_out_s2_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + reg previous_s1_pred_info_hit_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_hit_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_hit_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_hit_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [40:0] previous_s1_pred_info_target_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [40:0] previous_s1_pred_info_target_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [40:0] previous_s1_pred_info_target_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [40:0] previous_s1_pred_info_target_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_0_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_0_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_0_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_1_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_1_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_1_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_2_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_2_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_2_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_3_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_3_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_lastBrPosOH_3_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_taken_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_taken_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_taken_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_taken_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_0_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_0_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_1_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_1_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_2_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_2_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_3_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg previous_s1_pred_info_takenMask_3_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [3:0] previous_s1_pred_info_cfiIndex_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [3:0] previous_s1_pred_info_cfiIndex_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [3:0] previous_s1_pred_info_cfiIndex_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + reg [3:0] previous_s1_pred_info_cfiIndex_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40] + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T = + 41'(_predictors_io_out_s2_pc_0 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2 = + 41'(_predictors_io_out_s2_pc_1 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4 = + 41'(_predictors_io_out_s2_pc_2 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6 = + 41'(_predictors_io_out_s2_pc_3 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] assign s2_redirect_dup_0 = s2_valid_dup_3 & (previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_hit_0 @@ -3791,33 +3793,33 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 previous_s1_pred_info_takenMask_0_0} == 2'h0 & previous_s1_pred_info_hit_0 & _predictors_io_out_s2_full_pred_0_fallThroughAddr != previous_s1_pred_info_target_0 | ~previous_s1_pred_info_hit_0 - & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 != previous_s1_pred_info_target_0 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T != previous_s1_pred_info_target_0 | {previous_s1_pred_info_lastBrPosOH_0_2, previous_s1_pred_info_lastBrPosOH_0_1, - previous_s1_pred_info_lastBrPosOH_0_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 + previous_s1_pred_info_lastBrPosOH_0_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _predictors_io_out_s2_full_pred_0_hit, _predictors_io_out_s2_full_pred_0_slot_valids_0 - & (_selVecOH_T_66 + & (_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1) + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56) & _predictors_io_out_s2_full_pred_0_hit, ~_predictors_io_out_s2_full_pred_0_hit | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1)} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56)} | previous_s1_pred_info_taken_0 != (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) & _predictors_io_out_s2_full_pred_0_hit, - _selVecOH_T_66 + _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit}) | previous_s1_pred_info_taken_0 & (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) & _predictors_io_out_s2_full_pred_0_hit, - _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit}) - & previous_s1_pred_info_cfiIndex_0 != ((_selVecOH_T_66 + _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit}) + & previous_s1_pred_info_cfiIndex_0 != ((_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit ? _predictors_io_out_s2_full_pred_0_offsets_0 : _predictors_io_out_s2_full_pred_0_offsets_1) @@ -3825,8 +3827,8 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) & _predictors_io_out_s2_full_pred_0_hit, - _selVecOH_T_66 - & _predictors_io_out_s2_full_pred_0_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + _cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit} == 2'h0}})); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :536:64, :543:{112,119,127}, :544:97, :545:{147,153}, :601:40, :606:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:51, :422:{21,28,43}, :454:48, :459:69, :461:{25,47,50}, :468:38, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}, :506:47, :520:{46,53}, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] wire s2_redirect_dup_1 = s2_valid_dup_3 & (previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_hit_1 @@ -3838,33 +3840,33 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 previous_s1_pred_info_takenMask_1_0} == 2'h0 & previous_s1_pred_info_hit_1 & _predictors_io_out_s2_full_pred_1_fallThroughAddr != previous_s1_pred_info_target_1 | ~previous_s1_pred_info_hit_1 - & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 != previous_s1_pred_info_target_1 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2 != previous_s1_pred_info_target_1 | {previous_s1_pred_info_lastBrPosOH_1_2, previous_s1_pred_info_lastBrPosOH_1_1, - previous_s1_pred_info_lastBrPosOH_1_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 - & ~(_selVecOH_T_74 + previous_s1_pred_info_lastBrPosOH_1_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit) & _predictors_io_out_s2_full_pred_1_hit, _predictors_io_out_s2_full_pred_1_slot_valids_0 - & (_selVecOH_T_74 + & (_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) & _predictors_io_out_s2_full_pred_1_hit, ~_predictors_io_out_s2_full_pred_1_hit | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117)} | previous_s1_pred_info_taken_1 != (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) & _predictors_io_out_s2_full_pred_1_hit, - _selVecOH_T_74 + _cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit}) | previous_s1_pred_info_taken_1 & (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) & _predictors_io_out_s2_full_pred_1_hit, - _selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit}) - & previous_s1_pred_info_cfiIndex_1 != ((_selVecOH_T_74 + _cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit}) + & previous_s1_pred_info_cfiIndex_1 != ((_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit ? _predictors_io_out_s2_full_pred_1_offsets_0 : _predictors_io_out_s2_full_pred_1_offsets_1) @@ -3872,8 +3874,8 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) & _predictors_io_out_s2_full_pred_1_hit, - _selVecOH_T_74 - & _predictors_io_out_s2_full_pred_1_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + _cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit} == 2'h0}})); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :536:64, :543:{112,119,127}, :544:97, :545:{147,153}, :601:40, :606:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:51, :422:{21,28,43}, :454:48, :459:69, :461:{25,47,50}, :468:38, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}, :506:47, :520:{46,53}, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] assign s2_redirect_dup_2 = s2_valid_dup_3 & (previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_hit_2 @@ -3885,33 +3887,33 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 previous_s1_pred_info_takenMask_2_0} == 2'h0 & previous_s1_pred_info_hit_2 & _predictors_io_out_s2_full_pred_2_fallThroughAddr != previous_s1_pred_info_target_2 | ~previous_s1_pred_info_hit_2 - & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 != previous_s1_pred_info_target_2 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4 != previous_s1_pred_info_target_2 | {previous_s1_pred_info_lastBrPosOH_2_2, previous_s1_pred_info_lastBrPosOH_2_1, - previous_s1_pred_info_lastBrPosOH_2_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 - & ~(_selVecOH_T_82 + previous_s1_pred_info_lastBrPosOH_2_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit) & _predictors_io_out_s2_full_pred_2_hit, _predictors_io_out_s2_full_pred_2_slot_valids_0 - & (_selVecOH_T_82 + & (_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) & _predictors_io_out_s2_full_pred_2_hit, ~_predictors_io_out_s2_full_pred_2_hit | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178)} | previous_s1_pred_info_taken_2 != (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) & _predictors_io_out_s2_full_pred_2_hit, - _selVecOH_T_82 + _cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit}) | previous_s1_pred_info_taken_2 & (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) & _predictors_io_out_s2_full_pred_2_hit, - _selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit}) - & previous_s1_pred_info_cfiIndex_2 != ((_selVecOH_T_82 + _cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit}) + & previous_s1_pred_info_cfiIndex_2 != ((_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit ? _predictors_io_out_s2_full_pred_2_offsets_0 : _predictors_io_out_s2_full_pred_2_offsets_1) @@ -3919,8 +3921,8 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) & _predictors_io_out_s2_full_pred_2_hit, - _selVecOH_T_82 - & _predictors_io_out_s2_full_pred_2_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + _cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit} == 2'h0}})); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :536:64, :543:{112,119,127}, :544:97, :545:{147,153}, :601:40, :606:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:51, :422:{21,28,43}, :454:48, :459:69, :461:{25,47,50}, :468:38, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}, :506:47, :520:{46,53}, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] wire s2_redirect_dup_3 = s2_valid_dup_3 & (previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_hit_3 @@ -3932,33 +3934,33 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 previous_s1_pred_info_takenMask_3_0} == 2'h0 & previous_s1_pred_info_hit_3 & _predictors_io_out_s2_full_pred_3_fallThroughAddr != previous_s1_pred_info_target_3 | ~previous_s1_pred_info_hit_3 - & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 != previous_s1_pred_info_target_3 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6 != previous_s1_pred_info_target_3 | {previous_s1_pred_info_lastBrPosOH_3_2, previous_s1_pred_info_lastBrPosOH_3_1, - previous_s1_pred_info_lastBrPosOH_3_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 - & ~(_selVecOH_T_90 + previous_s1_pred_info_lastBrPosOH_3_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit) & _predictors_io_out_s2_full_pred_3_hit, _predictors_io_out_s2_full_pred_3_slot_valids_0 - & (_selVecOH_T_90 + & (_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit - | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) & _predictors_io_out_s2_full_pred_3_hit, ~_predictors_io_out_s2_full_pred_3_hit | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239)} | previous_s1_pred_info_taken_3 != (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) & _predictors_io_out_s2_full_pred_3_hit, - _selVecOH_T_90 + _cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit}) | previous_s1_pred_info_taken_3 & (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) & _predictors_io_out_s2_full_pred_3_hit, - _selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit}) - & previous_s1_pred_info_cfiIndex_3 != ((_selVecOH_T_90 + _cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit}) + & previous_s1_pred_info_cfiIndex_3 != ((_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit ? _predictors_io_out_s2_full_pred_3_offsets_0 : _predictors_io_out_s2_full_pred_3_offsets_1) @@ -3966,6369 +3968,6837 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) & _predictors_io_out_s2_full_pred_3_hit, - _selVecOH_T_90 - & _predictors_io_out_s2_full_pred_3_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + _cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit} == 2'h0}})); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :536:64, :543:{112,119,127}, :544:97, :545:{147,153}, :601:40, :606:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:51, :422:{21,28,43}, :454:48, :459:69, :461:{25,47,50}, :468:38, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}, :506:47, :520:{46,53}, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] wire _GEN_21 = _predictors_io_out_s2_full_pred_0_slot_valids_1 - & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_22 = _predictors_io_out_s2_full_pred_1_slot_valids_1 - & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_23 = _predictors_io_out_s2_full_pred_2_slot_valids_1 - & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_24 = _predictors_io_out_s2_full_pred_3_slot_valids_1 - & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire _GEN_25 = _selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_26 = _selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_27 = _selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire _GEN_25 = _cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_26 = _cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_27 = _cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] wire _ghv_wens_0_T_1 = ~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_1_T_1 = s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_2_T_1 = s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_3_T_1 = s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_4_T_1 = s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_5_T_1 = s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_6_T_1 = s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_7_T_1 = s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_8_T_1 = s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_9_T_1 = s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_10_T_1 = s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_11_T_1 = s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_12_T_1 = s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_13_T_1 = s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_14_T_1 = s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_15_T_1 = s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h10 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_16_T_1 = s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h11 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_17_T_1 = s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h12 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_18_T_1 = s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h13 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_19_T_1 = s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h14 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_20_T_1 = s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h15 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_21_T_1 = s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h16 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_22_T_1 = s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h17 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_23_T_1 = s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h18 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_24_T_1 = s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h19 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_25_T_1 = s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_26_T_1 = s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_27_T_1 = s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_28_T_1 = s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_29_T_1 = s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_30_T_1 = s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_31_T_1 = s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h20 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_32_T_1 = s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h21 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_33_T_1 = s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h22 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_34_T_1 = s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h23 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_35_T_1 = s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h24 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_36_T_1 = s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h25 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_37_T_1 = s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h26 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_38_T_1 = s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h27 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_39_T_1 = s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h28 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_40_T_1 = s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h29 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_41_T_1 = s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_42_T_1 = s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_43_T_1 = s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_44_T_1 = s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_45_T_1 = s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_46_T_1 = s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_47_T_1 = s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h30 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_48_T_1 = s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h31 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_49_T_1 = s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h32 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_50_T_1 = s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h33 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_51_T_1 = s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h34 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_52_T_1 = s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h35 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_53_T_1 = s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h36 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_54_T_1 = s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h37 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_55_T_1 = s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h38 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_56_T_1 = s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h39 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_57_T_1 = s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_58_T_1 = s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_59_T_1 = s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_60_T_1 = s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_61_T_1 = s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_62_T_1 = s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_63_T_1 = s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h40 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_64_T_1 = s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h41 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_65_T_1 = s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h42 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_66_T_1 = s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h43 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_67_T_1 = s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h44 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_68_T_1 = s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h45 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_69_T_1 = s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h46 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_70_T_1 = s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h47 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_71_T_1 = s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h48 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_72_T_1 = s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h49 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_73_T_1 = s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_74_T_1 = s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_75_T_1 = s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_76_T_1 = s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_77_T_1 = s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_78_T_1 = s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_79_T_1 = s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h50 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_80_T_1 = s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h51 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_81_T_1 = s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h52 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_82_T_1 = s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h53 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_83_T_1 = s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h54 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_84_T_1 = s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h55 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_85_T_1 = s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h56 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_86_T_1 = s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h57 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_87_T_1 = s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h58 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_88_T_1 = s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h59 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_89_T_1 = s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_90_T_1 = s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_91_T_1 = s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_92_T_1 = s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_93_T_1 = s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_94_T_1 = s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_95_T_1 = s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h60 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_96_T_1 = s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h61 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_97_T_1 = s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h62 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_98_T_1 = s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h63 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_99_T_1 = s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h64 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_100_T_1 = s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h65 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_101_T_1 = s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h66 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_102_T_1 = s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h67 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_103_T_1 = s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h68 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_104_T_1 = s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h69 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_105_T_1 = s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_106_T_1 = s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_107_T_1 = s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_108_T_1 = s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_109_T_1 = s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_110_T_1 = s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_111_T_1 = s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h70 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_112_T_1 = s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h71 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_113_T_1 = s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h72 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_114_T_1 = s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h73 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_115_T_1 = s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h74 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_116_T_1 = s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h75 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_117_T_1 = s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h76 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_118_T_1 = s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h77 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_119_T_1 = s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h78 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_120_T_1 = s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h79 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_121_T_1 = s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_122_T_1 = s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_123_T_1 = s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_124_T_1 = s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_125_T_1 = s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_126_T_1 = s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_127_T_1 = s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h80 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_128_T_1 = s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h81 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_129_T_1 = s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h82 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_130_T_1 = s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h83 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_131_T_1 = s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h84 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_132_T_1 = s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h85 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_133_T_1 = s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h86 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_134_T_1 = s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h87 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_135_T_1 = s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h88 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_136_T_1 = s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h89 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_137_T_1 = s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_138_T_1 = s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_139_T_1 = s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_140_T_1 = s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_141_T_1 = s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_142_T_1 = s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_143_T_1 = s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h90 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_144_T_1 = s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h91 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_145_T_1 = s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h92 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_146_T_1 = s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h93 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_147_T_1 = s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h94 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_148_T_1 = s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h95 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_149_T_1 = s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h96 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_150_T_1 = s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h97 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_151_T_1 = s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h98 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_152_T_1 = s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h99 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_153_T_1 = s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_154_T_1 = s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_155_T_1 = s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_156_T_1 = s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_157_T_1 = s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_158_T_1 = s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_159_T_1 = s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_160_T_1 = s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_161_T_1 = s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_162_T_1 = s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_163_T_1 = s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_164_T_1 = s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_165_T_1 = s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_166_T_1 = s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_167_T_1 = s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_168_T_1 = s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_169_T_1 = s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_170_T_1 = s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_171_T_1 = s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_172_T_1 = s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_173_T_1 = s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_174_T_1 = s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_175_T_1 = s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_176_T_1 = s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_177_T_1 = s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_178_T_1 = s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_179_T_1 = s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_180_T_1 = s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_181_T_1 = s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_182_T_1 = s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_183_T_1 = s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_184_T_1 = s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_185_T_1 = s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_186_T_1 = s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_187_T_1 = s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_188_T_1 = s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_189_T_1 = s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_190_T_1 = s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_191_T_1 = s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_192_T_1 = s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_193_T_1 = s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_194_T_1 = s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_195_T_1 = s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_196_T_1 = s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_197_T_1 = s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_198_T_1 = s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_199_T_1 = s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_200_T_1 = s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_201_T_1 = s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_202_T_1 = s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_203_T_1 = s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_204_T_1 = s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_205_T_1 = s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_206_T_1 = s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_207_T_1 = s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_208_T_1 = s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_209_T_1 = s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_210_T_1 = s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_211_T_1 = s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_212_T_1 = s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_213_T_1 = s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_214_T_1 = s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_215_T_1 = s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_216_T_1 = s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_217_T_1 = s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_218_T_1 = s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_219_T_1 = s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_220_T_1 = s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_221_T_1 = s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_222_T_1 = s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_223_T_1 = s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_224_T_1 = s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_225_T_1 = s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_226_T_1 = s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_227_T_1 = s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_228_T_1 = s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_229_T_1 = s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_230_T_1 = s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_231_T_1 = s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_232_T_1 = s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_233_T_1 = s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_234_T_1 = s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_235_T_1 = s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_236_T_1 = s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hED - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_237_T_1 = s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_238_T_1 = s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_239_T_1 = s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_240_T_1 = s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_241_T_1 = s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_242_T_1 = s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_243_T_1 = s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_244_T_1 = s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_245_T_1 = s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_246_T_1 = s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_247_T_1 = s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_248_T_1 = s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_249_T_1 = s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_250_T_1 = s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_251_T_1 = s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_252_T_1 = s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_253_T_1 = s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_254_T_1 = s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | (&s2_ghist_ptr_dup_0_value) - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_255_T_1 = (&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 & s2_redirect_dup_0 | ~(|s2_ghist_ptr_dup_0_value) - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 - wire [8:0] _GEN_28 = {s3_ghist_ptr_dup_0_flag, s3_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = - 9'(_GEN_28 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = - 9'(_GEN_28 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = - 9'(_GEN_28 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_29 = {s3_ghist_ptr_dup_1_flag, s3_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = - 9'(_GEN_29 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = - 9'(_GEN_29 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = - 9'(_GEN_29 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_30 = {s3_ghist_ptr_dup_2_flag, s3_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = - 9'(_GEN_30 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = - 9'(_GEN_30 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = - 9'(_GEN_30 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _GEN_31 = {s3_ghist_ptr_dup_3_flag, s3_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = - 9'(_GEN_31 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = - 9'(_GEN_31 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = - 9'(_GEN_31 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire _s3_ghv_wdatas_WIRE_13797_1 = + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:{58,129}, :606:28, :620:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] + wire [8:0] _GEN_28 = {s3_ghist_ptr_dup_0_flag, s3_ghist_ptr_dup_0_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_28 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_28 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_28 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_29 = {s3_ghist_ptr_dup_1_flag, s3_ghist_ptr_dup_1_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_29 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_29 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_29 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_30 = {s3_ghist_ptr_dup_2_flag, s3_ghist_ptr_dup_2_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_30 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_30 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_30 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _GEN_31 = {s3_ghist_ptr_dup_3_flag, s3_ghist_ptr_dup_3_value}; // @[src/main/scala/xiangshan/frontend/BPU.scala:326:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_31 - 9'h100); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_31 + 9'hFF); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_31 + 9'hFE); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire _s3_ghv_wdatas_T_57998 = _predictors_io_out_s3_full_pred_0_slot_valids_1 - & _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_0 = + & _predictors_io_out_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s3_predicted_ghist_ptr_dup_T_4 = ~_predictors_io_out_s3_full_pred_0_hit - | ~(_predictors_io_out_s3_full_pred_0_slot_valids_0 | _s3_ghv_wdatas_WIRE_13797_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_98 = + | ~(_predictors_io_out_s3_full_pred_0_slot_valids_0 | _s3_ghv_wdatas_T_57998); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_redirect_on_jalr_target_dup_T_8 = _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s3_redirect_on_jalr_target_dup_T_9 = _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + & _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] wire _s3_both_first_taken_dup_T_7 = _predictors_io_out_s3_full_pred_0_br_taken_mask_1 - & _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_1 = + & _predictors_io_out_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:475:27] + wire _s3_predicted_ghist_ptr_dup_T_32 = _predictors_io_out_s3_full_pred_0_slot_valids_0 - & (_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | ~_s3_ghv_wdatas_WIRE_13797_1) & _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_2 = - _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) - & _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_21_1 = + & (_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | ~_s3_ghv_wdatas_T_57998) & _predictors_io_out_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_ghist_ptr_dup_T_60 = + _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _predictors_io_out_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_ghv_wdatas_T_58023 = _predictors_io_out_s3_full_pred_1_slot_valids_1 - & _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_0 = + & _predictors_io_out_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s3_predicted_ghist_ptr_dup_T_65 = ~_predictors_io_out_s3_full_pred_1_hit - | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_106 = + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_redirect_on_jalr_target_dup_T_28 = _predictors_io_out_s3_full_pred_1_slot_valids_0 - & _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s3_redirect_on_jalr_target_dup_T_29 = _predictors_io_out_s3_full_pred_1_is_br_sharing - & _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_1 = + & _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s3_predicted_ghist_ptr_dup_T_93 = _predictors_io_out_s3_full_pred_1_slot_valids_0 - & (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit - | ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_2 = - _s3_predicted_fh_dup_WIRE_21_1 - & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit) - & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_35_1 = + & (_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_ghist_ptr_dup_T_121 = + _s3_ghv_wdatas_T_58023 + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_ghv_wdatas_T_58048 = _predictors_io_out_s3_full_pred_2_slot_valids_1 - & _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_0 = + & _predictors_io_out_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s3_predicted_ghist_ptr_dup_T_126 = ~_predictors_io_out_s3_full_pred_2_hit - | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_114 = + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_redirect_on_jalr_target_dup_T_48 = _predictors_io_out_s3_full_pred_2_slot_valids_0 - & _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s3_redirect_on_jalr_target_dup_T_49 = _predictors_io_out_s3_full_pred_2_is_br_sharing - & _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_1 = + & _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s3_predicted_ghist_ptr_dup_T_154 = _predictors_io_out_s3_full_pred_2_slot_valids_0 - & (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit - | ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_2 = - _s3_predicted_fh_dup_WIRE_35_1 - & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit) - & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_49_1 = + & (_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_ghist_ptr_dup_T_182 = + _s3_ghv_wdatas_T_58048 + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_ghv_wdatas_T_58073 = _predictors_io_out_s3_full_pred_3_slot_valids_1 - & _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_0 = + & _predictors_io_out_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48] + wire _s3_predicted_ghist_ptr_dup_T_187 = ~_predictors_io_out_s3_full_pred_3_hit - | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _selVecOH_T_122 = + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_redirect_on_jalr_target_dup_T_68 = _predictors_io_out_s3_full_pred_3_slot_valids_0 - & _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + & _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] wire _s3_redirect_on_jalr_target_dup_T_69 = _predictors_io_out_s3_full_pred_3_is_br_sharing - & _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 - wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_1 = + & _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:461:25] + wire _s3_predicted_ghist_ptr_dup_T_215 = _predictors_io_out_s3_full_pred_3_slot_valids_0 - & (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit - | ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_2 = - _s3_predicted_fh_dup_WIRE_49_1 - & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit) - & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_56_1_0 = + & (_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_ghist_ptr_dup_T_243 = + _s3_ghv_wdatas_T_58073 + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_predicted_fh_dup_T_65 = ~_predictors_io_out_s3_full_pred_1_hit - | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s3_predicted_fh_dup_WIRE_56_1_1 = + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_predicted_fh_dup_T_93 = _predictors_io_out_s3_full_pred_1_slot_valids_0 - & (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit - | ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_fh_dup_WIRE_56_1_2 = - _s3_predicted_fh_dup_WIRE_21_1 - & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit) - & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_56_2_0 = + & (_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_fh_dup_T_121 = + _s3_ghv_wdatas_T_58023 + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_predicted_fh_dup_T_126 = ~_predictors_io_out_s3_full_pred_2_hit - | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s3_predicted_fh_dup_WIRE_56_2_1 = + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_predicted_fh_dup_T_154 = _predictors_io_out_s3_full_pred_2_slot_valids_0 - & (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit - | ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_fh_dup_WIRE_56_2_2 = - _s3_predicted_fh_dup_WIRE_35_1 - & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit) - & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 - wire _s3_predicted_fh_dup_WIRE_56_3_0 = + & (_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_fh_dup_T_182 = + _s3_ghv_wdatas_T_58048 + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] + wire _s3_predicted_fh_dup_T_187 = ~_predictors_io_out_s3_full_pred_3_hit - | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} - wire _s3_predicted_fh_dup_WIRE_56_3_1 = + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] + wire _s3_predicted_fh_dup_T_215 = _predictors_io_out_s3_full_pred_3_slot_valids_0 - & (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit - | ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} - wire _s3_predicted_fh_dup_WIRE_56_3_2 = - _s3_predicted_fh_dup_WIRE_49_1 - & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit) - & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + & (_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :489:{34,37,97}] + wire _s3_predicted_fh_dup_T_243 = + _s3_ghv_wdatas_T_58073 + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :488:9, :489:97] wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = - _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = - _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = - _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = - _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = - _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = - _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = - _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - reg [38:0] previous_s2_pred_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg [38:0] previous_s2_pred_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - reg previous_s2_pred_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 - wire _s3_redirect_on_target_dup_selVecOH_T_34 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + reg [40:0] previous_s2_pred_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg [40:0] previous_s2_pred_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + reg previous_s2_pred_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35] + wire _s3_redirect_on_target_dup_T_56 = previous_s2_pred_full_pred_0_slot_valids_0 - & previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - wire _s3_redirect_on_target_dup_selVecOH_T_42 = + & previous_s2_pred_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + wire _s3_redirect_on_target_dup_T_70 = previous_s2_pred_full_pred_1_slot_valids_0 - & previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - wire _s3_redirect_on_target_dup_selVecOH_T_50 = + & previous_s2_pred_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + wire _s3_redirect_on_target_dup_T_84 = previous_s2_pred_full_pred_2_slot_valids_0 - & previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - wire _s3_redirect_on_target_dup_selVecOH_T_58 = + & previous_s2_pred_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + wire _s3_redirect_on_target_dup_T_98 = previous_s2_pred_full_pred_3_slot_valids_0 - & previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - wire _s3_redirect_on_target_dup_WIRE_1 = + & previous_s2_pred_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + wire _s3_redirect_on_target_dup_T_4 = _predictors_io_out_s3_full_pred_0_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_9 - | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _s3_redirect_on_target_dup_WIRE_1_3 = - 39'(_predictors_io_out_s3_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire _s3_redirect_on_target_dup_WIRE_3_1 = + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _s3_redirect_on_target_dup_T_5 = + 41'(_predictors_io_out_s3_pc_0 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire _s3_redirect_on_target_dup_T_18 = _predictors_io_out_s3_full_pred_1_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_29 - | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _s3_redirect_on_target_dup_WIRE_4_3 = - 39'(_predictors_io_out_s3_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire _s3_redirect_on_target_dup_WIRE_6_1 = + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _s3_redirect_on_target_dup_T_19 = + 41'(_predictors_io_out_s3_pc_1 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire _s3_redirect_on_target_dup_T_32 = _predictors_io_out_s3_full_pred_2_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_49 - | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _s3_redirect_on_target_dup_WIRE_7_3 = - 39'(_predictors_io_out_s3_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire _s3_redirect_on_target_dup_WIRE_9_1 = + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _s3_redirect_on_target_dup_T_33 = + 41'(_predictors_io_out_s3_pc_2 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire _s3_redirect_on_target_dup_T_46 = _predictors_io_out_s3_full_pred_3_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_69 - | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire [38:0] _s3_redirect_on_target_dup_WIRE_10_3 = - 39'(_predictors_io_out_s3_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 - wire _s3_redirect_on_target_dup_WIRE_13_1 = + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire [40:0] _s3_redirect_on_target_dup_T_47 = + 41'(_predictors_io_out_s3_pc_3 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:506:47] + wire _s3_redirect_on_target_dup_T_60 = previous_s2_pred_full_pred_0_slot_valids_1 & (previous_s2_pred_full_pred_0_is_br_sharing & previous_s2_pred_full_pred_0_br_taken_mask_1 - | ~previous_s2_pred_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire _s3_redirect_on_target_dup_WIRE_16_1 = + | ~previous_s2_pred_full_pred_0_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire _s3_redirect_on_target_dup_T_74 = previous_s2_pred_full_pred_1_slot_valids_1 & (previous_s2_pred_full_pred_1_is_br_sharing & previous_s2_pred_full_pred_1_br_taken_mask_1 - | ~previous_s2_pred_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire _s3_redirect_on_target_dup_WIRE_19_1 = + | ~previous_s2_pred_full_pred_1_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire _s3_redirect_on_target_dup_T_88 = previous_s2_pred_full_pred_2_slot_valids_1 & (previous_s2_pred_full_pred_2_is_br_sharing & previous_s2_pred_full_pred_2_br_taken_mask_1 - | ~previous_s2_pred_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire _s3_redirect_on_target_dup_WIRE_22_1 = + | ~previous_s2_pred_full_pred_2_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire _s3_redirect_on_target_dup_T_102 = previous_s2_pred_full_pred_3_slot_valids_1 & (previous_s2_pred_full_pred_3_is_br_sharing & previous_s2_pred_full_pred_3_br_taken_mask_1 - | ~previous_s2_pred_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + | ~previous_s2_pred_full_pred_3_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:674:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] assign s3_redirect_dup_0 = s3_valid_dup_3 & ({_s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing & _predictors_io_out_s3_full_pred_0_hit, - _selVecOH_T_98 + _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit} != {previous_s2_pred_full_pred_0_br_taken_mask_1 & previous_s2_pred_full_pred_0_slot_valids_1 & previous_s2_pred_full_pred_0_is_br_sharing & previous_s2_pred_full_pred_0_hit, - _s3_redirect_on_target_dup_selVecOH_T_34 + _s3_redirect_on_target_dup_T_56 & previous_s2_pred_full_pred_0_hit} - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - & _s3_redirect_on_target_dup_selVecOH_T_34 & previous_s2_pred_full_pred_0_hit) - | ((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + & _s3_redirect_on_target_dup_T_56 & previous_s2_pred_full_pred_0_hit) + | ((_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_targets_0 - : 39'h0) - | (~_selVecOH_T_98 & _s3_redirect_on_target_dup_WIRE_1 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_8 & _s3_redirect_on_target_dup_T_4 & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_1, _selVecOH_T_98} == 2'h0 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_4, _s3_redirect_on_jalr_target_dup_T_8} == 2'h0 & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_0_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_1_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_34 - & previous_s2_pred_full_pred_0_hit - ? previous_s2_pred_full_pred_0_targets_0 - : 39'h0) - | (~_s3_redirect_on_target_dup_selVecOH_T_34 - & _s3_redirect_on_target_dup_WIRE_13_1 - & previous_s2_pred_full_pred_0_hit - ? previous_s2_pred_full_pred_0_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_13_1, - _s3_redirect_on_target_dup_selVecOH_T_34} == 2'h0 - & previous_s2_pred_full_pred_0_hit - ? previous_s2_pred_full_pred_0_fallThroughAddr - : 39'h0) - | (previous_s2_pred_full_pred_0_hit - ? 39'h0 - : 39'(previous_s2_pred_pc_0 - + 39'h20))) + ? 41'h0 + : _s3_redirect_on_target_dup_T_5)) != ((_s3_redirect_on_target_dup_T_56 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_56 + & _s3_redirect_on_target_dup_T_60 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_60, + _s3_redirect_on_target_dup_T_56} == 2'h0 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_0_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_0 + + 41'h20))) | _predictors_io_out_s3_full_pred_0_hit - & _predictors_io_out_s3_full_pred_0_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:{27,63}, :505:47, :508:33 + & _predictors_io_out_s3_full_pred_0_fallThroughErr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :344:53, :674:35, :676:{136,143,172}, :677:135, :678:110, :685:28, :686:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :474:32, :475:{27,63}, :506:47, :509:33] wire s3_redirect_dup_1 = s3_valid_dup_3 & ({_predictors_io_out_s3_full_pred_1_br_taken_mask_1 & _predictors_io_out_s3_full_pred_1_slot_valids_1 & _predictors_io_out_s3_full_pred_1_is_br_sharing & _predictors_io_out_s3_full_pred_1_hit, - _selVecOH_T_106 + _s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit} != {previous_s2_pred_full_pred_1_br_taken_mask_1 & previous_s2_pred_full_pred_1_slot_valids_1 & previous_s2_pred_full_pred_1_is_br_sharing & previous_s2_pred_full_pred_1_hit, - _s3_redirect_on_target_dup_selVecOH_T_42 + _s3_redirect_on_target_dup_T_70 & previous_s2_pred_full_pred_1_hit} - & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit - & _s3_redirect_on_target_dup_selVecOH_T_42 & previous_s2_pred_full_pred_1_hit) - | ((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + & _s3_redirect_on_target_dup_T_70 & previous_s2_pred_full_pred_1_hit) + | ((_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_targets_0 - : 39'h0) - | (~_selVecOH_T_106 & _s3_redirect_on_target_dup_WIRE_3_1 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_28 & _s3_redirect_on_target_dup_T_18 & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_3_1, _selVecOH_T_106} == 2'h0 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_18, + _s3_redirect_on_jalr_target_dup_T_28} == 2'h0 & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_1_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_4_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_42 - & previous_s2_pred_full_pred_1_hit - ? previous_s2_pred_full_pred_1_targets_0 - : 39'h0) - | (~_s3_redirect_on_target_dup_selVecOH_T_42 - & _s3_redirect_on_target_dup_WIRE_16_1 - & previous_s2_pred_full_pred_1_hit - ? previous_s2_pred_full_pred_1_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_16_1, - _s3_redirect_on_target_dup_selVecOH_T_42} == 2'h0 - & previous_s2_pred_full_pred_1_hit - ? previous_s2_pred_full_pred_1_fallThroughAddr - : 39'h0) - | (previous_s2_pred_full_pred_1_hit - ? 39'h0 - : 39'(previous_s2_pred_pc_1 - + 39'h20))) + ? 41'h0 + : _s3_redirect_on_target_dup_T_19)) != ((_s3_redirect_on_target_dup_T_70 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_70 + & _s3_redirect_on_target_dup_T_74 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_74, + _s3_redirect_on_target_dup_T_70} == 2'h0 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_1_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_1 + + 41'h20))) | _predictors_io_out_s3_full_pred_1_hit - & _predictors_io_out_s3_full_pred_1_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + & _predictors_io_out_s3_full_pred_1_fallThroughErr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :344:53, :674:35, :676:{136,143,172}, :677:135, :678:110, :685:28, :686:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :474:32, :475:63, :506:47, :509:33] assign s3_redirect_dup_2 = s3_valid_dup_3 & ({_predictors_io_out_s3_full_pred_2_br_taken_mask_1 & _predictors_io_out_s3_full_pred_2_slot_valids_1 & _predictors_io_out_s3_full_pred_2_is_br_sharing & _predictors_io_out_s3_full_pred_2_hit, - _selVecOH_T_114 + _s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit} != {previous_s2_pred_full_pred_2_br_taken_mask_1 & previous_s2_pred_full_pred_2_slot_valids_1 & previous_s2_pred_full_pred_2_is_br_sharing & previous_s2_pred_full_pred_2_hit, - _s3_redirect_on_target_dup_selVecOH_T_50 + _s3_redirect_on_target_dup_T_84 & previous_s2_pred_full_pred_2_hit} - & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit - & _s3_redirect_on_target_dup_selVecOH_T_50 & previous_s2_pred_full_pred_2_hit) - | ((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + & _s3_redirect_on_target_dup_T_84 & previous_s2_pred_full_pred_2_hit) + | ((_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_targets_0 - : 39'h0) - | (~_selVecOH_T_114 & _s3_redirect_on_target_dup_WIRE_6_1 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_48 & _s3_redirect_on_target_dup_T_32 & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_6_1, _selVecOH_T_114} == 2'h0 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_32, + _s3_redirect_on_jalr_target_dup_T_48} == 2'h0 & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_2_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_7_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_50 - & previous_s2_pred_full_pred_2_hit - ? previous_s2_pred_full_pred_2_targets_0 - : 39'h0) - | (~_s3_redirect_on_target_dup_selVecOH_T_50 - & _s3_redirect_on_target_dup_WIRE_19_1 - & previous_s2_pred_full_pred_2_hit - ? previous_s2_pred_full_pred_2_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_19_1, - _s3_redirect_on_target_dup_selVecOH_T_50} == 2'h0 - & previous_s2_pred_full_pred_2_hit - ? previous_s2_pred_full_pred_2_fallThroughAddr - : 39'h0) - | (previous_s2_pred_full_pred_2_hit - ? 39'h0 - : 39'(previous_s2_pred_pc_2 - + 39'h20))) + ? 41'h0 + : _s3_redirect_on_target_dup_T_33)) != ((_s3_redirect_on_target_dup_T_84 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_84 + & _s3_redirect_on_target_dup_T_88 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_88, + _s3_redirect_on_target_dup_T_84} == 2'h0 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_2_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_2 + + 41'h20))) | _predictors_io_out_s3_full_pred_2_hit - & _predictors_io_out_s3_full_pred_2_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + & _predictors_io_out_s3_full_pred_2_fallThroughErr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :344:53, :674:35, :676:{136,143,172}, :677:135, :678:110, :685:28, :686:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :474:32, :475:63, :506:47, :509:33] assign s3_redirect_dup_3 = s3_valid_dup_3 & ({_predictors_io_out_s3_full_pred_3_br_taken_mask_1 & _predictors_io_out_s3_full_pred_3_slot_valids_1 & _predictors_io_out_s3_full_pred_3_is_br_sharing & _predictors_io_out_s3_full_pred_3_hit, - _selVecOH_T_122 + _s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit} != {previous_s2_pred_full_pred_3_br_taken_mask_1 & previous_s2_pred_full_pred_3_slot_valids_1 & previous_s2_pred_full_pred_3_is_br_sharing & previous_s2_pred_full_pred_3_hit, - _s3_redirect_on_target_dup_selVecOH_T_58 + _s3_redirect_on_target_dup_T_98 & previous_s2_pred_full_pred_3_hit} - & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit - & _s3_redirect_on_target_dup_selVecOH_T_58 & previous_s2_pred_full_pred_3_hit) - | ((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + & _s3_redirect_on_target_dup_T_98 & previous_s2_pred_full_pred_3_hit) + | ((_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_targets_0 - : 39'h0) - | (~_selVecOH_T_122 & _s3_redirect_on_target_dup_WIRE_9_1 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_68 & _s3_redirect_on_target_dup_T_46 & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_9_1, _selVecOH_T_122} == 2'h0 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_46, + _s3_redirect_on_jalr_target_dup_T_68} == 2'h0 & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_3_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_10_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_58 - & previous_s2_pred_full_pred_3_hit - ? previous_s2_pred_full_pred_3_targets_0 - : 39'h0) - | (~_s3_redirect_on_target_dup_selVecOH_T_58 - & _s3_redirect_on_target_dup_WIRE_22_1 - & previous_s2_pred_full_pred_3_hit - ? previous_s2_pred_full_pred_3_targets_1 - : 39'h0) - | ({_s3_redirect_on_target_dup_WIRE_22_1, - _s3_redirect_on_target_dup_selVecOH_T_58} == 2'h0 - & previous_s2_pred_full_pred_3_hit - ? previous_s2_pred_full_pred_3_fallThroughAddr - : 39'h0) - | (previous_s2_pred_full_pred_3_hit - ? 39'h0 - : 39'(previous_s2_pred_pc_3 - + 39'h20))) + ? 41'h0 + : _s3_redirect_on_target_dup_T_47)) != ((_s3_redirect_on_target_dup_T_98 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_98 + & _s3_redirect_on_target_dup_T_102 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_102, + _s3_redirect_on_target_dup_T_98} == 2'h0 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_3_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_3 + + 41'h20))) | _predictors_io_out_s3_full_pred_3_hit - & _predictors_io_out_s3_full_pred_3_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + & _predictors_io_out_s3_full_pred_3_fallThroughErr); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :272:65, :292:73, :344:53, :674:35, :676:{136,143,172}, :677:135, :678:110, :685:28, :686:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :474:32, :475:63, :506:47, :509:33] wire _GEN_32 = _predictors_io_out_s3_full_pred_0_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_9 - | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_33 = _predictors_io_out_s3_full_pred_1_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_29 - | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_34 = _predictors_io_out_s3_full_pred_2_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_49 - | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] wire _GEN_35 = _predictors_io_out_s3_full_pred_3_slot_valids_1 & (_s3_redirect_on_jalr_target_dup_T_69 - | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} - wire _GEN_36 = _selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_37 = _selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire _GEN_38 = _selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25, :461:{25,47,50}] + wire _GEN_36 = + _s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_37 = + _s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire _GEN_38 = + _s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] wire _ghv_wens_0_T_2 = ~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_1_T_2 = s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_2_T_2 = s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_3_T_2 = s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_4_T_2 = s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_5_T_2 = s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_6_T_2 = s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_7_T_2 = s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_8_T_2 = s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_9_T_2 = s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_10_T_2 = s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_11_T_2 = s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_12_T_2 = s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_13_T_2 = s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_14_T_2 = s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_15_T_2 = s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_16_T_2 = s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_17_T_2 = s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_18_T_2 = s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_19_T_2 = s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_20_T_2 = s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_21_T_2 = s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_22_T_2 = s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_23_T_2 = s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_24_T_2 = s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_25_T_2 = s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_26_T_2 = s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_27_T_2 = s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_28_T_2 = s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_29_T_2 = s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_30_T_2 = s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_31_T_2 = s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_32_T_2 = s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_33_T_2 = s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_34_T_2 = s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_35_T_2 = s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_36_T_2 = s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_37_T_2 = s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_38_T_2 = s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_39_T_2 = s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_40_T_2 = s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_41_T_2 = s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_42_T_2 = s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_43_T_2 = s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_44_T_2 = s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_45_T_2 = s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_46_T_2 = s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_47_T_2 = s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_48_T_2 = s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_49_T_2 = s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_50_T_2 = s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_51_T_2 = s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_52_T_2 = s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_53_T_2 = s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_54_T_2 = s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_55_T_2 = s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_56_T_2 = s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_57_T_2 = s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_58_T_2 = s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_59_T_2 = s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_60_T_2 = s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_61_T_2 = s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_62_T_2 = s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_63_T_2 = s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_64_T_2 = s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_65_T_2 = s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_66_T_2 = s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_67_T_2 = s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_68_T_2 = s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_69_T_2 = s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_70_T_2 = s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_71_T_2 = s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_72_T_2 = s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_73_T_2 = s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_74_T_2 = s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_75_T_2 = s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_76_T_2 = s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_77_T_2 = s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_78_T_2 = s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_79_T_2 = s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_80_T_2 = s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_81_T_2 = s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_82_T_2 = s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_83_T_2 = s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_84_T_2 = s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_85_T_2 = s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_86_T_2 = s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_87_T_2 = s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_88_T_2 = s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_89_T_2 = s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_90_T_2 = s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_91_T_2 = s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_92_T_2 = s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_93_T_2 = s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_94_T_2 = s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_95_T_2 = s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_96_T_2 = s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_97_T_2 = s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_98_T_2 = s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_99_T_2 = s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_100_T_2 = s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_101_T_2 = s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_102_T_2 = s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_103_T_2 = s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_104_T_2 = s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_105_T_2 = s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_106_T_2 = s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_107_T_2 = s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_108_T_2 = s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_109_T_2 = s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_110_T_2 = s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_111_T_2 = s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_112_T_2 = s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_113_T_2 = s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_114_T_2 = s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_115_T_2 = s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_116_T_2 = s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_117_T_2 = s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_118_T_2 = s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_119_T_2 = s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_120_T_2 = s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_121_T_2 = s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_122_T_2 = s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_123_T_2 = s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_124_T_2 = s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_125_T_2 = s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_126_T_2 = s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_127_T_2 = s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_128_T_2 = s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_129_T_2 = s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_130_T_2 = s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_131_T_2 = s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_132_T_2 = s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_133_T_2 = s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_134_T_2 = s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_135_T_2 = s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_136_T_2 = s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_137_T_2 = s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_138_T_2 = s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_139_T_2 = s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_140_T_2 = s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_141_T_2 = s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_142_T_2 = s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_143_T_2 = s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_144_T_2 = s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_145_T_2 = s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_146_T_2 = s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_147_T_2 = s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_148_T_2 = s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_149_T_2 = s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_150_T_2 = s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_151_T_2 = s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_152_T_2 = s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_153_T_2 = s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_154_T_2 = s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_155_T_2 = s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_156_T_2 = s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_157_T_2 = s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_158_T_2 = s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_159_T_2 = s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_160_T_2 = s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_161_T_2 = s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_162_T_2 = s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_163_T_2 = s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_164_T_2 = s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_165_T_2 = s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_166_T_2 = s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_167_T_2 = s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_168_T_2 = s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_169_T_2 = s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_170_T_2 = s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_171_T_2 = s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_172_T_2 = s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_173_T_2 = s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_174_T_2 = s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_175_T_2 = s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_176_T_2 = s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_177_T_2 = s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_178_T_2 = s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_179_T_2 = s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_180_T_2 = s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_181_T_2 = s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_182_T_2 = s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_183_T_2 = s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_184_T_2 = s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_185_T_2 = s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_186_T_2 = s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_187_T_2 = s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_188_T_2 = s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_189_T_2 = s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_190_T_2 = s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_191_T_2 = s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_192_T_2 = s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_193_T_2 = s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_194_T_2 = s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_195_T_2 = s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_196_T_2 = s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_197_T_2 = s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_198_T_2 = s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_199_T_2 = s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_200_T_2 = s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_201_T_2 = s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_202_T_2 = s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_203_T_2 = s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_204_T_2 = s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_205_T_2 = s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_206_T_2 = s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_207_T_2 = s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_208_T_2 = s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_209_T_2 = s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_210_T_2 = s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] wire _ghv_wens_211_T_2 = s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_212_T_2 = s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_213_T_2 = s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_214_T_2 = s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_215_T_2 = s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_216_T_2 = s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_217_T_2 = s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_218_T_2 = s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_219_T_2 = s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_220_T_2 = s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_221_T_2 = s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_222_T_2 = s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_223_T_2 = s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_224_T_2 = s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_225_T_2 = s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_226_T_2 = s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_227_T_2 = s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_228_T_2 = s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_229_T_2 = s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_230_T_2 = s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_231_T_2 = s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_232_T_2 = s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_233_T_2 = s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_234_T_2 = s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_235_T_2 = s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_236_T_2 = s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_237_T_2 = s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_238_T_2 = s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_239_T_2 = s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_240_T_2 = s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_241_T_2 = s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_242_T_2 = s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_243_T_2 = s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_244_T_2 = s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_245_T_2 = s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_246_T_2 = s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_247_T_2 = s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_248_T_2 = s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_249_T_2 = s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_250_T_2 = s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_251_T_2 = s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_252_T_2 = s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_253_T_2 = s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_254_T_2 = s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + & s3_redirect_dup_0 | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12] wire _ghv_wens_255_T_2 = (&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & s3_redirect_dup_0 | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 - reg s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 - reg [5:0] s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 - reg s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:709:29 - reg [5:0] s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:709:29 - reg predictors_io_update_REG_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [38:0] predictors_io_update_REG_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [10:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [10:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [6:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [8:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [3:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [8:0] - predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [8:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [10:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [3:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [11:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [1:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [3:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [19:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [1:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [3:0] predictors_io_update_REG_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [3:0] predictors_io_update_REG_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg predictors_io_update_REG_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [218:0] predictors_io_update_REG_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - reg [38:0] predictors_io_update_REG_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - wire [1:0] _shouldShiftVec_dup_T_46 = 2'(thisBrNumOH_dup_shiftAmount - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:156 - wire [3:0] _shouldShiftVec_dup_T_4 = 4'h1 << _shouldShiftVec_dup_T_46; // src/main/scala/xiangshan/frontend/BPU.scala:737:{147,156} - wire [1:0] _GEN_39 = _shouldShiftVec_dup_T_4[1:0] | _shouldShiftVec_dup_T_4[2:1]; // src/main/scala/xiangshan/frontend/BPU.scala:737:147, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + & s3_redirect_dup_0 | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:{58,129}, :685:28, :705:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12] + reg s2_ftq_idx_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29] + reg [5:0] s2_ftq_idx_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29] + reg s3_ftq_idx_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:710:29] + reg [5:0] s3_ftq_idx_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:710:29] + reg predictors_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:728:40] + reg [40:0] predictors_io_update_bits_r_pc; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [3:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [3:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [11:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [1:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [3:0] predictors_io_update_bits_r_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [19:0] predictors_io_update_bits_r_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [1:0] predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [3:0] predictors_io_update_bits_r_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_isCall; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_isRet; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_isJalr; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_cfi_idx_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [3:0] predictors_io_update_bits_r_cfi_idx_bits; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_jmp_taken; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_mispred_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_mispred_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_mispred_mask_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg predictors_io_update_bits_r_old_entry; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [222:0] predictors_io_update_bits_r_meta; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + reg [40:0] predictors_io_update_bits_r_full_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + wire [1:0] _shouldShiftVec_dup_T_46 = + 2'(do_redirect_dup_next_bits_r_cfiUpdate_shift - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:740:156, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] _shouldShiftVec_dup_T_4 = 4'h1 << _shouldShiftVec_dup_T_46; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:{147,156}] + wire [1:0] _GEN_39 = _shouldShiftVec_dup_T_4[1:0] | _shouldShiftVec_dup_T_4[2:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:147, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire shouldShiftVec_dup_0_0 = - (|thisBrNumOH_dup_shiftAmount) - & (_GEN_39[0] | _shouldShiftVec_dup_T_46 == 2'h2 | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :737:{54,61,156}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + (|do_redirect_dup_next_bits_r_cfiUpdate_shift) + & (_GEN_39[0] | _shouldShiftVec_dup_T_46 == 2'h2 | (&_shouldShiftVec_dup_T_46)); // @[src/main/scala/xiangshan/frontend/BPU.scala:441:30, :740:{54,61,156}, utility/src/main/scala/utility/BitUtils.scala:33:27, :124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire shouldShiftVec_dup_0_1 = - (|thisBrNumOH_dup_shiftAmount) & (_GEN_39[1] | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:{54,61,156}, utility/src/main/scala/utility/ParallelMux.scala:36:53 + (|do_redirect_dup_next_bits_r_cfiUpdate_shift) + & (_GEN_39[1] | (&_shouldShiftVec_dup_T_46)); // @[src/main/scala/xiangshan/frontend/BPU.scala:740:{54,61,156}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ParallelMux.scala:36:53] wire real_br_taken_mask_dup_0_0 = - thisBrNumOH_dup_shiftAmount == 2'h1 & do_redirect_dup_3_bits_cfiUpdate_taken - & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :747:{44,65} + do_redirect_dup_next_bits_r_cfiUpdate_shift == 2'h1 + & do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; // @[src/main/scala/xiangshan/frontend/BPU.scala:750:{44,65}, utility/src/main/scala/utility/BitUtils.scala:33:27] wire real_br_taken_mask_dup_0_1 = - thisBrNumOH_dup_shiftAmount == 2'h2 & do_redirect_dup_3_bits_cfiUpdate_taken - & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :747:{44,65} + do_redirect_dup_next_bits_r_cfiUpdate_shift == 2'h2 + & do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; // @[src/main/scala/xiangshan/frontend/BPU.scala:441:30, :750:{44,65}, utility/src/main/scala/utility/BitUtils.scala:33:27] wire [8:0] _updated_ptr_dup_flipped_new_ptr_T_6 = - 9'(9'h100 - {7'h0, thisBrNumOH_dup_shiftAmount}); // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + 9'(9'h100 - {7'h0, do_redirect_dup_next_bits_r_cfiUpdate_shift}); // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50] wire [8:0] _GEN_40 = - {do_redirect_dup_3_bits_cfiUpdate_histPtr_flag, - do_redirect_dup_3_bits_cfiUpdate_histPtr_value}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1 = - 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 - wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3 = - 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 - wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5 = - 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 - wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7 = - 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 - wire - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 = - do_redirect_dup_3_bits_cfiUpdate_taken & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83 + {do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag, + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value}; // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50] + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50] + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50] + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50] + wire _updated_ghist_1_T = + do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; // @[src/main/scala/xiangshan/frontend/BPU.scala:758:83, utility/src/main/scala/utility/BitUtils.scala:33:27] wire _GEN_41 = - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[0] - | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_1_0_hist_0_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[0] + | _updated_ghist_1_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_0_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] wire _GEN_42 = - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[0] - | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [3:0] _updated_fh_dup_WIRE_1_0_hist_12_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[0] + | _updated_ghist_1_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] updated_fh_dup_res_hist_12_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] wire _GEN_43 = - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[0] - | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_1_0_hist_14_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_2_0_hist_0_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [3:0] _updated_fh_dup_WIRE_2_0_hist_12_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_2_0_hist_14_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_3_0_hist_0_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [3:0] _updated_fh_dup_WIRE_3_0_hist_12_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [7:0] _updated_fh_dup_WIRE_3_0_hist_14_folded_hist = - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 - wire [3:0] _GEN_44 = {2'h0, thisBrNumOH_dup_shiftAmount}; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - wire [3:0] _thisBrNumOH_dup_T_1 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 - wire [3:0] _thisBrNumOH_dup_T_2 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 - wire [3:0] _thisBrNumOH_dup_T_3 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[0] + | _updated_ghist_1_T; // @[src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_14_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_0_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] updated_fh_dup_res_hist_12_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_14_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_0_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] updated_fh_dup_res_hist_12_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [7:0] updated_fh_dup_res_hist_14_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:29, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] _GEN_44 = {2'h0, do_redirect_dup_next_bits_r_cfiUpdate_shift}; // @[src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:292:73, utility/src/main/scala/utility/BitUtils.scala:33:27] + wire [3:0] _thisBrNumOH_dup_T_1 = 4'h1 << _GEN_44; // @[src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:740:147] + wire [3:0] _thisBrNumOH_dup_T_2 = 4'h1 << _GEN_44; // @[src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:740:147] + wire [3:0] _thisBrNumOH_dup_T_3 = 4'h1 << _GEN_44; // @[src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:740:147] wire thisAheadFhOb_dup_1_afhob_0_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_1_afhob_0_bits_2 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_1_afhob_0_bits_3 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_1_afhob_1_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_2_afhob_0_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_2_afhob_0_bits_2 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_2_afhob_0_bits_3 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_2_afhob_1_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_3_afhob_0_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_3_afhob_0_bits_2 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_3_afhob_0_bits_3 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire thisAheadFhOb_dup_3_afhob_1_bits_0 = - _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] wire _ghv_wens_0_T_3 = - ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_1_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_2_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_3_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_4_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_5_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_6_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_7_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_8_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_9_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_10_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_11_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_12_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_13_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_14_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_15_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_16_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_17_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_18_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_19_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_20_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_21_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_22_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_23_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_24_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_25_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_26_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_27_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_28_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_29_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_30_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_31_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_32_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_33_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_34_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_35_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_36_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_37_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_38_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_39_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_40_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_41_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_42_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_43_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_44_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_45_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_46_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_47_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_48_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_49_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_50_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_51_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_52_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_53_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_54_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_55_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_56_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_57_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_58_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_59_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_60_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_61_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_62_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_63_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_64_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_65_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_66_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_67_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_68_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_69_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_70_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_71_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_72_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_73_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_74_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_75_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_76_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_77_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_78_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_79_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_80_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_81_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_82_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_83_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_84_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_85_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_86_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_87_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_88_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_89_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_90_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_91_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_92_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_93_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_94_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_95_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_96_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_97_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_98_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_99_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_100_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_101_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_102_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_103_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_104_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_105_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_106_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_107_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_108_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_109_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_110_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_111_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_112_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_113_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_114_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_115_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_116_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_117_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_118_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_119_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_120_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_121_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_122_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_123_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_124_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_125_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_126_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_127_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_128_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_129_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_130_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_131_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_132_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_133_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_134_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_135_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_136_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_137_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_138_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_139_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_140_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_141_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_142_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_143_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_144_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_145_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_146_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_147_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_148_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_149_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_150_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_151_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_152_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_153_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_154_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_155_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_156_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_157_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_158_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_159_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_160_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_161_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_162_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_163_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_164_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_165_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_166_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_167_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_168_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_169_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_170_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_171_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_172_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_173_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_174_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_175_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_176_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_177_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_178_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_179_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_180_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_181_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_182_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_183_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_184_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_185_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_186_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_187_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_188_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_189_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_190_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_191_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_192_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_193_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_194_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_195_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_196_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_197_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_198_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_199_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_200_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_201_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_202_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_203_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_204_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_205_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_206_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_207_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_208_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_209_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_210_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_211_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_212_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_213_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_214_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_215_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_216_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_217_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_218_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_219_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_220_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_221_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_222_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_223_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_224_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_225_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_226_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_227_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_228_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_229_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_230_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_231_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_232_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_233_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_234_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_235_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_236_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_237_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_238_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_239_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_240_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_241_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_242_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_243_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_244_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_245_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_246_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_247_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_248_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_249_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_250_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_251_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_252_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_253_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_254_T_3 = - do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire _ghv_wens_255_T_3 = - (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 - & do_redirect_dup_3_valid | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) - & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26 + (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; // @[src/main/scala/xiangshan/frontend/BPU.scala:740:54, :763:{50,117}, :858:26, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] wire [3:0][10:0] _GEN_45 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_46 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_47 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_48 = - {{_updated_fh_dup_WIRE_1_0_hist_14_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + {{updated_fh_dup_res_hist_14_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_1_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_3_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_49 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][3:0] _GEN_50 = - {{_updated_fh_dup_WIRE_1_0_hist_12_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + {{updated_fh_dup_res_hist_12_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_1_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_3_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_51 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_52 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_53 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_54 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_55 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_56 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_57 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_58 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_59 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_60 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_61 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_62 = - {{_updated_fh_dup_WIRE_1_0_hist_0_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + {{updated_fh_dup_res_hist_0_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_1_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_3_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_63 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_64 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_65 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_66 = - {{_updated_fh_dup_WIRE_2_0_hist_14_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + {{updated_fh_dup_res_hist_14_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_2_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_6_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_67 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][3:0] _GEN_68 = - {{_updated_fh_dup_WIRE_2_0_hist_12_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + {{updated_fh_dup_res_hist_12_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_2_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_6_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_69 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_70 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_71 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_72 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_73 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_74 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_75 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_76 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_77 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_78 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_79 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_80 = - {{_updated_fh_dup_WIRE_2_0_hist_0_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + {{updated_fh_dup_res_hist_0_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_2_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_6_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_81 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_82 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_83 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_84 = - {{_updated_fh_dup_WIRE_3_0_hist_14_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + {{updated_fh_dup_res_hist_14_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_3_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_9_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_85 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][3:0] _GEN_86 = - {{_updated_fh_dup_WIRE_3_0_hist_12_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + {{updated_fh_dup_res_hist_12_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_3_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_9_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_87 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_88 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_89 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_90 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_91 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][8:0] _GEN_92 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, - {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][6:0] _GEN_93 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_94 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_95 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_96 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][10:0] _GEN_97 = - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], - (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 - | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] - & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 - ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, - {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] wire [3:0][7:0] _GEN_98 = - {{_updated_fh_dup_WIRE_3_0_hist_0_folded_hist}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + {{updated_fh_dup_res_hist_0_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], 1'h0, - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], - _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, - {_updated_fh_dup_WIRE_3_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_9_folded_hist}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :758:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + reg [5:0] io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_2_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_3_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_3_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_4_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_4_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_5_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_5_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg [5:0] io_perf_6_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg [5:0] io_perf_6_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] wire _GEN_99 = - _cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 - wire s2_flush_dup_0 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 - wire s2_flush_dup_1 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 - wire s2_flush_dup_2 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 - wire s1_flush_dup_0 = s2_flush_dup_0 | s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 - wire s1_flush_dup_1 = s2_flush_dup_1 | s2_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 - wire s1_flush_dup_2 = s2_flush_dup_2 | s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 - wire s1_flush_dup_3 = s2_flush_dup_3 | s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 - wire _GEN_100 = s3_valid_dup_3 | io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :408:{26,37}, :409:26, :410:{26,37} - always @(posedge clock or posedge reset) begin - if (reset) begin - s1_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s2_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s3_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s0_folded_gh_reg_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s1_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s2_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s3_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s0_last_br_num_oh_reg_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s0_last_br_num_oh_reg_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s0_last_br_num_oh_reg_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s1_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s1_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s1_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s2_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s2_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s2_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s3_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s3_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s3_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - ghv_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_4 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_5 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_6 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_7 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_8 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_9 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_10 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_11 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_12 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_13 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_14 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_15 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_16 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_17 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_18 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_19 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_20 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_21 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_22 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_23 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_24 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_25 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_26 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_27 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_28 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_29 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_30 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_31 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_32 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_33 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_34 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_35 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_36 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_37 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_38 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_39 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_40 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_41 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_42 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_43 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_44 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_45 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_46 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_47 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_48 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_49 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_50 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_51 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_52 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_53 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_54 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_55 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_56 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_57 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_58 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_59 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_60 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_61 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_62 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_63 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_64 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_65 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_66 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_67 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_68 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_69 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_70 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_71 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_72 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_73 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_74 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_75 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_76 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_77 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_78 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_79 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_80 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_81 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_82 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_83 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_84 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_85 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_86 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_87 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_88 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_89 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_90 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_91 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_92 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_93 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_94 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_95 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_96 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_97 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_98 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_99 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_100 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_101 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_102 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_103 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_104 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_105 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_106 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_107 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_108 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_109 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_110 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_111 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_112 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_113 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_114 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_115 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_116 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_117 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_118 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_119 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_120 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_121 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_122 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_123 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_124 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_125 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_126 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_127 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_128 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_129 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_130 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_131 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_132 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_133 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_134 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_135 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_136 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_137 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_138 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_139 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_140 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_141 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_142 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_143 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_144 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_145 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_146 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_147 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_148 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_149 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_150 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_151 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_152 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_153 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_154 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_155 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_156 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_157 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_158 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_159 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_160 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_161 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_162 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_163 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_164 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_165 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_166 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_167 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_168 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_169 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_170 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_171 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_172 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_173 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_174 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_175 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_176 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_177 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_178 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_179 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_180 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_181 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_182 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_183 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_184 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_185 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_186 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_187 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_188 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_189 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_190 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_191 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_192 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_193 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_194 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_195 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_196 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_197 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_198 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_199 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_200 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_201 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_202 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_203 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_204 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_205 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_206 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_207 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_208 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_209 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_210 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_211 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_212 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_213 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_214 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_215 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_216 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_217 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_218 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_219 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_220 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_221 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_222 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_223 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_224 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_225 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_226 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_227 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_228 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_229 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_230 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_231 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_232 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_233 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_234 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_235 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_236 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_237 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_238 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_239 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_240 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_241 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_242 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_243 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_244 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_245 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_246 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_247 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_248 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_249 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_250 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_251 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_252 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_253 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_254 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_255 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - s0_ghist_ptr_reg_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s1_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s2_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s3_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - do_redirect_dup_3_valid <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_level <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pc <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isCall <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRet <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_ssp <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_sctr <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_target <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_taken <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - thisBrNumOH_dup_shiftAmount <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_addIntoHist <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - previous_s1_pred_info_hit_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_target_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_lastBrPosOH_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_0_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_0 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_1 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_2 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_3 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s2_pred_pc_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :474:32] + wire s2_flush_dup_0 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :685:28] + wire s2_flush_dup_1 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :685:28] + wire s2_flush_dup_2 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :685:28] + wire s1_flush_dup_0 = s2_flush_dup_0 | s2_redirect_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :361:26, :606:28] + wire s1_flush_dup_1 = s2_flush_dup_1 | s2_redirect_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :361:26, :606:28] + wire s1_flush_dup_2 = s2_flush_dup_2 | s2_redirect_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :361:26, :606:28] + wire s1_flush_dup_3 = s2_flush_dup_3 | s2_redirect_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:359:26, :361:26, :606:28] + wire _GEN_100 = s3_valid_dup_3 | io_ftq_to_bpu_redirect_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :409:{26,37}, :410:26, :411:{26,37}] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + s1_valid_dup_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s2_valid_dup_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s3_valid_dup_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s0_folded_gh_reg_dup_1_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_1_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_2_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_3_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s1_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s2_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s3_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s0_last_br_num_oh_reg_dup_1 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s0_last_br_num_oh_reg_dup_2 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s0_last_br_num_oh_reg_dup_3 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s1_last_br_num_oh_dup_1 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s1_last_br_num_oh_dup_2 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s1_last_br_num_oh_dup_3 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s2_last_br_num_oh_dup_1 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s2_last_br_num_oh_dup_2 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s2_last_br_num_oh_dup_3 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s3_last_br_num_oh_dup_1 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s3_last_br_num_oh_dup_2 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s3_last_br_num_oh_dup_3 <= 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + ghv_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_4 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_5 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_6 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_7 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_8 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_9 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_10 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_11 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_12 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_13 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_14 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_15 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_16 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_17 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_18 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_19 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_20 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_21 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_22 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_23 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_24 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_25 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_26 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_27 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_28 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_29 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_30 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_31 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_32 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_33 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_34 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_35 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_36 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_37 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_38 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_39 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_40 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_41 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_42 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_43 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_44 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_45 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_46 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_47 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_48 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_49 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_50 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_51 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_52 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_53 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_54 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_55 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_56 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_57 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_58 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_59 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_60 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_61 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_62 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_63 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_64 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_65 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_66 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_67 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_68 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_69 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_70 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_71 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_72 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_73 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_74 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_75 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_76 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_77 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_78 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_79 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_80 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_81 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_82 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_83 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_84 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_85 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_86 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_87 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_88 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_89 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_90 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_91 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_92 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_93 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_94 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_95 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_96 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_97 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_98 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_99 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_100 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_101 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_102 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_103 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_104 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_105 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_106 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_107 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_108 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_109 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_110 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_111 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_112 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_113 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_114 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_115 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_116 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_117 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_118 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_119 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_120 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_121 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_122 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_123 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_124 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_125 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_126 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_127 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_128 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_129 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_130 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_131 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_132 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_133 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_134 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_135 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_136 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_137 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_138 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_139 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_140 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_141 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_142 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_143 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_144 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_145 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_146 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_147 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_148 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_149 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_150 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_151 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_152 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_153 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_154 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_155 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_156 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_157 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_158 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_159 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_160 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_161 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_162 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_163 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_164 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_165 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_166 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_167 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_168 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_169 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_170 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_171 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_172 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_173 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_174 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_175 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_176 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_177 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_178 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_179 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_180 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_181 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_182 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_183 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_184 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_185 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_186 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_187 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_188 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_189 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_190 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_191 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_192 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_193 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_194 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_195 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_196 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_197 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_198 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_199 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_200 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_201 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_202 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_203 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_204 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_205 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_206 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_207 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_208 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_209 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_210 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_211 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_212 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_213 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_214 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_215 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_216 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_217 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_218 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_219 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_220 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_221 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_222 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_223 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_224 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_225 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_226 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_227 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_228 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_229 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_230 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_231 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_232 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_233 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_234 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_235 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_236 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_237 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_238 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_239 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_240 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_241 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_242 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_243 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_244 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_245 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_246 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_247 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_248 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_249 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_250 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_251 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_252 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_253 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_254 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_255 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + s0_ghist_ptr_reg_dup_0_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_0_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_1_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_1_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_2_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_2_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_3_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_3_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s1_ghist_ptr_dup_0_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_0_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_1_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_1_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_2_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_2_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_3_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_3_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s2_ghist_ptr_dup_0_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_0_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_1_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_1_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_2_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_2_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_3_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_3_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s3_ghist_ptr_dup_0_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_0_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_1_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_1_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_2_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_2_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_3_flag <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_3_value <= 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + do_redirect_dup_next_valid_last_r <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + previous_s1_pred_info_hit_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_target_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_2 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_3 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_lastBrPosOH_0_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_0_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_0_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_2 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_3 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_0_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_0_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_1_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_1_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_2_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_2_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_3_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_3_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_0 <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_1 <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_2 <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_3 <= 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s2_pred_pc_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_2 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_3 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_slot_valids_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_slot_valids_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_targets_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_targets_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_fallThroughAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_is_br_sharing <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_hit <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_slot_valids_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_slot_valids_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_targets_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_targets_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_fallThroughAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_is_br_sharing <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_hit <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_slot_valids_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_slot_valids_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_targets_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_targets_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_fallThroughAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_is_br_sharing <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_hit <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_slot_valids_0 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_slot_valids_1 <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_targets_0 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_targets_1 <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_fallThroughAddr <= 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_is_br_sharing <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_hit <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + predictors_io_update_valid_REG <= 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :728:40] end - else begin + else begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] s1_valid_dup_3 <= ~io_ftq_to_bpu_redirect_valid & (s0_fire_dup_3 @@ -10338,7 +10808,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (s0_fire_dup_1 | ~(s1_flush_dup_1 | s1_fire_dup_1 | io_ftq_to_bpu_redirect_valid) & (s0_fire_dup_0 | ~(s1_flush_dup_0 | s1_fire_dup_0) - & s1_valid_dup_3)))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :360:26, :367:36, :374:60, :383:{31,42}, :384:{31,42}, :385:{31,42}, :386:{31,42} + & s1_valid_dup_3)))); // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :361:26, :368:36, :375:60, :384:{31,42}, :385:{31,42}, :386:{31,42}, :387:{31,42}] s2_valid_dup_3 <= ~s2_flush_dup_3 & (s1_fire_dup_3 @@ -10350,7 +10820,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & (s1_fire_dup_1 ? ~s1_flush_dup_1 : ~(s2_valid_dup_3 | s2_flush_dup_0) & s1_fire_dup_0 - & ~s1_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :360:26, :374:60, :395:{26,37}, :396:{26,37,40}, :397:{26,37} + & ~s1_flush_dup_0))); // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :359:26, :361:26, :375:60, :396:{26,37}, :397:{26,37,40}, :398:{26,37}] s3_valid_dup_3 <= ~io_ftq_to_bpu_redirect_valid & (s2_valid_dup_3 @@ -10361,3980 +10831,3947 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 : ~_GEN_100 & (s2_valid_dup_3 ? ~s2_flush_dup_1 - : ~_GEN_100 & s2_valid_dup_3 & ~s2_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :383:{31,42}, :384:31, :408:{26,37}, :409:{26,37,40}, :410:{26,37} + : ~_GEN_100 & s2_valid_dup_3 & ~s2_flush_dup_0))); // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :359:26, :384:{31,42}, :385:31, :409:{26,37}, :410:{26,37,40}, :411:{26,37}] s0_folded_gh_reg_dup_1_hist_17_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_16_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_15_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_14_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_13_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_12_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_11_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_10_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_9_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_8_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_7_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_6_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_5_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_4_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_3_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_2_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_1_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_1_hist_0_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_17_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_16_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_15_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_14_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_13_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_12_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_11_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_10_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_9_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_8_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_7_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_6_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_5_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_4_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_3_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_2_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_1_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_2_hist_0_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_17_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_16_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_15_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_14_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_13_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_12_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_11_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_10_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_9_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_8_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_7_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_6_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_5_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_4_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_3_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_2_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_1_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_folded_gh_reg_dup_3_hist_0_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (s0_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (s0_fire_dup_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:368:36] s1_folded_gh_dup_1_hist_17_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_16_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_15_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_14_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_13_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_12_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_11_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_10_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_9_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_8_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_7_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_6_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_5_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_4_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_3_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_2_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_1_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_1_hist_0_folded_hist <= - _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_17_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_16_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_15_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_14_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_13_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_12_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_11_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_10_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_9_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_8_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_7_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_6_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_5_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_4_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_3_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_2_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_1_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_2_hist_0_folded_hist <= - _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_17_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_16_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_15_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_14_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_13_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_12_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_11_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_10_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_9_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_8_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_7_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_6_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_5_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_4_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_3_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_2_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_1_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_folded_gh_dup_3_hist_0_folded_hist <= - _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_last_br_num_oh_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_last_br_num_oh_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_last_br_num_oh_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_last_br_num_oh_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_last_br_num_oh_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_last_br_num_oh_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s1_ghist_ptr_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s1_ghist_ptr_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] end - if (s1_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - s2_folded_gh_dup_1_hist_17_folded_hist <= s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_16_folded_hist <= s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_15_folded_hist <= s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_14_folded_hist <= s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_13_folded_hist <= s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_12_folded_hist <= s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_11_folded_hist <= s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_10_folded_hist <= s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_9_folded_hist <= s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_8_folded_hist <= s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_7_folded_hist <= s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_6_folded_hist <= s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_5_folded_hist <= s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_4_folded_hist <= s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_3_folded_hist <= s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_2_folded_hist <= s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_1_folded_hist <= s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_1_hist_0_folded_hist <= s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_17_folded_hist <= s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_16_folded_hist <= s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_15_folded_hist <= s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_14_folded_hist <= s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_13_folded_hist <= s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_12_folded_hist <= s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_11_folded_hist <= s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_10_folded_hist <= s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_9_folded_hist <= s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_8_folded_hist <= s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_7_folded_hist <= s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_6_folded_hist <= s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_5_folded_hist <= s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_4_folded_hist <= s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_3_folded_hist <= s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_2_folded_hist <= s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_1_folded_hist <= s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_2_hist_0_folded_hist <= s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_17_folded_hist <= s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_16_folded_hist <= s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_15_folded_hist <= s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_14_folded_hist <= s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_13_folded_hist <= s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_12_folded_hist <= s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_11_folded_hist <= s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_10_folded_hist <= s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_9_folded_hist <= s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_8_folded_hist <= s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_7_folded_hist <= s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_6_folded_hist <= s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_5_folded_hist <= s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_4_folded_hist <= s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_3_folded_hist <= s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_2_folded_hist <= s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_1_folded_hist <= s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_folded_gh_dup_3_hist_0_folded_hist <= s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 - s2_last_br_num_oh_dup_1 <= s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 - s2_last_br_num_oh_dup_2 <= s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 - s2_last_br_num_oh_dup_3 <= s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 + if (s1_fire_dup_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + s2_folded_gh_dup_1_hist_17_folded_hist <= s1_folded_gh_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_16_folded_hist <= s1_folded_gh_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_15_folded_hist <= s1_folded_gh_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_14_folded_hist <= s1_folded_gh_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_13_folded_hist <= s1_folded_gh_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_12_folded_hist <= s1_folded_gh_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_11_folded_hist <= s1_folded_gh_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_10_folded_hist <= s1_folded_gh_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_9_folded_hist <= s1_folded_gh_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_8_folded_hist <= s1_folded_gh_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_7_folded_hist <= s1_folded_gh_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_6_folded_hist <= s1_folded_gh_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_5_folded_hist <= s1_folded_gh_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_4_folded_hist <= s1_folded_gh_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_3_folded_hist <= s1_folded_gh_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_2_folded_hist <= s1_folded_gh_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_1_folded_hist <= s1_folded_gh_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_1_hist_0_folded_hist <= s1_folded_gh_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_17_folded_hist <= s1_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_16_folded_hist <= s1_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_15_folded_hist <= s1_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_14_folded_hist <= s1_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_13_folded_hist <= s1_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_12_folded_hist <= s1_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_11_folded_hist <= s1_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_10_folded_hist <= s1_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_9_folded_hist <= s1_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_8_folded_hist <= s1_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_7_folded_hist <= s1_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_6_folded_hist <= s1_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_5_folded_hist <= s1_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_4_folded_hist <= s1_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_3_folded_hist <= s1_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_2_folded_hist <= s1_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_1_folded_hist <= s1_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_2_hist_0_folded_hist <= s1_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_17_folded_hist <= s1_folded_gh_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_16_folded_hist <= s1_folded_gh_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_15_folded_hist <= s1_folded_gh_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_14_folded_hist <= s1_folded_gh_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_13_folded_hist <= s1_folded_gh_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_12_folded_hist <= s1_folded_gh_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_11_folded_hist <= s1_folded_gh_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_10_folded_hist <= s1_folded_gh_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_9_folded_hist <= s1_folded_gh_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_8_folded_hist <= s1_folded_gh_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_7_folded_hist <= s1_folded_gh_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_6_folded_hist <= s1_folded_gh_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_5_folded_hist <= s1_folded_gh_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_4_folded_hist <= s1_folded_gh_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_3_folded_hist <= s1_folded_gh_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_2_folded_hist <= s1_folded_gh_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_1_folded_hist <= s1_folded_gh_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_folded_gh_dup_3_hist_0_folded_hist <= s1_folded_gh_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35] + s2_last_br_num_oh_dup_1 <= s1_last_br_num_oh_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40] + s2_last_br_num_oh_dup_2 <= s1_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40] + s2_last_br_num_oh_dup_3 <= s1_last_br_num_oh_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40] s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 - s2_ghist_ptr_dup_0_flag <= s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_0_value <= s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_1_flag <= s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_1_value <= s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_2_flag <= s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_2_value <= s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_3_flag <= s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 - s2_ghist_ptr_dup_3_value <= s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46] + s2_ghist_ptr_dup_0_flag <= s1_ghist_ptr_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_0_value <= s1_ghist_ptr_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_1_flag <= s1_ghist_ptr_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_1_value <= s1_ghist_ptr_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_2_flag <= s1_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_2_value <= s1_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_3_flag <= s1_ghist_ptr_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] + s2_ghist_ptr_dup_3_value <= s1_ghist_ptr_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35] end - if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - s3_folded_gh_dup_1_hist_17_folded_hist <= s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_16_folded_hist <= s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_15_folded_hist <= s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_14_folded_hist <= s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_13_folded_hist <= s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_12_folded_hist <= s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_11_folded_hist <= s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_10_folded_hist <= s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_9_folded_hist <= s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_8_folded_hist <= s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_7_folded_hist <= s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_6_folded_hist <= s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_5_folded_hist <= s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_4_folded_hist <= s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_3_folded_hist <= s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_2_folded_hist <= s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_1_folded_hist <= s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_1_hist_0_folded_hist <= s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_17_folded_hist <= s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_16_folded_hist <= s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_15_folded_hist <= s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_14_folded_hist <= s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_13_folded_hist <= s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_12_folded_hist <= s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_11_folded_hist <= s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_10_folded_hist <= s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_9_folded_hist <= s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_8_folded_hist <= s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_7_folded_hist <= s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_6_folded_hist <= s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_5_folded_hist <= s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_4_folded_hist <= s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_3_folded_hist <= s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_2_folded_hist <= s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_1_folded_hist <= s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_2_hist_0_folded_hist <= s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_17_folded_hist <= s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_16_folded_hist <= s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_15_folded_hist <= s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_14_folded_hist <= s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_13_folded_hist <= s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_12_folded_hist <= s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_11_folded_hist <= s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_10_folded_hist <= s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_9_folded_hist <= s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_8_folded_hist <= s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_7_folded_hist <= s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_6_folded_hist <= s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_5_folded_hist <= s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_4_folded_hist <= s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_3_folded_hist <= s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_2_folded_hist <= s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_1_folded_hist <= s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_folded_gh_dup_3_hist_0_folded_hist <= s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 - s3_last_br_num_oh_dup_1 <= s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 - s3_last_br_num_oh_dup_2 <= s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 - s3_last_br_num_oh_dup_3 <= s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 + if (s2_valid_dup_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + s3_folded_gh_dup_1_hist_17_folded_hist <= s2_folded_gh_dup_1_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_16_folded_hist <= s2_folded_gh_dup_1_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_15_folded_hist <= s2_folded_gh_dup_1_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_14_folded_hist <= s2_folded_gh_dup_1_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_13_folded_hist <= s2_folded_gh_dup_1_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_12_folded_hist <= s2_folded_gh_dup_1_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_11_folded_hist <= s2_folded_gh_dup_1_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_10_folded_hist <= s2_folded_gh_dup_1_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_9_folded_hist <= s2_folded_gh_dup_1_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_8_folded_hist <= s2_folded_gh_dup_1_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_7_folded_hist <= s2_folded_gh_dup_1_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_6_folded_hist <= s2_folded_gh_dup_1_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_5_folded_hist <= s2_folded_gh_dup_1_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_4_folded_hist <= s2_folded_gh_dup_1_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_3_folded_hist <= s2_folded_gh_dup_1_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_2_folded_hist <= s2_folded_gh_dup_1_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_1_folded_hist <= s2_folded_gh_dup_1_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_1_hist_0_folded_hist <= s2_folded_gh_dup_1_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_17_folded_hist <= s2_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_16_folded_hist <= s2_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_15_folded_hist <= s2_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_14_folded_hist <= s2_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_13_folded_hist <= s2_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_12_folded_hist <= s2_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_11_folded_hist <= s2_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_10_folded_hist <= s2_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_9_folded_hist <= s2_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_8_folded_hist <= s2_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_7_folded_hist <= s2_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_6_folded_hist <= s2_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_5_folded_hist <= s2_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_4_folded_hist <= s2_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_3_folded_hist <= s2_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_2_folded_hist <= s2_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_1_folded_hist <= s2_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_2_hist_0_folded_hist <= s2_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_17_folded_hist <= s2_folded_gh_dup_3_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_16_folded_hist <= s2_folded_gh_dup_3_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_15_folded_hist <= s2_folded_gh_dup_3_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_14_folded_hist <= s2_folded_gh_dup_3_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_13_folded_hist <= s2_folded_gh_dup_3_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_12_folded_hist <= s2_folded_gh_dup_3_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_11_folded_hist <= s2_folded_gh_dup_3_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_10_folded_hist <= s2_folded_gh_dup_3_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_9_folded_hist <= s2_folded_gh_dup_3_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_8_folded_hist <= s2_folded_gh_dup_3_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_7_folded_hist <= s2_folded_gh_dup_3_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_6_folded_hist <= s2_folded_gh_dup_3_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_5_folded_hist <= s2_folded_gh_dup_3_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_4_folded_hist <= s2_folded_gh_dup_3_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_3_folded_hist <= s2_folded_gh_dup_3_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_2_folded_hist <= s2_folded_gh_dup_3_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_1_folded_hist <= s2_folded_gh_dup_3_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_folded_gh_dup_3_hist_0_folded_hist <= s2_folded_gh_dup_3_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:288:35, :289:35] + s3_last_br_num_oh_dup_1 <= s2_last_br_num_oh_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40, :295:40] + s3_last_br_num_oh_dup_2 <= s2_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40, :295:40] + s3_last_br_num_oh_dup_3 <= s2_last_br_num_oh_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:294:40, :295:40] s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 - s3_ghist_ptr_dup_0_flag <= s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_0_value <= s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_1_flag <= s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_1_value <= s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_2_flag <= s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_2_value <= s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_3_flag <= s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - s3_ghist_ptr_dup_3_value <= s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 - previous_s2_pred_pc_0 <= _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_pc_1 <= _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_pc_2 <= _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_pc_3 <= _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:300:46, :301:46] + s3_ghist_ptr_dup_0_flag <= s2_ghist_ptr_dup_0_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_0_value <= s2_ghist_ptr_dup_0_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_1_flag <= s2_ghist_ptr_dup_1_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_1_value <= s2_ghist_ptr_dup_1_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_2_flag <= s2_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_2_value <= s2_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_3_flag <= s2_ghist_ptr_dup_3_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + s3_ghist_ptr_dup_3_value <= s2_ghist_ptr_dup_3_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:325:35, :326:35] + previous_s2_pred_pc_0 <= _predictors_io_out_s2_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_pc_1 <= _predictors_io_out_s2_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_pc_2 <= _predictors_io_out_s2_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_pc_3 <= _predictors_io_out_s2_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_br_taken_mask_0 <= - _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_br_taken_mask_1 <= - _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_slot_valids_0 <= - _predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_slot_valids_1 <= - _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_targets_0 <= - _predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_targets_1 <= - _predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_fallThroughAddr <= - _predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_0_is_br_sharing <= - _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_full_pred_0_hit <= _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_full_pred_0_hit <= _predictors_io_out_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_br_taken_mask_0 <= - _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_br_taken_mask_1 <= - _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_slot_valids_0 <= - _predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_slot_valids_1 <= - _predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_targets_0 <= - _predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_targets_1 <= - _predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_fallThroughAddr <= - _predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_1_is_br_sharing <= - _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_full_pred_1_hit <= _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_full_pred_1_hit <= _predictors_io_out_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_br_taken_mask_0 <= - _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_br_taken_mask_1 <= - _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_slot_valids_0 <= - _predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_slot_valids_1 <= - _predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_targets_0 <= - _predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_targets_1 <= - _predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_fallThroughAddr <= - _predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_2_is_br_sharing <= - _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_full_pred_2_hit <= _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_full_pred_2_hit <= _predictors_io_out_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_br_taken_mask_0 <= - _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_br_taken_mask_1 <= - _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_slot_valids_0 <= - _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_slot_valids_1 <= - _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_targets_0 <= - _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_targets_1 <= - _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_fallThroughAddr <= - _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] previous_s2_pred_full_pred_3_is_br_sharing <= - _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 - previous_s2_pred_full_pred_3_hit <= _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + _predictors_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] + previous_s2_pred_full_pred_3_hit <= _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :674:35] end - s0_last_br_num_oh_reg_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_last_br_num_oh_reg_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_last_br_num_oh_reg_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_last_br_num_oh_reg_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_last_br_num_oh_reg_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_last_br_num_oh_reg_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= - _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_0_T | _ghv_wens_0_T_1 | _ghv_wens_0_T_2 | _ghv_wens_0_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_0 <= _ghv_write_datas_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_1_T | _ghv_wens_1_T_1 | _ghv_wens_1_T_2 | _ghv_wens_1_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_1 <= _ghv_write_datas_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_2_T | _ghv_wens_2_T_1 | _ghv_wens_2_T_2 | _ghv_wens_2_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_2 <= _ghv_write_datas_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_3_T | _ghv_wens_3_T_1 | _ghv_wens_3_T_2 | _ghv_wens_3_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_3 <= _ghv_write_datas_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_4_T | _ghv_wens_4_T_1 | _ghv_wens_4_T_2 | _ghv_wens_4_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_4 <= _ghv_write_datas_4_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_5_T | _ghv_wens_5_T_1 | _ghv_wens_5_T_2 | _ghv_wens_5_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_5 <= _ghv_write_datas_5_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_6_T | _ghv_wens_6_T_1 | _ghv_wens_6_T_2 | _ghv_wens_6_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_6 <= _ghv_write_datas_6_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_7_T | _ghv_wens_7_T_1 | _ghv_wens_7_T_2 | _ghv_wens_7_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_7 <= _ghv_write_datas_7_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_8_T | _ghv_wens_8_T_1 | _ghv_wens_8_T_2 | _ghv_wens_8_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_8 <= _ghv_write_datas_8_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_9_T | _ghv_wens_9_T_1 | _ghv_wens_9_T_2 | _ghv_wens_9_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_9 <= _ghv_write_datas_9_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_10_T | _ghv_wens_10_T_1 | _ghv_wens_10_T_2 | _ghv_wens_10_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_10 <= _ghv_write_datas_10_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_11_T | _ghv_wens_11_T_1 | _ghv_wens_11_T_2 | _ghv_wens_11_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_11 <= _ghv_write_datas_11_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_12_T | _ghv_wens_12_T_1 | _ghv_wens_12_T_2 | _ghv_wens_12_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_12 <= _ghv_write_datas_12_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_13_T | _ghv_wens_13_T_1 | _ghv_wens_13_T_2 | _ghv_wens_13_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_13 <= _ghv_write_datas_13_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_14_T | _ghv_wens_14_T_1 | _ghv_wens_14_T_2 | _ghv_wens_14_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_14 <= _ghv_write_datas_14_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_15_T | _ghv_wens_15_T_1 | _ghv_wens_15_T_2 | _ghv_wens_15_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_15 <= _ghv_write_datas_15_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_16_T | _ghv_wens_16_T_1 | _ghv_wens_16_T_2 | _ghv_wens_16_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_16 <= _ghv_write_datas_16_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_17_T | _ghv_wens_17_T_1 | _ghv_wens_17_T_2 | _ghv_wens_17_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_17 <= _ghv_write_datas_17_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_18_T | _ghv_wens_18_T_1 | _ghv_wens_18_T_2 | _ghv_wens_18_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_18 <= _ghv_write_datas_18_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_19_T | _ghv_wens_19_T_1 | _ghv_wens_19_T_2 | _ghv_wens_19_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_19 <= _ghv_write_datas_19_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_20_T | _ghv_wens_20_T_1 | _ghv_wens_20_T_2 | _ghv_wens_20_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_20 <= _ghv_write_datas_20_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_21_T | _ghv_wens_21_T_1 | _ghv_wens_21_T_2 | _ghv_wens_21_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_21 <= _ghv_write_datas_21_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_22_T | _ghv_wens_22_T_1 | _ghv_wens_22_T_2 | _ghv_wens_22_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_22 <= _ghv_write_datas_22_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_23_T | _ghv_wens_23_T_1 | _ghv_wens_23_T_2 | _ghv_wens_23_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_23 <= _ghv_write_datas_23_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_24_T | _ghv_wens_24_T_1 | _ghv_wens_24_T_2 | _ghv_wens_24_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_24 <= _ghv_write_datas_24_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_25_T | _ghv_wens_25_T_1 | _ghv_wens_25_T_2 | _ghv_wens_25_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_25 <= _ghv_write_datas_25_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_26_T | _ghv_wens_26_T_1 | _ghv_wens_26_T_2 | _ghv_wens_26_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_26 <= _ghv_write_datas_26_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_27_T | _ghv_wens_27_T_1 | _ghv_wens_27_T_2 | _ghv_wens_27_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_27 <= _ghv_write_datas_27_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_28_T | _ghv_wens_28_T_1 | _ghv_wens_28_T_2 | _ghv_wens_28_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_28 <= _ghv_write_datas_28_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_29_T | _ghv_wens_29_T_1 | _ghv_wens_29_T_2 | _ghv_wens_29_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_29 <= _ghv_write_datas_29_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_30_T | _ghv_wens_30_T_1 | _ghv_wens_30_T_2 | _ghv_wens_30_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_30 <= _ghv_write_datas_30_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_31_T | _ghv_wens_31_T_1 | _ghv_wens_31_T_2 | _ghv_wens_31_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_31 <= _ghv_write_datas_31_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_32_T | _ghv_wens_32_T_1 | _ghv_wens_32_T_2 | _ghv_wens_32_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_32 <= _ghv_write_datas_32_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_33_T | _ghv_wens_33_T_1 | _ghv_wens_33_T_2 | _ghv_wens_33_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_33 <= _ghv_write_datas_33_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_34_T | _ghv_wens_34_T_1 | _ghv_wens_34_T_2 | _ghv_wens_34_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_34 <= _ghv_write_datas_34_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_35_T | _ghv_wens_35_T_1 | _ghv_wens_35_T_2 | _ghv_wens_35_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_35 <= _ghv_write_datas_35_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_36_T | _ghv_wens_36_T_1 | _ghv_wens_36_T_2 | _ghv_wens_36_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_36 <= _ghv_write_datas_36_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_37_T | _ghv_wens_37_T_1 | _ghv_wens_37_T_2 | _ghv_wens_37_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_37 <= _ghv_write_datas_37_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_38_T | _ghv_wens_38_T_1 | _ghv_wens_38_T_2 | _ghv_wens_38_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_38 <= _ghv_write_datas_38_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_39_T | _ghv_wens_39_T_1 | _ghv_wens_39_T_2 | _ghv_wens_39_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_39 <= _ghv_write_datas_39_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_40_T | _ghv_wens_40_T_1 | _ghv_wens_40_T_2 | _ghv_wens_40_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_40 <= _ghv_write_datas_40_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_41_T | _ghv_wens_41_T_1 | _ghv_wens_41_T_2 | _ghv_wens_41_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_41 <= _ghv_write_datas_41_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_42_T | _ghv_wens_42_T_1 | _ghv_wens_42_T_2 | _ghv_wens_42_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_42 <= _ghv_write_datas_42_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_43_T | _ghv_wens_43_T_1 | _ghv_wens_43_T_2 | _ghv_wens_43_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_43 <= _ghv_write_datas_43_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_44_T | _ghv_wens_44_T_1 | _ghv_wens_44_T_2 | _ghv_wens_44_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_44 <= _ghv_write_datas_44_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_45_T | _ghv_wens_45_T_1 | _ghv_wens_45_T_2 | _ghv_wens_45_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_45 <= _ghv_write_datas_45_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_46_T | _ghv_wens_46_T_1 | _ghv_wens_46_T_2 | _ghv_wens_46_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_46 <= _ghv_write_datas_46_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_47_T | _ghv_wens_47_T_1 | _ghv_wens_47_T_2 | _ghv_wens_47_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_47 <= _ghv_write_datas_47_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_48_T | _ghv_wens_48_T_1 | _ghv_wens_48_T_2 | _ghv_wens_48_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_48 <= _ghv_write_datas_48_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_49_T | _ghv_wens_49_T_1 | _ghv_wens_49_T_2 | _ghv_wens_49_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_49 <= _ghv_write_datas_49_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_50_T | _ghv_wens_50_T_1 | _ghv_wens_50_T_2 | _ghv_wens_50_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_50 <= _ghv_write_datas_50_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_51_T | _ghv_wens_51_T_1 | _ghv_wens_51_T_2 | _ghv_wens_51_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_51 <= _ghv_write_datas_51_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_52_T | _ghv_wens_52_T_1 | _ghv_wens_52_T_2 | _ghv_wens_52_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_52 <= _ghv_write_datas_52_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_53_T | _ghv_wens_53_T_1 | _ghv_wens_53_T_2 | _ghv_wens_53_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_53 <= _ghv_write_datas_53_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_54_T | _ghv_wens_54_T_1 | _ghv_wens_54_T_2 | _ghv_wens_54_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_54 <= _ghv_write_datas_54_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_55_T | _ghv_wens_55_T_1 | _ghv_wens_55_T_2 | _ghv_wens_55_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_55 <= _ghv_write_datas_55_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_56_T | _ghv_wens_56_T_1 | _ghv_wens_56_T_2 | _ghv_wens_56_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_56 <= _ghv_write_datas_56_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_57_T | _ghv_wens_57_T_1 | _ghv_wens_57_T_2 | _ghv_wens_57_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_57 <= _ghv_write_datas_57_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_58_T | _ghv_wens_58_T_1 | _ghv_wens_58_T_2 | _ghv_wens_58_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_58 <= _ghv_write_datas_58_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_59_T | _ghv_wens_59_T_1 | _ghv_wens_59_T_2 | _ghv_wens_59_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_59 <= _ghv_write_datas_59_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_60_T | _ghv_wens_60_T_1 | _ghv_wens_60_T_2 | _ghv_wens_60_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_60 <= _ghv_write_datas_60_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_61_T | _ghv_wens_61_T_1 | _ghv_wens_61_T_2 | _ghv_wens_61_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_61 <= _ghv_write_datas_61_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_62_T | _ghv_wens_62_T_1 | _ghv_wens_62_T_2 | _ghv_wens_62_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_62 <= _ghv_write_datas_62_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_63_T | _ghv_wens_63_T_1 | _ghv_wens_63_T_2 | _ghv_wens_63_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_63 <= _ghv_write_datas_63_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_64_T | _ghv_wens_64_T_1 | _ghv_wens_64_T_2 | _ghv_wens_64_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_64 <= _ghv_write_datas_64_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_65_T | _ghv_wens_65_T_1 | _ghv_wens_65_T_2 | _ghv_wens_65_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_65 <= _ghv_write_datas_65_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_66_T | _ghv_wens_66_T_1 | _ghv_wens_66_T_2 | _ghv_wens_66_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_66 <= _ghv_write_datas_66_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_67_T | _ghv_wens_67_T_1 | _ghv_wens_67_T_2 | _ghv_wens_67_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_67 <= _ghv_write_datas_67_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_68_T | _ghv_wens_68_T_1 | _ghv_wens_68_T_2 | _ghv_wens_68_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_68 <= _ghv_write_datas_68_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_69_T | _ghv_wens_69_T_1 | _ghv_wens_69_T_2 | _ghv_wens_69_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_69 <= _ghv_write_datas_69_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_70_T | _ghv_wens_70_T_1 | _ghv_wens_70_T_2 | _ghv_wens_70_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_70 <= _ghv_write_datas_70_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_71_T | _ghv_wens_71_T_1 | _ghv_wens_71_T_2 | _ghv_wens_71_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_71 <= _ghv_write_datas_71_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_72_T | _ghv_wens_72_T_1 | _ghv_wens_72_T_2 | _ghv_wens_72_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_72 <= _ghv_write_datas_72_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_73_T | _ghv_wens_73_T_1 | _ghv_wens_73_T_2 | _ghv_wens_73_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_73 <= _ghv_write_datas_73_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_74_T | _ghv_wens_74_T_1 | _ghv_wens_74_T_2 | _ghv_wens_74_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_74 <= _ghv_write_datas_74_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_75_T | _ghv_wens_75_T_1 | _ghv_wens_75_T_2 | _ghv_wens_75_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_75 <= _ghv_write_datas_75_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_76_T | _ghv_wens_76_T_1 | _ghv_wens_76_T_2 | _ghv_wens_76_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_76 <= _ghv_write_datas_76_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_77_T | _ghv_wens_77_T_1 | _ghv_wens_77_T_2 | _ghv_wens_77_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_77 <= _ghv_write_datas_77_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_78_T | _ghv_wens_78_T_1 | _ghv_wens_78_T_2 | _ghv_wens_78_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_78 <= _ghv_write_datas_78_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_79_T | _ghv_wens_79_T_1 | _ghv_wens_79_T_2 | _ghv_wens_79_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_79 <= _ghv_write_datas_79_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_80_T | _ghv_wens_80_T_1 | _ghv_wens_80_T_2 | _ghv_wens_80_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_80 <= _ghv_write_datas_80_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_81_T | _ghv_wens_81_T_1 | _ghv_wens_81_T_2 | _ghv_wens_81_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_81 <= _ghv_write_datas_81_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_82_T | _ghv_wens_82_T_1 | _ghv_wens_82_T_2 | _ghv_wens_82_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_82 <= _ghv_write_datas_82_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_83_T | _ghv_wens_83_T_1 | _ghv_wens_83_T_2 | _ghv_wens_83_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_83 <= _ghv_write_datas_83_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_84_T | _ghv_wens_84_T_1 | _ghv_wens_84_T_2 | _ghv_wens_84_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_84 <= _ghv_write_datas_84_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_85_T | _ghv_wens_85_T_1 | _ghv_wens_85_T_2 | _ghv_wens_85_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_85 <= _ghv_write_datas_85_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_86_T | _ghv_wens_86_T_1 | _ghv_wens_86_T_2 | _ghv_wens_86_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_86 <= _ghv_write_datas_86_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_87_T | _ghv_wens_87_T_1 | _ghv_wens_87_T_2 | _ghv_wens_87_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_87 <= _ghv_write_datas_87_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_88_T | _ghv_wens_88_T_1 | _ghv_wens_88_T_2 | _ghv_wens_88_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_88 <= _ghv_write_datas_88_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_89_T | _ghv_wens_89_T_1 | _ghv_wens_89_T_2 | _ghv_wens_89_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_89 <= _ghv_write_datas_89_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_90_T | _ghv_wens_90_T_1 | _ghv_wens_90_T_2 | _ghv_wens_90_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_90 <= _ghv_write_datas_90_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_91_T | _ghv_wens_91_T_1 | _ghv_wens_91_T_2 | _ghv_wens_91_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_91 <= _ghv_write_datas_91_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_92_T | _ghv_wens_92_T_1 | _ghv_wens_92_T_2 | _ghv_wens_92_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_92 <= _ghv_write_datas_92_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_93_T | _ghv_wens_93_T_1 | _ghv_wens_93_T_2 | _ghv_wens_93_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_93 <= _ghv_write_datas_93_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_94_T | _ghv_wens_94_T_1 | _ghv_wens_94_T_2 | _ghv_wens_94_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_94 <= _ghv_write_datas_94_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_95_T | _ghv_wens_95_T_1 | _ghv_wens_95_T_2 | _ghv_wens_95_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_95 <= _ghv_write_datas_95_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_96_T | _ghv_wens_96_T_1 | _ghv_wens_96_T_2 | _ghv_wens_96_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_96 <= _ghv_write_datas_96_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_97_T | _ghv_wens_97_T_1 | _ghv_wens_97_T_2 | _ghv_wens_97_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_97 <= _ghv_write_datas_97_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_98_T | _ghv_wens_98_T_1 | _ghv_wens_98_T_2 | _ghv_wens_98_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_98 <= _ghv_write_datas_98_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_99_T | _ghv_wens_99_T_1 | _ghv_wens_99_T_2 | _ghv_wens_99_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_99 <= _ghv_write_datas_99_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_100_T | _ghv_wens_100_T_1 | _ghv_wens_100_T_2 | _ghv_wens_100_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_100 <= _ghv_write_datas_100_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_101_T | _ghv_wens_101_T_1 | _ghv_wens_101_T_2 | _ghv_wens_101_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_101 <= _ghv_write_datas_101_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_102_T | _ghv_wens_102_T_1 | _ghv_wens_102_T_2 | _ghv_wens_102_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_102 <= _ghv_write_datas_102_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_103_T | _ghv_wens_103_T_1 | _ghv_wens_103_T_2 | _ghv_wens_103_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_103 <= _ghv_write_datas_103_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_104_T | _ghv_wens_104_T_1 | _ghv_wens_104_T_2 | _ghv_wens_104_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_104 <= _ghv_write_datas_104_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_105_T | _ghv_wens_105_T_1 | _ghv_wens_105_T_2 | _ghv_wens_105_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_105 <= _ghv_write_datas_105_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_106_T | _ghv_wens_106_T_1 | _ghv_wens_106_T_2 | _ghv_wens_106_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_106 <= _ghv_write_datas_106_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_107_T | _ghv_wens_107_T_1 | _ghv_wens_107_T_2 | _ghv_wens_107_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_107 <= _ghv_write_datas_107_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_108_T | _ghv_wens_108_T_1 | _ghv_wens_108_T_2 | _ghv_wens_108_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_108 <= _ghv_write_datas_108_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_109_T | _ghv_wens_109_T_1 | _ghv_wens_109_T_2 | _ghv_wens_109_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_109 <= _ghv_write_datas_109_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_110_T | _ghv_wens_110_T_1 | _ghv_wens_110_T_2 | _ghv_wens_110_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_110 <= _ghv_write_datas_110_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_111_T | _ghv_wens_111_T_1 | _ghv_wens_111_T_2 | _ghv_wens_111_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_111 <= _ghv_write_datas_111_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_112_T | _ghv_wens_112_T_1 | _ghv_wens_112_T_2 | _ghv_wens_112_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_112 <= _ghv_write_datas_112_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_113_T | _ghv_wens_113_T_1 | _ghv_wens_113_T_2 | _ghv_wens_113_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_113 <= _ghv_write_datas_113_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_114_T | _ghv_wens_114_T_1 | _ghv_wens_114_T_2 | _ghv_wens_114_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_114 <= _ghv_write_datas_114_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_115_T | _ghv_wens_115_T_1 | _ghv_wens_115_T_2 | _ghv_wens_115_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_115 <= _ghv_write_datas_115_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_116_T | _ghv_wens_116_T_1 | _ghv_wens_116_T_2 | _ghv_wens_116_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_116 <= _ghv_write_datas_116_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_117_T | _ghv_wens_117_T_1 | _ghv_wens_117_T_2 | _ghv_wens_117_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_117 <= _ghv_write_datas_117_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_118_T | _ghv_wens_118_T_1 | _ghv_wens_118_T_2 | _ghv_wens_118_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_118 <= _ghv_write_datas_118_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_119_T | _ghv_wens_119_T_1 | _ghv_wens_119_T_2 | _ghv_wens_119_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_119 <= _ghv_write_datas_119_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_120_T | _ghv_wens_120_T_1 | _ghv_wens_120_T_2 | _ghv_wens_120_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_120 <= _ghv_write_datas_120_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_121_T | _ghv_wens_121_T_1 | _ghv_wens_121_T_2 | _ghv_wens_121_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_121 <= _ghv_write_datas_121_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_122_T | _ghv_wens_122_T_1 | _ghv_wens_122_T_2 | _ghv_wens_122_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_122 <= _ghv_write_datas_122_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_123_T | _ghv_wens_123_T_1 | _ghv_wens_123_T_2 | _ghv_wens_123_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_123 <= _ghv_write_datas_123_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_124_T | _ghv_wens_124_T_1 | _ghv_wens_124_T_2 | _ghv_wens_124_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_124 <= _ghv_write_datas_124_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_125_T | _ghv_wens_125_T_1 | _ghv_wens_125_T_2 | _ghv_wens_125_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_125 <= _ghv_write_datas_125_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_126_T | _ghv_wens_126_T_1 | _ghv_wens_126_T_2 | _ghv_wens_126_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_126 <= _ghv_write_datas_126_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_127_T | _ghv_wens_127_T_1 | _ghv_wens_127_T_2 | _ghv_wens_127_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_127 <= _ghv_write_datas_127_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_128_T | _ghv_wens_128_T_1 | _ghv_wens_128_T_2 | _ghv_wens_128_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_128 <= _ghv_write_datas_128_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_129_T | _ghv_wens_129_T_1 | _ghv_wens_129_T_2 | _ghv_wens_129_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_129 <= _ghv_write_datas_129_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_130_T | _ghv_wens_130_T_1 | _ghv_wens_130_T_2 | _ghv_wens_130_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_130 <= _ghv_write_datas_130_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_131_T | _ghv_wens_131_T_1 | _ghv_wens_131_T_2 | _ghv_wens_131_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_131 <= _ghv_write_datas_131_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_132_T | _ghv_wens_132_T_1 | _ghv_wens_132_T_2 | _ghv_wens_132_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_132 <= _ghv_write_datas_132_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_133_T | _ghv_wens_133_T_1 | _ghv_wens_133_T_2 | _ghv_wens_133_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_133 <= _ghv_write_datas_133_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_134_T | _ghv_wens_134_T_1 | _ghv_wens_134_T_2 | _ghv_wens_134_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_134 <= _ghv_write_datas_134_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_135_T | _ghv_wens_135_T_1 | _ghv_wens_135_T_2 | _ghv_wens_135_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_135 <= _ghv_write_datas_135_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_136_T | _ghv_wens_136_T_1 | _ghv_wens_136_T_2 | _ghv_wens_136_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_136 <= _ghv_write_datas_136_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_137_T | _ghv_wens_137_T_1 | _ghv_wens_137_T_2 | _ghv_wens_137_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_137 <= _ghv_write_datas_137_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_138_T | _ghv_wens_138_T_1 | _ghv_wens_138_T_2 | _ghv_wens_138_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_138 <= _ghv_write_datas_138_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_139_T | _ghv_wens_139_T_1 | _ghv_wens_139_T_2 | _ghv_wens_139_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_139 <= _ghv_write_datas_139_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_140_T | _ghv_wens_140_T_1 | _ghv_wens_140_T_2 | _ghv_wens_140_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_140 <= _ghv_write_datas_140_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_141_T | _ghv_wens_141_T_1 | _ghv_wens_141_T_2 | _ghv_wens_141_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_141 <= _ghv_write_datas_141_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_142_T | _ghv_wens_142_T_1 | _ghv_wens_142_T_2 | _ghv_wens_142_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_142 <= _ghv_write_datas_142_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_143_T | _ghv_wens_143_T_1 | _ghv_wens_143_T_2 | _ghv_wens_143_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_143 <= _ghv_write_datas_143_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_144_T | _ghv_wens_144_T_1 | _ghv_wens_144_T_2 | _ghv_wens_144_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_144 <= _ghv_write_datas_144_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_145_T | _ghv_wens_145_T_1 | _ghv_wens_145_T_2 | _ghv_wens_145_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_145 <= _ghv_write_datas_145_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_146_T | _ghv_wens_146_T_1 | _ghv_wens_146_T_2 | _ghv_wens_146_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_146 <= _ghv_write_datas_146_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_147_T | _ghv_wens_147_T_1 | _ghv_wens_147_T_2 | _ghv_wens_147_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_147 <= _ghv_write_datas_147_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_148_T | _ghv_wens_148_T_1 | _ghv_wens_148_T_2 | _ghv_wens_148_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_148 <= _ghv_write_datas_148_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_149_T | _ghv_wens_149_T_1 | _ghv_wens_149_T_2 | _ghv_wens_149_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_149 <= _ghv_write_datas_149_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_150_T | _ghv_wens_150_T_1 | _ghv_wens_150_T_2 | _ghv_wens_150_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_150 <= _ghv_write_datas_150_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_151_T | _ghv_wens_151_T_1 | _ghv_wens_151_T_2 | _ghv_wens_151_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_151 <= _ghv_write_datas_151_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_152_T | _ghv_wens_152_T_1 | _ghv_wens_152_T_2 | _ghv_wens_152_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_152 <= _ghv_write_datas_152_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_153_T | _ghv_wens_153_T_1 | _ghv_wens_153_T_2 | _ghv_wens_153_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_153 <= _ghv_write_datas_153_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_154_T | _ghv_wens_154_T_1 | _ghv_wens_154_T_2 | _ghv_wens_154_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_154 <= _ghv_write_datas_154_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_155_T | _ghv_wens_155_T_1 | _ghv_wens_155_T_2 | _ghv_wens_155_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_155 <= _ghv_write_datas_155_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_156_T | _ghv_wens_156_T_1 | _ghv_wens_156_T_2 | _ghv_wens_156_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_156 <= _ghv_write_datas_156_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_157_T | _ghv_wens_157_T_1 | _ghv_wens_157_T_2 | _ghv_wens_157_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_157 <= _ghv_write_datas_157_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_158_T | _ghv_wens_158_T_1 | _ghv_wens_158_T_2 | _ghv_wens_158_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_158 <= _ghv_write_datas_158_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_159_T | _ghv_wens_159_T_1 | _ghv_wens_159_T_2 | _ghv_wens_159_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_159 <= _ghv_write_datas_159_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_160_T | _ghv_wens_160_T_1 | _ghv_wens_160_T_2 | _ghv_wens_160_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_160 <= _ghv_write_datas_160_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_161_T | _ghv_wens_161_T_1 | _ghv_wens_161_T_2 | _ghv_wens_161_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_161 <= _ghv_write_datas_161_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_162_T | _ghv_wens_162_T_1 | _ghv_wens_162_T_2 | _ghv_wens_162_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_162 <= _ghv_write_datas_162_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_163_T | _ghv_wens_163_T_1 | _ghv_wens_163_T_2 | _ghv_wens_163_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_163 <= _ghv_write_datas_163_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_164_T | _ghv_wens_164_T_1 | _ghv_wens_164_T_2 | _ghv_wens_164_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_164 <= _ghv_write_datas_164_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_165_T | _ghv_wens_165_T_1 | _ghv_wens_165_T_2 | _ghv_wens_165_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_165 <= _ghv_write_datas_165_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_166_T | _ghv_wens_166_T_1 | _ghv_wens_166_T_2 | _ghv_wens_166_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_166 <= _ghv_write_datas_166_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_167_T | _ghv_wens_167_T_1 | _ghv_wens_167_T_2 | _ghv_wens_167_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_167 <= _ghv_write_datas_167_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_168_T | _ghv_wens_168_T_1 | _ghv_wens_168_T_2 | _ghv_wens_168_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_168 <= _ghv_write_datas_168_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_169_T | _ghv_wens_169_T_1 | _ghv_wens_169_T_2 | _ghv_wens_169_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_169 <= _ghv_write_datas_169_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_170_T | _ghv_wens_170_T_1 | _ghv_wens_170_T_2 | _ghv_wens_170_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_170 <= _ghv_write_datas_170_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_171_T | _ghv_wens_171_T_1 | _ghv_wens_171_T_2 | _ghv_wens_171_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_171 <= _ghv_write_datas_171_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_172_T | _ghv_wens_172_T_1 | _ghv_wens_172_T_2 | _ghv_wens_172_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_172 <= _ghv_write_datas_172_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_173_T | _ghv_wens_173_T_1 | _ghv_wens_173_T_2 | _ghv_wens_173_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_173 <= _ghv_write_datas_173_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_174_T | _ghv_wens_174_T_1 | _ghv_wens_174_T_2 | _ghv_wens_174_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_174 <= _ghv_write_datas_174_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_175_T | _ghv_wens_175_T_1 | _ghv_wens_175_T_2 | _ghv_wens_175_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_175 <= _ghv_write_datas_175_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_176_T | _ghv_wens_176_T_1 | _ghv_wens_176_T_2 | _ghv_wens_176_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_176 <= _ghv_write_datas_176_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_177_T | _ghv_wens_177_T_1 | _ghv_wens_177_T_2 | _ghv_wens_177_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_177 <= _ghv_write_datas_177_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_178_T | _ghv_wens_178_T_1 | _ghv_wens_178_T_2 | _ghv_wens_178_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_178 <= _ghv_write_datas_178_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_179_T | _ghv_wens_179_T_1 | _ghv_wens_179_T_2 | _ghv_wens_179_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_179 <= _ghv_write_datas_179_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_180_T | _ghv_wens_180_T_1 | _ghv_wens_180_T_2 | _ghv_wens_180_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_180 <= _ghv_write_datas_180_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_181_T | _ghv_wens_181_T_1 | _ghv_wens_181_T_2 | _ghv_wens_181_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_181 <= _ghv_write_datas_181_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_182_T | _ghv_wens_182_T_1 | _ghv_wens_182_T_2 | _ghv_wens_182_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_182 <= _ghv_write_datas_182_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_183_T | _ghv_wens_183_T_1 | _ghv_wens_183_T_2 | _ghv_wens_183_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_183 <= _ghv_write_datas_183_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_184_T | _ghv_wens_184_T_1 | _ghv_wens_184_T_2 | _ghv_wens_184_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_184 <= _ghv_write_datas_184_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_185_T | _ghv_wens_185_T_1 | _ghv_wens_185_T_2 | _ghv_wens_185_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_185 <= _ghv_write_datas_185_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_186_T | _ghv_wens_186_T_1 | _ghv_wens_186_T_2 | _ghv_wens_186_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_186 <= _ghv_write_datas_186_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_187_T | _ghv_wens_187_T_1 | _ghv_wens_187_T_2 | _ghv_wens_187_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_187 <= _ghv_write_datas_187_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_188_T | _ghv_wens_188_T_1 | _ghv_wens_188_T_2 | _ghv_wens_188_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_188 <= _ghv_write_datas_188_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_189_T | _ghv_wens_189_T_1 | _ghv_wens_189_T_2 | _ghv_wens_189_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_189 <= _ghv_write_datas_189_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_190_T | _ghv_wens_190_T_1 | _ghv_wens_190_T_2 | _ghv_wens_190_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_190 <= _ghv_write_datas_190_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_191_T | _ghv_wens_191_T_1 | _ghv_wens_191_T_2 | _ghv_wens_191_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_191 <= _ghv_write_datas_191_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_192_T | _ghv_wens_192_T_1 | _ghv_wens_192_T_2 | _ghv_wens_192_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_192 <= _ghv_write_datas_192_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_193_T | _ghv_wens_193_T_1 | _ghv_wens_193_T_2 | _ghv_wens_193_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_193 <= _ghv_write_datas_193_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_194_T | _ghv_wens_194_T_1 | _ghv_wens_194_T_2 | _ghv_wens_194_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_194 <= _ghv_write_datas_194_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_195_T | _ghv_wens_195_T_1 | _ghv_wens_195_T_2 | _ghv_wens_195_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_195 <= _ghv_write_datas_195_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_196_T | _ghv_wens_196_T_1 | _ghv_wens_196_T_2 | _ghv_wens_196_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_196 <= _ghv_write_datas_196_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_197_T | _ghv_wens_197_T_1 | _ghv_wens_197_T_2 | _ghv_wens_197_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_197 <= _ghv_write_datas_197_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_198_T | _ghv_wens_198_T_1 | _ghv_wens_198_T_2 | _ghv_wens_198_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_198 <= _ghv_write_datas_198_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_199_T | _ghv_wens_199_T_1 | _ghv_wens_199_T_2 | _ghv_wens_199_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_199 <= _ghv_write_datas_199_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_200_T | _ghv_wens_200_T_1 | _ghv_wens_200_T_2 | _ghv_wens_200_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_200 <= _ghv_write_datas_200_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_201_T | _ghv_wens_201_T_1 | _ghv_wens_201_T_2 | _ghv_wens_201_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_201 <= _ghv_write_datas_201_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_202_T | _ghv_wens_202_T_1 | _ghv_wens_202_T_2 | _ghv_wens_202_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_202 <= _ghv_write_datas_202_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_203_T | _ghv_wens_203_T_1 | _ghv_wens_203_T_2 | _ghv_wens_203_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_203 <= _ghv_write_datas_203_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_204_T | _ghv_wens_204_T_1 | _ghv_wens_204_T_2 | _ghv_wens_204_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_204 <= _ghv_write_datas_204_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_205_T | _ghv_wens_205_T_1 | _ghv_wens_205_T_2 | _ghv_wens_205_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_205 <= _ghv_write_datas_205_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_206_T | _ghv_wens_206_T_1 | _ghv_wens_206_T_2 | _ghv_wens_206_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_206 <= _ghv_write_datas_206_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_207_T | _ghv_wens_207_T_1 | _ghv_wens_207_T_2 | _ghv_wens_207_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_207 <= _ghv_write_datas_207_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_208_T | _ghv_wens_208_T_1 | _ghv_wens_208_T_2 | _ghv_wens_208_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_208 <= _ghv_write_datas_208_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_209_T | _ghv_wens_209_T_1 | _ghv_wens_209_T_2 | _ghv_wens_209_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_209 <= _ghv_write_datas_209_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_210_T | _ghv_wens_210_T_1 | _ghv_wens_210_T_2 | _ghv_wens_210_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_210 <= _ghv_write_datas_210_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_211_T | _ghv_wens_211_T_1 | _ghv_wens_211_T_2 | _ghv_wens_211_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_211 <= _ghv_write_datas_211_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_212_T | _ghv_wens_212_T_1 | _ghv_wens_212_T_2 | _ghv_wens_212_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_212 <= _ghv_write_datas_212_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_213_T | _ghv_wens_213_T_1 | _ghv_wens_213_T_2 | _ghv_wens_213_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_213 <= _ghv_write_datas_213_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_214_T | _ghv_wens_214_T_1 | _ghv_wens_214_T_2 | _ghv_wens_214_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_214 <= _ghv_write_datas_214_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_215_T | _ghv_wens_215_T_1 | _ghv_wens_215_T_2 | _ghv_wens_215_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_215 <= _ghv_write_datas_215_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_216_T | _ghv_wens_216_T_1 | _ghv_wens_216_T_2 | _ghv_wens_216_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_216 <= _ghv_write_datas_216_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_217_T | _ghv_wens_217_T_1 | _ghv_wens_217_T_2 | _ghv_wens_217_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_217 <= _ghv_write_datas_217_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_218_T | _ghv_wens_218_T_1 | _ghv_wens_218_T_2 | _ghv_wens_218_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_218 <= _ghv_write_datas_218_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_219_T | _ghv_wens_219_T_1 | _ghv_wens_219_T_2 | _ghv_wens_219_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_219 <= _ghv_write_datas_219_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_220_T | _ghv_wens_220_T_1 | _ghv_wens_220_T_2 | _ghv_wens_220_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_220 <= _ghv_write_datas_220_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_221_T | _ghv_wens_221_T_1 | _ghv_wens_221_T_2 | _ghv_wens_221_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_221 <= _ghv_write_datas_221_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_222_T | _ghv_wens_222_T_1 | _ghv_wens_222_T_2 | _ghv_wens_222_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_222 <= _ghv_write_datas_222_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_223_T | _ghv_wens_223_T_1 | _ghv_wens_223_T_2 | _ghv_wens_223_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_223 <= _ghv_write_datas_223_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_224_T | _ghv_wens_224_T_1 | _ghv_wens_224_T_2 | _ghv_wens_224_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_224 <= _ghv_write_datas_224_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_225_T | _ghv_wens_225_T_1 | _ghv_wens_225_T_2 | _ghv_wens_225_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_225 <= _ghv_write_datas_225_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_226_T | _ghv_wens_226_T_1 | _ghv_wens_226_T_2 | _ghv_wens_226_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_226 <= _ghv_write_datas_226_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_227_T | _ghv_wens_227_T_1 | _ghv_wens_227_T_2 | _ghv_wens_227_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_227 <= _ghv_write_datas_227_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_228_T | _ghv_wens_228_T_1 | _ghv_wens_228_T_2 | _ghv_wens_228_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_228 <= _ghv_write_datas_228_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_229_T | _ghv_wens_229_T_1 | _ghv_wens_229_T_2 | _ghv_wens_229_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_229 <= _ghv_write_datas_229_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_230_T | _ghv_wens_230_T_1 | _ghv_wens_230_T_2 | _ghv_wens_230_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_230 <= _ghv_write_datas_230_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_231_T | _ghv_wens_231_T_1 | _ghv_wens_231_T_2 | _ghv_wens_231_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_231 <= _ghv_write_datas_231_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_232_T | _ghv_wens_232_T_1 | _ghv_wens_232_T_2 | _ghv_wens_232_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_232 <= _ghv_write_datas_232_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_233_T | _ghv_wens_233_T_1 | _ghv_wens_233_T_2 | _ghv_wens_233_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_233 <= _ghv_write_datas_233_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_234_T | _ghv_wens_234_T_1 | _ghv_wens_234_T_2 | _ghv_wens_234_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_234 <= _ghv_write_datas_234_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_235_T | _ghv_wens_235_T_1 | _ghv_wens_235_T_2 | _ghv_wens_235_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_235 <= _ghv_write_datas_235_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_236_T | _ghv_wens_236_T_1 | _ghv_wens_236_T_2 | _ghv_wens_236_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_236 <= _ghv_write_datas_236_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_237_T | _ghv_wens_237_T_1 | _ghv_wens_237_T_2 | _ghv_wens_237_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_237 <= _ghv_write_datas_237_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_238_T | _ghv_wens_238_T_1 | _ghv_wens_238_T_2 | _ghv_wens_238_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_238 <= _ghv_write_datas_238_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_239_T | _ghv_wens_239_T_1 | _ghv_wens_239_T_2 | _ghv_wens_239_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_239 <= _ghv_write_datas_239_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_240_T | _ghv_wens_240_T_1 | _ghv_wens_240_T_2 | _ghv_wens_240_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_240 <= _ghv_write_datas_240_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_241_T | _ghv_wens_241_T_1 | _ghv_wens_241_T_2 | _ghv_wens_241_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_241 <= _ghv_write_datas_241_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_242_T | _ghv_wens_242_T_1 | _ghv_wens_242_T_2 | _ghv_wens_242_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_242 <= _ghv_write_datas_242_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_243_T | _ghv_wens_243_T_1 | _ghv_wens_243_T_2 | _ghv_wens_243_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_243 <= _ghv_write_datas_243_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_244_T | _ghv_wens_244_T_1 | _ghv_wens_244_T_2 | _ghv_wens_244_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_244 <= _ghv_write_datas_244_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_245_T | _ghv_wens_245_T_1 | _ghv_wens_245_T_2 | _ghv_wens_245_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_245 <= _ghv_write_datas_245_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_246_T | _ghv_wens_246_T_1 | _ghv_wens_246_T_2 | _ghv_wens_246_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_246 <= _ghv_write_datas_246_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_247_T | _ghv_wens_247_T_1 | _ghv_wens_247_T_2 | _ghv_wens_247_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_247 <= _ghv_write_datas_247_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_248_T | _ghv_wens_248_T_1 | _ghv_wens_248_T_2 | _ghv_wens_248_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_248 <= _ghv_write_datas_248_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_249_T | _ghv_wens_249_T_1 | _ghv_wens_249_T_2 | _ghv_wens_249_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_249 <= _ghv_write_datas_249_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_250_T | _ghv_wens_250_T_1 | _ghv_wens_250_T_2 | _ghv_wens_250_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_250 <= _ghv_write_datas_250_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_251_T | _ghv_wens_251_T_1 | _ghv_wens_251_T_2 | _ghv_wens_251_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_251 <= _ghv_write_datas_251_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_252_T | _ghv_wens_252_T_1 | _ghv_wens_252_T_2 | _ghv_wens_252_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_252 <= _ghv_write_datas_252_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_253_T | _ghv_wens_253_T_1 | _ghv_wens_253_T_2 | _ghv_wens_253_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_253 <= _ghv_write_datas_253_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_254_T | _ghv_wens_254_T_1 | _ghv_wens_254_T_2 | _ghv_wens_254_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_254 <= _ghv_write_datas_254_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - if (_ghv_wens_255_T | _ghv_wens_255_T_1 | _ghv_wens_255_T_2 | _ghv_wens_255_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 - ghv_255 <= _ghv_write_datas_255_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_ghist_ptr_reg_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - do_redirect_dup_3_valid <= io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_level <= io_ftq_to_bpu_redirect_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_pc <= io_ftq_to_bpu_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isCall <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRet <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_ssp <= io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_sctr <= io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_value <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_value <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_flag <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_value <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_value <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_target <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_taken <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - thisBrNumOH_dup_shiftAmount <= io_ftq_to_bpu_redirect_bits_cfiUpdate_shift; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - do_redirect_dup_3_bits_cfiUpdate_addIntoHist <= - io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - previous_s1_pred_info_hit_0 <= _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 - previous_s1_pred_info_hit_1 <= _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 - previous_s1_pred_info_hit_2 <= _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 - previous_s1_pred_info_hit_3 <= _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_0_T | _ghv_wens_0_T_1 | _ghv_wens_0_T_2 | _ghv_wens_0_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_0 <= _ghv_write_datas_0_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_1_T | _ghv_wens_1_T_1 | _ghv_wens_1_T_2 | _ghv_wens_1_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_1 <= _ghv_write_datas_1_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_2_T | _ghv_wens_2_T_1 | _ghv_wens_2_T_2 | _ghv_wens_2_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_2 <= _ghv_write_datas_2_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_3_T | _ghv_wens_3_T_1 | _ghv_wens_3_T_2 | _ghv_wens_3_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_3 <= _ghv_write_datas_3_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_4_T | _ghv_wens_4_T_1 | _ghv_wens_4_T_2 | _ghv_wens_4_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_4 <= _ghv_write_datas_4_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_5_T | _ghv_wens_5_T_1 | _ghv_wens_5_T_2 | _ghv_wens_5_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_5 <= _ghv_write_datas_5_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_6_T | _ghv_wens_6_T_1 | _ghv_wens_6_T_2 | _ghv_wens_6_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_6 <= _ghv_write_datas_6_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_7_T | _ghv_wens_7_T_1 | _ghv_wens_7_T_2 | _ghv_wens_7_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_7 <= _ghv_write_datas_7_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_8_T | _ghv_wens_8_T_1 | _ghv_wens_8_T_2 | _ghv_wens_8_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_8 <= _ghv_write_datas_8_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_9_T | _ghv_wens_9_T_1 | _ghv_wens_9_T_2 | _ghv_wens_9_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_9 <= _ghv_write_datas_9_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_10_T | _ghv_wens_10_T_1 | _ghv_wens_10_T_2 | _ghv_wens_10_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_10 <= _ghv_write_datas_10_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_11_T | _ghv_wens_11_T_1 | _ghv_wens_11_T_2 | _ghv_wens_11_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_11 <= _ghv_write_datas_11_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_12_T | _ghv_wens_12_T_1 | _ghv_wens_12_T_2 | _ghv_wens_12_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_12 <= _ghv_write_datas_12_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_13_T | _ghv_wens_13_T_1 | _ghv_wens_13_T_2 | _ghv_wens_13_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_13 <= _ghv_write_datas_13_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_14_T | _ghv_wens_14_T_1 | _ghv_wens_14_T_2 | _ghv_wens_14_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_14 <= _ghv_write_datas_14_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_15_T | _ghv_wens_15_T_1 | _ghv_wens_15_T_2 | _ghv_wens_15_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_15 <= _ghv_write_datas_15_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_16_T | _ghv_wens_16_T_1 | _ghv_wens_16_T_2 | _ghv_wens_16_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_16 <= _ghv_write_datas_16_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_17_T | _ghv_wens_17_T_1 | _ghv_wens_17_T_2 | _ghv_wens_17_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_17 <= _ghv_write_datas_17_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_18_T | _ghv_wens_18_T_1 | _ghv_wens_18_T_2 | _ghv_wens_18_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_18 <= _ghv_write_datas_18_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_19_T | _ghv_wens_19_T_1 | _ghv_wens_19_T_2 | _ghv_wens_19_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_19 <= _ghv_write_datas_19_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_20_T | _ghv_wens_20_T_1 | _ghv_wens_20_T_2 | _ghv_wens_20_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_20 <= _ghv_write_datas_20_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_21_T | _ghv_wens_21_T_1 | _ghv_wens_21_T_2 | _ghv_wens_21_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_21 <= _ghv_write_datas_21_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_22_T | _ghv_wens_22_T_1 | _ghv_wens_22_T_2 | _ghv_wens_22_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_22 <= _ghv_write_datas_22_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_23_T | _ghv_wens_23_T_1 | _ghv_wens_23_T_2 | _ghv_wens_23_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_23 <= _ghv_write_datas_23_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_24_T | _ghv_wens_24_T_1 | _ghv_wens_24_T_2 | _ghv_wens_24_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_24 <= _ghv_write_datas_24_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_25_T | _ghv_wens_25_T_1 | _ghv_wens_25_T_2 | _ghv_wens_25_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_25 <= _ghv_write_datas_25_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_26_T | _ghv_wens_26_T_1 | _ghv_wens_26_T_2 | _ghv_wens_26_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_26 <= _ghv_write_datas_26_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_27_T | _ghv_wens_27_T_1 | _ghv_wens_27_T_2 | _ghv_wens_27_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_27 <= _ghv_write_datas_27_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_28_T | _ghv_wens_28_T_1 | _ghv_wens_28_T_2 | _ghv_wens_28_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_28 <= _ghv_write_datas_28_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_29_T | _ghv_wens_29_T_1 | _ghv_wens_29_T_2 | _ghv_wens_29_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_29 <= _ghv_write_datas_29_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_30_T | _ghv_wens_30_T_1 | _ghv_wens_30_T_2 | _ghv_wens_30_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_30 <= _ghv_write_datas_30_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_31_T | _ghv_wens_31_T_1 | _ghv_wens_31_T_2 | _ghv_wens_31_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_31 <= _ghv_write_datas_31_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_32_T | _ghv_wens_32_T_1 | _ghv_wens_32_T_2 | _ghv_wens_32_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_32 <= _ghv_write_datas_32_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_33_T | _ghv_wens_33_T_1 | _ghv_wens_33_T_2 | _ghv_wens_33_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_33 <= _ghv_write_datas_33_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_34_T | _ghv_wens_34_T_1 | _ghv_wens_34_T_2 | _ghv_wens_34_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_34 <= _ghv_write_datas_34_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_35_T | _ghv_wens_35_T_1 | _ghv_wens_35_T_2 | _ghv_wens_35_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_35 <= _ghv_write_datas_35_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_36_T | _ghv_wens_36_T_1 | _ghv_wens_36_T_2 | _ghv_wens_36_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_36 <= _ghv_write_datas_36_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_37_T | _ghv_wens_37_T_1 | _ghv_wens_37_T_2 | _ghv_wens_37_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_37 <= _ghv_write_datas_37_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_38_T | _ghv_wens_38_T_1 | _ghv_wens_38_T_2 | _ghv_wens_38_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_38 <= _ghv_write_datas_38_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_39_T | _ghv_wens_39_T_1 | _ghv_wens_39_T_2 | _ghv_wens_39_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_39 <= _ghv_write_datas_39_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_40_T | _ghv_wens_40_T_1 | _ghv_wens_40_T_2 | _ghv_wens_40_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_40 <= _ghv_write_datas_40_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_41_T | _ghv_wens_41_T_1 | _ghv_wens_41_T_2 | _ghv_wens_41_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_41 <= _ghv_write_datas_41_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_42_T | _ghv_wens_42_T_1 | _ghv_wens_42_T_2 | _ghv_wens_42_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_42 <= _ghv_write_datas_42_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_43_T | _ghv_wens_43_T_1 | _ghv_wens_43_T_2 | _ghv_wens_43_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_43 <= _ghv_write_datas_43_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_44_T | _ghv_wens_44_T_1 | _ghv_wens_44_T_2 | _ghv_wens_44_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_44 <= _ghv_write_datas_44_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_45_T | _ghv_wens_45_T_1 | _ghv_wens_45_T_2 | _ghv_wens_45_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_45 <= _ghv_write_datas_45_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_46_T | _ghv_wens_46_T_1 | _ghv_wens_46_T_2 | _ghv_wens_46_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_46 <= _ghv_write_datas_46_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_47_T | _ghv_wens_47_T_1 | _ghv_wens_47_T_2 | _ghv_wens_47_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_47 <= _ghv_write_datas_47_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_48_T | _ghv_wens_48_T_1 | _ghv_wens_48_T_2 | _ghv_wens_48_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_48 <= _ghv_write_datas_48_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_49_T | _ghv_wens_49_T_1 | _ghv_wens_49_T_2 | _ghv_wens_49_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_49 <= _ghv_write_datas_49_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_50_T | _ghv_wens_50_T_1 | _ghv_wens_50_T_2 | _ghv_wens_50_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_50 <= _ghv_write_datas_50_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_51_T | _ghv_wens_51_T_1 | _ghv_wens_51_T_2 | _ghv_wens_51_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_51 <= _ghv_write_datas_51_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_52_T | _ghv_wens_52_T_1 | _ghv_wens_52_T_2 | _ghv_wens_52_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_52 <= _ghv_write_datas_52_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_53_T | _ghv_wens_53_T_1 | _ghv_wens_53_T_2 | _ghv_wens_53_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_53 <= _ghv_write_datas_53_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_54_T | _ghv_wens_54_T_1 | _ghv_wens_54_T_2 | _ghv_wens_54_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_54 <= _ghv_write_datas_54_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_55_T | _ghv_wens_55_T_1 | _ghv_wens_55_T_2 | _ghv_wens_55_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_55 <= _ghv_write_datas_55_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_56_T | _ghv_wens_56_T_1 | _ghv_wens_56_T_2 | _ghv_wens_56_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_56 <= _ghv_write_datas_56_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_57_T | _ghv_wens_57_T_1 | _ghv_wens_57_T_2 | _ghv_wens_57_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_57 <= _ghv_write_datas_57_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_58_T | _ghv_wens_58_T_1 | _ghv_wens_58_T_2 | _ghv_wens_58_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_58 <= _ghv_write_datas_58_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_59_T | _ghv_wens_59_T_1 | _ghv_wens_59_T_2 | _ghv_wens_59_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_59 <= _ghv_write_datas_59_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_60_T | _ghv_wens_60_T_1 | _ghv_wens_60_T_2 | _ghv_wens_60_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_60 <= _ghv_write_datas_60_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_61_T | _ghv_wens_61_T_1 | _ghv_wens_61_T_2 | _ghv_wens_61_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_61 <= _ghv_write_datas_61_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_62_T | _ghv_wens_62_T_1 | _ghv_wens_62_T_2 | _ghv_wens_62_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_62 <= _ghv_write_datas_62_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_63_T | _ghv_wens_63_T_1 | _ghv_wens_63_T_2 | _ghv_wens_63_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_63 <= _ghv_write_datas_63_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_64_T | _ghv_wens_64_T_1 | _ghv_wens_64_T_2 | _ghv_wens_64_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_64 <= _ghv_write_datas_64_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_65_T | _ghv_wens_65_T_1 | _ghv_wens_65_T_2 | _ghv_wens_65_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_65 <= _ghv_write_datas_65_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_66_T | _ghv_wens_66_T_1 | _ghv_wens_66_T_2 | _ghv_wens_66_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_66 <= _ghv_write_datas_66_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_67_T | _ghv_wens_67_T_1 | _ghv_wens_67_T_2 | _ghv_wens_67_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_67 <= _ghv_write_datas_67_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_68_T | _ghv_wens_68_T_1 | _ghv_wens_68_T_2 | _ghv_wens_68_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_68 <= _ghv_write_datas_68_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_69_T | _ghv_wens_69_T_1 | _ghv_wens_69_T_2 | _ghv_wens_69_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_69 <= _ghv_write_datas_69_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_70_T | _ghv_wens_70_T_1 | _ghv_wens_70_T_2 | _ghv_wens_70_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_70 <= _ghv_write_datas_70_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_71_T | _ghv_wens_71_T_1 | _ghv_wens_71_T_2 | _ghv_wens_71_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_71 <= _ghv_write_datas_71_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_72_T | _ghv_wens_72_T_1 | _ghv_wens_72_T_2 | _ghv_wens_72_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_72 <= _ghv_write_datas_72_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_73_T | _ghv_wens_73_T_1 | _ghv_wens_73_T_2 | _ghv_wens_73_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_73 <= _ghv_write_datas_73_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_74_T | _ghv_wens_74_T_1 | _ghv_wens_74_T_2 | _ghv_wens_74_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_74 <= _ghv_write_datas_74_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_75_T | _ghv_wens_75_T_1 | _ghv_wens_75_T_2 | _ghv_wens_75_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_75 <= _ghv_write_datas_75_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_76_T | _ghv_wens_76_T_1 | _ghv_wens_76_T_2 | _ghv_wens_76_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_76 <= _ghv_write_datas_76_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_77_T | _ghv_wens_77_T_1 | _ghv_wens_77_T_2 | _ghv_wens_77_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_77 <= _ghv_write_datas_77_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_78_T | _ghv_wens_78_T_1 | _ghv_wens_78_T_2 | _ghv_wens_78_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_78 <= _ghv_write_datas_78_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_79_T | _ghv_wens_79_T_1 | _ghv_wens_79_T_2 | _ghv_wens_79_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_79 <= _ghv_write_datas_79_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_80_T | _ghv_wens_80_T_1 | _ghv_wens_80_T_2 | _ghv_wens_80_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_80 <= _ghv_write_datas_80_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_81_T | _ghv_wens_81_T_1 | _ghv_wens_81_T_2 | _ghv_wens_81_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_81 <= _ghv_write_datas_81_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_82_T | _ghv_wens_82_T_1 | _ghv_wens_82_T_2 | _ghv_wens_82_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_82 <= _ghv_write_datas_82_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_83_T | _ghv_wens_83_T_1 | _ghv_wens_83_T_2 | _ghv_wens_83_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_83 <= _ghv_write_datas_83_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_84_T | _ghv_wens_84_T_1 | _ghv_wens_84_T_2 | _ghv_wens_84_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_84 <= _ghv_write_datas_84_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_85_T | _ghv_wens_85_T_1 | _ghv_wens_85_T_2 | _ghv_wens_85_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_85 <= _ghv_write_datas_85_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_86_T | _ghv_wens_86_T_1 | _ghv_wens_86_T_2 | _ghv_wens_86_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_86 <= _ghv_write_datas_86_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_87_T | _ghv_wens_87_T_1 | _ghv_wens_87_T_2 | _ghv_wens_87_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_87 <= _ghv_write_datas_87_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_88_T | _ghv_wens_88_T_1 | _ghv_wens_88_T_2 | _ghv_wens_88_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_88 <= _ghv_write_datas_88_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_89_T | _ghv_wens_89_T_1 | _ghv_wens_89_T_2 | _ghv_wens_89_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_89 <= _ghv_write_datas_89_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_90_T | _ghv_wens_90_T_1 | _ghv_wens_90_T_2 | _ghv_wens_90_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_90 <= _ghv_write_datas_90_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_91_T | _ghv_wens_91_T_1 | _ghv_wens_91_T_2 | _ghv_wens_91_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_91 <= _ghv_write_datas_91_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_92_T | _ghv_wens_92_T_1 | _ghv_wens_92_T_2 | _ghv_wens_92_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_92 <= _ghv_write_datas_92_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_93_T | _ghv_wens_93_T_1 | _ghv_wens_93_T_2 | _ghv_wens_93_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_93 <= _ghv_write_datas_93_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_94_T | _ghv_wens_94_T_1 | _ghv_wens_94_T_2 | _ghv_wens_94_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_94 <= _ghv_write_datas_94_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_95_T | _ghv_wens_95_T_1 | _ghv_wens_95_T_2 | _ghv_wens_95_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_95 <= _ghv_write_datas_95_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_96_T | _ghv_wens_96_T_1 | _ghv_wens_96_T_2 | _ghv_wens_96_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_96 <= _ghv_write_datas_96_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_97_T | _ghv_wens_97_T_1 | _ghv_wens_97_T_2 | _ghv_wens_97_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_97 <= _ghv_write_datas_97_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_98_T | _ghv_wens_98_T_1 | _ghv_wens_98_T_2 | _ghv_wens_98_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_98 <= _ghv_write_datas_98_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_99_T | _ghv_wens_99_T_1 | _ghv_wens_99_T_2 | _ghv_wens_99_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_99 <= _ghv_write_datas_99_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_100_T | _ghv_wens_100_T_1 | _ghv_wens_100_T_2 | _ghv_wens_100_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_100 <= _ghv_write_datas_100_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_101_T | _ghv_wens_101_T_1 | _ghv_wens_101_T_2 | _ghv_wens_101_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_101 <= _ghv_write_datas_101_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_102_T | _ghv_wens_102_T_1 | _ghv_wens_102_T_2 | _ghv_wens_102_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_102 <= _ghv_write_datas_102_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_103_T | _ghv_wens_103_T_1 | _ghv_wens_103_T_2 | _ghv_wens_103_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_103 <= _ghv_write_datas_103_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_104_T | _ghv_wens_104_T_1 | _ghv_wens_104_T_2 | _ghv_wens_104_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_104 <= _ghv_write_datas_104_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_105_T | _ghv_wens_105_T_1 | _ghv_wens_105_T_2 | _ghv_wens_105_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_105 <= _ghv_write_datas_105_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_106_T | _ghv_wens_106_T_1 | _ghv_wens_106_T_2 | _ghv_wens_106_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_106 <= _ghv_write_datas_106_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_107_T | _ghv_wens_107_T_1 | _ghv_wens_107_T_2 | _ghv_wens_107_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_107 <= _ghv_write_datas_107_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_108_T | _ghv_wens_108_T_1 | _ghv_wens_108_T_2 | _ghv_wens_108_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_108 <= _ghv_write_datas_108_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_109_T | _ghv_wens_109_T_1 | _ghv_wens_109_T_2 | _ghv_wens_109_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_109 <= _ghv_write_datas_109_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_110_T | _ghv_wens_110_T_1 | _ghv_wens_110_T_2 | _ghv_wens_110_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_110 <= _ghv_write_datas_110_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_111_T | _ghv_wens_111_T_1 | _ghv_wens_111_T_2 | _ghv_wens_111_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_111 <= _ghv_write_datas_111_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_112_T | _ghv_wens_112_T_1 | _ghv_wens_112_T_2 | _ghv_wens_112_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_112 <= _ghv_write_datas_112_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_113_T | _ghv_wens_113_T_1 | _ghv_wens_113_T_2 | _ghv_wens_113_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_113 <= _ghv_write_datas_113_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_114_T | _ghv_wens_114_T_1 | _ghv_wens_114_T_2 | _ghv_wens_114_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_114 <= _ghv_write_datas_114_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_115_T | _ghv_wens_115_T_1 | _ghv_wens_115_T_2 | _ghv_wens_115_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_115 <= _ghv_write_datas_115_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_116_T | _ghv_wens_116_T_1 | _ghv_wens_116_T_2 | _ghv_wens_116_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_116 <= _ghv_write_datas_116_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_117_T | _ghv_wens_117_T_1 | _ghv_wens_117_T_2 | _ghv_wens_117_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_117 <= _ghv_write_datas_117_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_118_T | _ghv_wens_118_T_1 | _ghv_wens_118_T_2 | _ghv_wens_118_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_118 <= _ghv_write_datas_118_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_119_T | _ghv_wens_119_T_1 | _ghv_wens_119_T_2 | _ghv_wens_119_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_119 <= _ghv_write_datas_119_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_120_T | _ghv_wens_120_T_1 | _ghv_wens_120_T_2 | _ghv_wens_120_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_120 <= _ghv_write_datas_120_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_121_T | _ghv_wens_121_T_1 | _ghv_wens_121_T_2 | _ghv_wens_121_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_121 <= _ghv_write_datas_121_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_122_T | _ghv_wens_122_T_1 | _ghv_wens_122_T_2 | _ghv_wens_122_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_122 <= _ghv_write_datas_122_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_123_T | _ghv_wens_123_T_1 | _ghv_wens_123_T_2 | _ghv_wens_123_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_123 <= _ghv_write_datas_123_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_124_T | _ghv_wens_124_T_1 | _ghv_wens_124_T_2 | _ghv_wens_124_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_124 <= _ghv_write_datas_124_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_125_T | _ghv_wens_125_T_1 | _ghv_wens_125_T_2 | _ghv_wens_125_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_125 <= _ghv_write_datas_125_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_126_T | _ghv_wens_126_T_1 | _ghv_wens_126_T_2 | _ghv_wens_126_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_126 <= _ghv_write_datas_126_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_127_T | _ghv_wens_127_T_1 | _ghv_wens_127_T_2 | _ghv_wens_127_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_127 <= _ghv_write_datas_127_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_128_T | _ghv_wens_128_T_1 | _ghv_wens_128_T_2 | _ghv_wens_128_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_128 <= _ghv_write_datas_128_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_129_T | _ghv_wens_129_T_1 | _ghv_wens_129_T_2 | _ghv_wens_129_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_129 <= _ghv_write_datas_129_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_130_T | _ghv_wens_130_T_1 | _ghv_wens_130_T_2 | _ghv_wens_130_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_130 <= _ghv_write_datas_130_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_131_T | _ghv_wens_131_T_1 | _ghv_wens_131_T_2 | _ghv_wens_131_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_131 <= _ghv_write_datas_131_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_132_T | _ghv_wens_132_T_1 | _ghv_wens_132_T_2 | _ghv_wens_132_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_132 <= _ghv_write_datas_132_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_133_T | _ghv_wens_133_T_1 | _ghv_wens_133_T_2 | _ghv_wens_133_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_133 <= _ghv_write_datas_133_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_134_T | _ghv_wens_134_T_1 | _ghv_wens_134_T_2 | _ghv_wens_134_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_134 <= _ghv_write_datas_134_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_135_T | _ghv_wens_135_T_1 | _ghv_wens_135_T_2 | _ghv_wens_135_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_135 <= _ghv_write_datas_135_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_136_T | _ghv_wens_136_T_1 | _ghv_wens_136_T_2 | _ghv_wens_136_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_136 <= _ghv_write_datas_136_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_137_T | _ghv_wens_137_T_1 | _ghv_wens_137_T_2 | _ghv_wens_137_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_137 <= _ghv_write_datas_137_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_138_T | _ghv_wens_138_T_1 | _ghv_wens_138_T_2 | _ghv_wens_138_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_138 <= _ghv_write_datas_138_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_139_T | _ghv_wens_139_T_1 | _ghv_wens_139_T_2 | _ghv_wens_139_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_139 <= _ghv_write_datas_139_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_140_T | _ghv_wens_140_T_1 | _ghv_wens_140_T_2 | _ghv_wens_140_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_140 <= _ghv_write_datas_140_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_141_T | _ghv_wens_141_T_1 | _ghv_wens_141_T_2 | _ghv_wens_141_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_141 <= _ghv_write_datas_141_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_142_T | _ghv_wens_142_T_1 | _ghv_wens_142_T_2 | _ghv_wens_142_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_142 <= _ghv_write_datas_142_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_143_T | _ghv_wens_143_T_1 | _ghv_wens_143_T_2 | _ghv_wens_143_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_143 <= _ghv_write_datas_143_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_144_T | _ghv_wens_144_T_1 | _ghv_wens_144_T_2 | _ghv_wens_144_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_144 <= _ghv_write_datas_144_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_145_T | _ghv_wens_145_T_1 | _ghv_wens_145_T_2 | _ghv_wens_145_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_145 <= _ghv_write_datas_145_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_146_T | _ghv_wens_146_T_1 | _ghv_wens_146_T_2 | _ghv_wens_146_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_146 <= _ghv_write_datas_146_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_147_T | _ghv_wens_147_T_1 | _ghv_wens_147_T_2 | _ghv_wens_147_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_147 <= _ghv_write_datas_147_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_148_T | _ghv_wens_148_T_1 | _ghv_wens_148_T_2 | _ghv_wens_148_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_148 <= _ghv_write_datas_148_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_149_T | _ghv_wens_149_T_1 | _ghv_wens_149_T_2 | _ghv_wens_149_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_149 <= _ghv_write_datas_149_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_150_T | _ghv_wens_150_T_1 | _ghv_wens_150_T_2 | _ghv_wens_150_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_150 <= _ghv_write_datas_150_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_151_T | _ghv_wens_151_T_1 | _ghv_wens_151_T_2 | _ghv_wens_151_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_151 <= _ghv_write_datas_151_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_152_T | _ghv_wens_152_T_1 | _ghv_wens_152_T_2 | _ghv_wens_152_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_152 <= _ghv_write_datas_152_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_153_T | _ghv_wens_153_T_1 | _ghv_wens_153_T_2 | _ghv_wens_153_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_153 <= _ghv_write_datas_153_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_154_T | _ghv_wens_154_T_1 | _ghv_wens_154_T_2 | _ghv_wens_154_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_154 <= _ghv_write_datas_154_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_155_T | _ghv_wens_155_T_1 | _ghv_wens_155_T_2 | _ghv_wens_155_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_155 <= _ghv_write_datas_155_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_156_T | _ghv_wens_156_T_1 | _ghv_wens_156_T_2 | _ghv_wens_156_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_156 <= _ghv_write_datas_156_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_157_T | _ghv_wens_157_T_1 | _ghv_wens_157_T_2 | _ghv_wens_157_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_157 <= _ghv_write_datas_157_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_158_T | _ghv_wens_158_T_1 | _ghv_wens_158_T_2 | _ghv_wens_158_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_158 <= _ghv_write_datas_158_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_159_T | _ghv_wens_159_T_1 | _ghv_wens_159_T_2 | _ghv_wens_159_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_159 <= _ghv_write_datas_159_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_160_T | _ghv_wens_160_T_1 | _ghv_wens_160_T_2 | _ghv_wens_160_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_160 <= _ghv_write_datas_160_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_161_T | _ghv_wens_161_T_1 | _ghv_wens_161_T_2 | _ghv_wens_161_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_161 <= _ghv_write_datas_161_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_162_T | _ghv_wens_162_T_1 | _ghv_wens_162_T_2 | _ghv_wens_162_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_162 <= _ghv_write_datas_162_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_163_T | _ghv_wens_163_T_1 | _ghv_wens_163_T_2 | _ghv_wens_163_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_163 <= _ghv_write_datas_163_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_164_T | _ghv_wens_164_T_1 | _ghv_wens_164_T_2 | _ghv_wens_164_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_164 <= _ghv_write_datas_164_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_165_T | _ghv_wens_165_T_1 | _ghv_wens_165_T_2 | _ghv_wens_165_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_165 <= _ghv_write_datas_165_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_166_T | _ghv_wens_166_T_1 | _ghv_wens_166_T_2 | _ghv_wens_166_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_166 <= _ghv_write_datas_166_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_167_T | _ghv_wens_167_T_1 | _ghv_wens_167_T_2 | _ghv_wens_167_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_167 <= _ghv_write_datas_167_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_168_T | _ghv_wens_168_T_1 | _ghv_wens_168_T_2 | _ghv_wens_168_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_168 <= _ghv_write_datas_168_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_169_T | _ghv_wens_169_T_1 | _ghv_wens_169_T_2 | _ghv_wens_169_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_169 <= _ghv_write_datas_169_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_170_T | _ghv_wens_170_T_1 | _ghv_wens_170_T_2 | _ghv_wens_170_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_170 <= _ghv_write_datas_170_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_171_T | _ghv_wens_171_T_1 | _ghv_wens_171_T_2 | _ghv_wens_171_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_171 <= _ghv_write_datas_171_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_172_T | _ghv_wens_172_T_1 | _ghv_wens_172_T_2 | _ghv_wens_172_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_172 <= _ghv_write_datas_172_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_173_T | _ghv_wens_173_T_1 | _ghv_wens_173_T_2 | _ghv_wens_173_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_173 <= _ghv_write_datas_173_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_174_T | _ghv_wens_174_T_1 | _ghv_wens_174_T_2 | _ghv_wens_174_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_174 <= _ghv_write_datas_174_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_175_T | _ghv_wens_175_T_1 | _ghv_wens_175_T_2 | _ghv_wens_175_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_175 <= _ghv_write_datas_175_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_176_T | _ghv_wens_176_T_1 | _ghv_wens_176_T_2 | _ghv_wens_176_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_176 <= _ghv_write_datas_176_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_177_T | _ghv_wens_177_T_1 | _ghv_wens_177_T_2 | _ghv_wens_177_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_177 <= _ghv_write_datas_177_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_178_T | _ghv_wens_178_T_1 | _ghv_wens_178_T_2 | _ghv_wens_178_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_178 <= _ghv_write_datas_178_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_179_T | _ghv_wens_179_T_1 | _ghv_wens_179_T_2 | _ghv_wens_179_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_179 <= _ghv_write_datas_179_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_180_T | _ghv_wens_180_T_1 | _ghv_wens_180_T_2 | _ghv_wens_180_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_180 <= _ghv_write_datas_180_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_181_T | _ghv_wens_181_T_1 | _ghv_wens_181_T_2 | _ghv_wens_181_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_181 <= _ghv_write_datas_181_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_182_T | _ghv_wens_182_T_1 | _ghv_wens_182_T_2 | _ghv_wens_182_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_182 <= _ghv_write_datas_182_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_183_T | _ghv_wens_183_T_1 | _ghv_wens_183_T_2 | _ghv_wens_183_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_183 <= _ghv_write_datas_183_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_184_T | _ghv_wens_184_T_1 | _ghv_wens_184_T_2 | _ghv_wens_184_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_184 <= _ghv_write_datas_184_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_185_T | _ghv_wens_185_T_1 | _ghv_wens_185_T_2 | _ghv_wens_185_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_185 <= _ghv_write_datas_185_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_186_T | _ghv_wens_186_T_1 | _ghv_wens_186_T_2 | _ghv_wens_186_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_186 <= _ghv_write_datas_186_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_187_T | _ghv_wens_187_T_1 | _ghv_wens_187_T_2 | _ghv_wens_187_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_187 <= _ghv_write_datas_187_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_188_T | _ghv_wens_188_T_1 | _ghv_wens_188_T_2 | _ghv_wens_188_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_188 <= _ghv_write_datas_188_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_189_T | _ghv_wens_189_T_1 | _ghv_wens_189_T_2 | _ghv_wens_189_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_189 <= _ghv_write_datas_189_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_190_T | _ghv_wens_190_T_1 | _ghv_wens_190_T_2 | _ghv_wens_190_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_190 <= _ghv_write_datas_190_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_191_T | _ghv_wens_191_T_1 | _ghv_wens_191_T_2 | _ghv_wens_191_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_191 <= _ghv_write_datas_191_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_192_T | _ghv_wens_192_T_1 | _ghv_wens_192_T_2 | _ghv_wens_192_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_192 <= _ghv_write_datas_192_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_193_T | _ghv_wens_193_T_1 | _ghv_wens_193_T_2 | _ghv_wens_193_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_193 <= _ghv_write_datas_193_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_194_T | _ghv_wens_194_T_1 | _ghv_wens_194_T_2 | _ghv_wens_194_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_194 <= _ghv_write_datas_194_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_195_T | _ghv_wens_195_T_1 | _ghv_wens_195_T_2 | _ghv_wens_195_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_195 <= _ghv_write_datas_195_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_196_T | _ghv_wens_196_T_1 | _ghv_wens_196_T_2 | _ghv_wens_196_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_196 <= _ghv_write_datas_196_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_197_T | _ghv_wens_197_T_1 | _ghv_wens_197_T_2 | _ghv_wens_197_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_197 <= _ghv_write_datas_197_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_198_T | _ghv_wens_198_T_1 | _ghv_wens_198_T_2 | _ghv_wens_198_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_198 <= _ghv_write_datas_198_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_199_T | _ghv_wens_199_T_1 | _ghv_wens_199_T_2 | _ghv_wens_199_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_199 <= _ghv_write_datas_199_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_200_T | _ghv_wens_200_T_1 | _ghv_wens_200_T_2 | _ghv_wens_200_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_200 <= _ghv_write_datas_200_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_201_T | _ghv_wens_201_T_1 | _ghv_wens_201_T_2 | _ghv_wens_201_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_201 <= _ghv_write_datas_201_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_202_T | _ghv_wens_202_T_1 | _ghv_wens_202_T_2 | _ghv_wens_202_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_202 <= _ghv_write_datas_202_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_203_T | _ghv_wens_203_T_1 | _ghv_wens_203_T_2 | _ghv_wens_203_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_203 <= _ghv_write_datas_203_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_204_T | _ghv_wens_204_T_1 | _ghv_wens_204_T_2 | _ghv_wens_204_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_204 <= _ghv_write_datas_204_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_205_T | _ghv_wens_205_T_1 | _ghv_wens_205_T_2 | _ghv_wens_205_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_205 <= _ghv_write_datas_205_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_206_T | _ghv_wens_206_T_1 | _ghv_wens_206_T_2 | _ghv_wens_206_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_206 <= _ghv_write_datas_206_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_207_T | _ghv_wens_207_T_1 | _ghv_wens_207_T_2 | _ghv_wens_207_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_207 <= _ghv_write_datas_207_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_208_T | _ghv_wens_208_T_1 | _ghv_wens_208_T_2 | _ghv_wens_208_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_208 <= _ghv_write_datas_208_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_209_T | _ghv_wens_209_T_1 | _ghv_wens_209_T_2 | _ghv_wens_209_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_209 <= _ghv_write_datas_209_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_210_T | _ghv_wens_210_T_1 | _ghv_wens_210_T_2 | _ghv_wens_210_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_210 <= _ghv_write_datas_210_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_211_T | _ghv_wens_211_T_1 | _ghv_wens_211_T_2 | _ghv_wens_211_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_211 <= _ghv_write_datas_211_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_212_T | _ghv_wens_212_T_1 | _ghv_wens_212_T_2 | _ghv_wens_212_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_212 <= _ghv_write_datas_212_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_213_T | _ghv_wens_213_T_1 | _ghv_wens_213_T_2 | _ghv_wens_213_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_213 <= _ghv_write_datas_213_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_214_T | _ghv_wens_214_T_1 | _ghv_wens_214_T_2 | _ghv_wens_214_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_214 <= _ghv_write_datas_214_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_215_T | _ghv_wens_215_T_1 | _ghv_wens_215_T_2 | _ghv_wens_215_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_215 <= _ghv_write_datas_215_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_216_T | _ghv_wens_216_T_1 | _ghv_wens_216_T_2 | _ghv_wens_216_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_216 <= _ghv_write_datas_216_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_217_T | _ghv_wens_217_T_1 | _ghv_wens_217_T_2 | _ghv_wens_217_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_217 <= _ghv_write_datas_217_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_218_T | _ghv_wens_218_T_1 | _ghv_wens_218_T_2 | _ghv_wens_218_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_218 <= _ghv_write_datas_218_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_219_T | _ghv_wens_219_T_1 | _ghv_wens_219_T_2 | _ghv_wens_219_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_219 <= _ghv_write_datas_219_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_220_T | _ghv_wens_220_T_1 | _ghv_wens_220_T_2 | _ghv_wens_220_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_220 <= _ghv_write_datas_220_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_221_T | _ghv_wens_221_T_1 | _ghv_wens_221_T_2 | _ghv_wens_221_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_221 <= _ghv_write_datas_221_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_222_T | _ghv_wens_222_T_1 | _ghv_wens_222_T_2 | _ghv_wens_222_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_222 <= _ghv_write_datas_222_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_223_T | _ghv_wens_223_T_1 | _ghv_wens_223_T_2 | _ghv_wens_223_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_223 <= _ghv_write_datas_223_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_224_T | _ghv_wens_224_T_1 | _ghv_wens_224_T_2 | _ghv_wens_224_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_224 <= _ghv_write_datas_224_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_225_T | _ghv_wens_225_T_1 | _ghv_wens_225_T_2 | _ghv_wens_225_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_225 <= _ghv_write_datas_225_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_226_T | _ghv_wens_226_T_1 | _ghv_wens_226_T_2 | _ghv_wens_226_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_226 <= _ghv_write_datas_226_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_227_T | _ghv_wens_227_T_1 | _ghv_wens_227_T_2 | _ghv_wens_227_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_227 <= _ghv_write_datas_227_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_228_T | _ghv_wens_228_T_1 | _ghv_wens_228_T_2 | _ghv_wens_228_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_228 <= _ghv_write_datas_228_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_229_T | _ghv_wens_229_T_1 | _ghv_wens_229_T_2 | _ghv_wens_229_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_229 <= _ghv_write_datas_229_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_230_T | _ghv_wens_230_T_1 | _ghv_wens_230_T_2 | _ghv_wens_230_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_230 <= _ghv_write_datas_230_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_231_T | _ghv_wens_231_T_1 | _ghv_wens_231_T_2 | _ghv_wens_231_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_231 <= _ghv_write_datas_231_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_232_T | _ghv_wens_232_T_1 | _ghv_wens_232_T_2 | _ghv_wens_232_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_232 <= _ghv_write_datas_232_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_233_T | _ghv_wens_233_T_1 | _ghv_wens_233_T_2 | _ghv_wens_233_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_233 <= _ghv_write_datas_233_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_234_T | _ghv_wens_234_T_1 | _ghv_wens_234_T_2 | _ghv_wens_234_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_234 <= _ghv_write_datas_234_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_235_T | _ghv_wens_235_T_1 | _ghv_wens_235_T_2 | _ghv_wens_235_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_235 <= _ghv_write_datas_235_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_236_T | _ghv_wens_236_T_1 | _ghv_wens_236_T_2 | _ghv_wens_236_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_236 <= _ghv_write_datas_236_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_237_T | _ghv_wens_237_T_1 | _ghv_wens_237_T_2 | _ghv_wens_237_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_237 <= _ghv_write_datas_237_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_238_T | _ghv_wens_238_T_1 | _ghv_wens_238_T_2 | _ghv_wens_238_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_238 <= _ghv_write_datas_238_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_239_T | _ghv_wens_239_T_1 | _ghv_wens_239_T_2 | _ghv_wens_239_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_239 <= _ghv_write_datas_239_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_240_T | _ghv_wens_240_T_1 | _ghv_wens_240_T_2 | _ghv_wens_240_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_240 <= _ghv_write_datas_240_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_241_T | _ghv_wens_241_T_1 | _ghv_wens_241_T_2 | _ghv_wens_241_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_241 <= _ghv_write_datas_241_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_242_T | _ghv_wens_242_T_1 | _ghv_wens_242_T_2 | _ghv_wens_242_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_242 <= _ghv_write_datas_242_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_243_T | _ghv_wens_243_T_1 | _ghv_wens_243_T_2 | _ghv_wens_243_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_243 <= _ghv_write_datas_243_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_244_T | _ghv_wens_244_T_1 | _ghv_wens_244_T_2 | _ghv_wens_244_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_244 <= _ghv_write_datas_244_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_245_T | _ghv_wens_245_T_1 | _ghv_wens_245_T_2 | _ghv_wens_245_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_245 <= _ghv_write_datas_245_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_246_T | _ghv_wens_246_T_1 | _ghv_wens_246_T_2 | _ghv_wens_246_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_246 <= _ghv_write_datas_246_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_247_T | _ghv_wens_247_T_1 | _ghv_wens_247_T_2 | _ghv_wens_247_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_247 <= _ghv_write_datas_247_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_248_T | _ghv_wens_248_T_1 | _ghv_wens_248_T_2 | _ghv_wens_248_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_248 <= _ghv_write_datas_248_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_249_T | _ghv_wens_249_T_1 | _ghv_wens_249_T_2 | _ghv_wens_249_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_249 <= _ghv_write_datas_249_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_250_T | _ghv_wens_250_T_1 | _ghv_wens_250_T_2 | _ghv_wens_250_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_250 <= _ghv_write_datas_250_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_251_T | _ghv_wens_251_T_1 | _ghv_wens_251_T_2 | _ghv_wens_251_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_251 <= _ghv_write_datas_251_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_252_T | _ghv_wens_252_T_1 | _ghv_wens_252_T_2 | _ghv_wens_252_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_252 <= _ghv_write_datas_252_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_253_T | _ghv_wens_253_T_1 | _ghv_wens_253_T_2 | _ghv_wens_253_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_253 <= _ghv_write_datas_253_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_254_T | _ghv_wens_254_T_1 | _ghv_wens_254_T_2 | _ghv_wens_254_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_254 <= _ghv_write_datas_254_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (_ghv_wens_255_T | _ghv_wens_255_T_1 | _ghv_wens_255_T_2 | _ghv_wens_255_T_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, :878:113] + ghv_255 <= _ghv_write_datas_255_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:312:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_ghist_ptr_reg_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + if (io_ftq_to_bpu_redirect_valid | do_redirect_dup_next_valid_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}] + do_redirect_dup_next_valid_last_r <= io_ftq_to_bpu_redirect_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + if (s1_fire_dup_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + previous_s1_pred_info_hit_0 <= _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40] + previous_s1_pred_info_hit_1 <= _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40] + previous_s1_pred_info_hit_2 <= _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40] + previous_s1_pred_info_hit_3 <= _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40] previous_s1_pred_info_target_0 <= - (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1 + : 41'h0) + | (~s1_pred_info_takenMask_0_0 & s1_pred_info_takenMask_0_1 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_0_1, s1_pred_info_takenMask_0_0} == 2'h0 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_fallThroughAddr - : 39'h0) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + : 41'h0) | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] previous_s1_pred_info_target_1 <= - (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1 + : 41'h0) + | (~s1_pred_info_takenMask_1_0 & s1_pred_info_takenMask_1_1 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_1_1, s1_pred_info_takenMask_1_0} == 2'h0 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_fallThroughAddr - : 39'h0) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + : 41'h0) | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] previous_s1_pred_info_target_2 <= - (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1 + : 41'h0) + | (~s1_pred_info_takenMask_2_0 & s1_pred_info_takenMask_2_1 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_2_1, s1_pred_info_takenMask_2_0} == 2'h0 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_fallThroughAddr - : 39'h0) | _GEN_6; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + : 41'h0) | _GEN_6; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] previous_s1_pred_info_target_3 <= - (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1 + : 41'h0) + | (~s1_pred_info_takenMask_3_0 & s1_pred_info_takenMask_3_1 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_3_1, s1_pred_info_takenMask_3_0} == 2'h0 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_fallThroughAddr - : 39'h0) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + : 41'h0) | _GEN_7; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] previous_s1_pred_info_lastBrPosOH_0_0 <= ~_predictors_io_out_s1_full_pred_0_hit - | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 - | _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_T_190528); // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :485:{14,19,22,41}] previous_s1_pred_info_lastBrPosOH_0_1 <= _predictors_io_out_s1_full_pred_0_slot_valids_0 - & (_GEN_99 | ~_s1_ghv_wdatas_WIRE_44494_1) - & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37,97} + & (_GEN_99 | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :489:{34,37,97}] previous_s1_pred_info_lastBrPosOH_0_2 <= - _s1_ghv_wdatas_WIRE_44494_1 & ~_GEN_99 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + _s1_ghv_wdatas_T_190528 & ~_GEN_99 & _predictors_io_out_s1_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :488:9, :489:97] previous_s1_pred_info_lastBrPosOH_1_0 <= - ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:{14,19,22,41}] previous_s1_pred_info_lastBrPosOH_1_1 <= _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:489:{34,97}] previous_s1_pred_info_lastBrPosOH_1_2 <= - _s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9 - & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + _s1_ghv_wdatas_T_190589 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :488:9, :489:97] previous_s1_pred_info_lastBrPosOH_2_0 <= - ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:{14,19,22,41}] previous_s1_pred_info_lastBrPosOH_2_1 <= _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:489:{34,97}] previous_s1_pred_info_lastBrPosOH_2_2 <= - _s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12 - & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + _s1_ghv_wdatas_T_190650 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :488:9, :489:97] previous_s1_pred_info_lastBrPosOH_3_0 <= - ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:{14,19,22,41}] previous_s1_pred_info_lastBrPosOH_3_1 <= _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:489:{34,97}] previous_s1_pred_info_lastBrPosOH_3_2 <= - _s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15 - & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + _s1_ghv_wdatas_T_190711 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :488:9, :489:97] previous_s1_pred_info_taken_0 <= |{_predictors_io_out_s1_full_pred_0_slot_valids_1 & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) & _predictors_io_out_s1_full_pred_0_hit, - _cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :520:{46,53}] previous_s1_pred_info_taken_1 <= |{_predictors_io_out_s1_full_pred_1_slot_valids_1 & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) & _predictors_io_out_s1_full_pred_1_hit, - _cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :520:{46,53}] previous_s1_pred_info_taken_2 <= |{_predictors_io_out_s1_full_pred_2_slot_valids_1 & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) & _predictors_io_out_s1_full_pred_2_hit, - _cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :520:{46,53}] previous_s1_pred_info_taken_3 <= |{_predictors_io_out_s1_full_pred_3_slot_valids_1 & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) & _predictors_io_out_s1_full_pred_3_hit, - _cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} - previous_s1_pred_info_takenMask_0_0 <= _cfiIndex_bits_WIRE_18_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - previous_s1_pred_info_takenMask_0_1 <= s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 - previous_s1_pred_info_takenMask_1_0 <= _cfiIndex_bits_WIRE_22_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - previous_s1_pred_info_takenMask_1_1 <= s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 - previous_s1_pred_info_takenMask_2_0 <= _cfiIndex_bits_WIRE_26_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - previous_s1_pred_info_takenMask_2_1 <= s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 - previous_s1_pred_info_takenMask_3_0 <= _cfiIndex_bits_WIRE_30_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 - previous_s1_pred_info_takenMask_3_1 <= s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 + s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :520:{46,53}] + previous_s1_pred_info_takenMask_0_0 <= s1_pred_info_takenMask_0_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + previous_s1_pred_info_takenMask_0_1 <= s1_pred_info_takenMask_0_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25] + previous_s1_pred_info_takenMask_1_0 <= s1_pred_info_takenMask_1_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + previous_s1_pred_info_takenMask_1_1 <= s1_pred_info_takenMask_1_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25] + previous_s1_pred_info_takenMask_2_0 <= s1_pred_info_takenMask_2_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + previous_s1_pred_info_takenMask_2_1 <= s1_pred_info_takenMask_2_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25] + previous_s1_pred_info_takenMask_3_0 <= s1_pred_info_takenMask_3_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69] + previous_s1_pred_info_takenMask_3_1 <= s1_pred_info_takenMask_3_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25] previous_s1_pred_info_cfiIndex_0 <= - (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_offsets_0 : _predictors_io_out_s1_full_pred_0_offsets_1) | {4{{_predictors_io_out_s1_full_pred_0_slot_valids_1 & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) & _predictors_io_out_s1_full_pred_0_hit, - _cfiIndex_bits_WIRE_18_0 - & _predictors_io_out_s1_full_pred_0_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s1_pred_info_takenMask_0_0 + & _predictors_io_out_s1_full_pred_0_hit} == 2'h0}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] previous_s1_pred_info_cfiIndex_1 <= - (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_offsets_0 : _predictors_io_out_s1_full_pred_1_offsets_1) | {4{{_predictors_io_out_s1_full_pred_1_slot_valids_1 & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) & _predictors_io_out_s1_full_pred_1_hit, - _cfiIndex_bits_WIRE_22_0 - & _predictors_io_out_s1_full_pred_1_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s1_pred_info_takenMask_1_0 + & _predictors_io_out_s1_full_pred_1_hit} == 2'h0}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] previous_s1_pred_info_cfiIndex_2 <= - (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_offsets_0 : _predictors_io_out_s1_full_pred_2_offsets_1) | {4{{_predictors_io_out_s1_full_pred_2_slot_valids_1 & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) & _predictors_io_out_s1_full_pred_2_hit, - _cfiIndex_bits_WIRE_26_0 - & _predictors_io_out_s1_full_pred_2_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s1_pred_info_takenMask_2_0 + & _predictors_io_out_s1_full_pred_2_hit} == 2'h0}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] previous_s1_pred_info_cfiIndex_3 <= - (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_offsets_0 : _predictors_io_out_s1_full_pred_3_offsets_1) | {4{{_predictors_io_out_s1_full_pred_3_slot_valids_1 & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) & _predictors_io_out_s1_full_pred_3_hit, - _cfiIndex_bits_WIRE_30_0 - & _predictors_io_out_s1_full_pred_3_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s1_pred_info_takenMask_3_0 + & _predictors_io_out_s1_full_pred_3_hit} == 2'h0}}; // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :601:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:69, :461:{25,47,50}, :468:38, :523:60, :524:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77] end + predictors_io_update_valid_REG <= io_ftq_to_bpu_update_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:728:40] end end // always @(posedge, posedge) - wire [38:0] _GEN_101 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:58, :278:43, :292:76, utility/src/main/scala/utility/Hold.scala:97:23 - always @(posedge clock) begin - s0_pc_reg_dup_0 <= REG_1 ? _GEN_101 : _s0_pc_dup_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_pc_reg_dup_1 <= REG_1 ? _GEN_101 : _s0_pc_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_pc_reg_dup_2 <= REG_1 ? _GEN_101 : _s0_pc_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - s0_pc_reg_dup_3 <= REG_1 ? _GEN_101 : _s0_pc_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:24 - REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:{16,24,39,42} - if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - s2_ftq_idx_flag <= io_ftq_to_bpu_enq_ptr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 - s2_ftq_idx_value <= io_ftq_to_bpu_enq_ptr_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 + wire [40:0] _GEN_101 = {5'h0, _reset_vector_delay_io_out}; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49, :278:58, :279:43, utility/src/main/scala/utility/Hold.scala:100:23] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + s0_pc_reg_dup_0 <= REG_1 ? _GEN_101 : _s0_pc_dup_0_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49, :278:{16,58}, :279:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_pc_reg_dup_1 <= REG_1 ? _GEN_101 : _s0_pc_dup_1_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49, :278:{16,58}, :279:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_pc_reg_dup_2 <= REG_1 ? _GEN_101 : _s0_pc_dup_2_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49, :278:{16,58}, :279:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + s0_pc_reg_dup_3 <= REG_1 ? _GEN_101 : _s0_pc_dup_3_ppm_out_res; // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49, :278:{16,58}, :279:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + REG <= reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:278:24] + REG_1 <= REG & ~reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:278:{16,24,39,42}] + if (io_ftq_to_bpu_redirect_valid) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + do_redirect_dup_next_bits_r_level <= io_ftq_to_bpu_redirect_bits_level; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pc <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pc; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_ssp <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_sctr <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_NOS_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_target <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_target; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_taken <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_taken; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_shift <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_shift; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist; // @[utility/src/main/scala/utility/BitUtils.scala:33:27] end - if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - s3_ftq_idx_flag <= s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29 - s3_ftq_idx_value <= s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29 + if (s1_fire_dup_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + s2_ftq_idx_flag <= io_ftq_to_bpu_enq_ptr_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29] + s2_ftq_idx_value <= io_ftq_to_bpu_enq_ptr_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29] end - predictors_io_update_REG_valid <= io_ftq_to_bpu_update_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_pc <= io_ftq_to_bpu_update_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist <= - io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_valid <= - io_ftq_to_bpu_update_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset <= - io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower <= - io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat <= - io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing <= - io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid <= - io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_offset <= - io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_lower <= - io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat <= - io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing <= - io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_valid <= - io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_pftAddr <= - io_ftq_to_bpu_update_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_carry <= - io_ftq_to_bpu_update_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_isCall <= - io_ftq_to_bpu_update_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_isRet <= - io_ftq_to_bpu_update_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_isJalr <= - io_ftq_to_bpu_update_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call <= - io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_always_taken_0 <= - io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_ftb_entry_always_taken_1 <= - io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_cfi_idx_valid <= - io_ftq_to_bpu_update_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_cfi_idx_bits <= io_ftq_to_bpu_update_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_br_taken_mask_0 <= - io_ftq_to_bpu_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_br_taken_mask_1 <= - io_ftq_to_bpu_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_jmp_taken <= io_ftq_to_bpu_update_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_mispred_mask_0 <= - io_ftq_to_bpu_update_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_mispred_mask_1 <= - io_ftq_to_bpu_update_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_mispred_mask_2 <= - io_ftq_to_bpu_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_old_entry <= io_ftq_to_bpu_update_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_meta <= io_ftq_to_bpu_update_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - predictors_io_update_REG_bits_full_target <= io_ftq_to_bpu_update_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + if (s2_valid_dup_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + s3_ftq_idx_flag <= s2_ftq_idx_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29, :710:29] + s3_ftq_idx_value <= s2_ftq_idx_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:709:29, :710:29] + end + if (io_ftq_to_bpu_update_valid) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:223:14] + predictors_io_update_bits_r_pc <= io_ftq_to_bpu_update_bits_pc; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_pftAddr <= + io_ftq_to_bpu_update_bits_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_carry <= + io_ftq_to_bpu_update_bits_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_isCall <= + io_ftq_to_bpu_update_bits_ftb_entry_isCall; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_isRet <= + io_ftq_to_bpu_update_bits_ftb_entry_isRet; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_isJalr <= + io_ftq_to_bpu_update_bits_ftb_entry_isJalr; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call <= + io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_always_taken_0 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_ftb_entry_always_taken_1 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_cfi_idx_valid <= + io_ftq_to_bpu_update_bits_cfi_idx_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_cfi_idx_bits <= io_ftq_to_bpu_update_bits_cfi_idx_bits; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_br_taken_mask_0 <= + io_ftq_to_bpu_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_br_taken_mask_1 <= + io_ftq_to_bpu_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_jmp_taken <= io_ftq_to_bpu_update_bits_jmp_taken; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_mispred_mask_0 <= + io_ftq_to_bpu_update_bits_mispred_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_mispred_mask_1 <= + io_ftq_to_bpu_update_bits_mispred_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_mispred_mask_2 <= + io_ftq_to_bpu_update_bits_mispred_mask_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_old_entry <= io_ftq_to_bpu_update_bits_old_entry; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_meta <= io_ftq_to_bpu_update_bits_meta; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + predictors_io_update_bits_r_full_target <= io_ftq_to_bpu_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + end + io_perf_0_value_REG <= _predictors_io_perf_0_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_0_value_REG_1 <= io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_1_value_REG <= _predictors_io_perf_1_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_1_value_REG_1 <= io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_2_value_REG <= _predictors_io_perf_2_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_2_value_REG_1 <= io_perf_2_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_3_value_REG <= _predictors_io_perf_3_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_3_value_REG_1 <= io_perf_3_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_4_value_REG <= _predictors_io_perf_4_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_4_value_REG_1 <= io_perf_4_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_5_value_REG <= _predictors_io_perf_5_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_5_value_REG_1 <= io_perf_5_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_6_value_REG <= _predictors_io_perf_6_value; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:226:26] + io_perf_6_value_REG_1 <= io_perf_6_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] end // always @(posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:180]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - initial begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + logic [31:0] _RANDOM[0:210]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + initial begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - for (logic [7:0] i = 8'h0; i < 8'hB5; i += 8'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - end // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - s1_valid_dup_3 = _RANDOM[8'h3][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 - s2_valid_dup_3 = _RANDOM[8'h3][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 - s3_valid_dup_3 = _RANDOM[8'h3][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 - s0_pc_reg_dup_0 = {_RANDOM[8'h3][31:30], _RANDOM[8'h4], _RANDOM[8'h5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :276:49 - s0_pc_reg_dup_1 = {_RANDOM[8'h5][31:5], _RANDOM[8'h6][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 - s0_pc_reg_dup_2 = {_RANDOM[8'h6][31:12], _RANDOM[8'h7][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 - s0_pc_reg_dup_3 = {_RANDOM[8'h7][31:19], _RANDOM[8'h8][25:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 - REG = _RANDOM[8'h8][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:24 - REG_1 = _RANDOM[8'h8][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:16 - s0_folded_gh_reg_dup_1_hist_17_folded_hist = _RANDOM[8'h11][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_16_folded_hist = _RANDOM[8'h11][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_15_folded_hist = - {_RANDOM[8'h11][31:27], _RANDOM[8'h12][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_14_folded_hist = _RANDOM[8'h12][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_13_folded_hist = _RANDOM[8'h12][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_12_folded_hist = _RANDOM[8'h12][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_11_folded_hist = _RANDOM[8'h12][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_10_folded_hist = - {_RANDOM[8'h12][31], _RANDOM[8'h13][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_9_folded_hist = _RANDOM[8'h13][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_8_folded_hist = _RANDOM[8'h13][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_7_folded_hist = _RANDOM[8'h13][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_6_folded_hist = - {_RANDOM[8'h13][31:30], _RANDOM[8'h14][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_5_folded_hist = _RANDOM[8'h14][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_4_folded_hist = _RANDOM[8'h14][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_3_folded_hist = _RANDOM[8'h14][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_2_folded_hist = - {_RANDOM[8'h14][31:30], _RANDOM[8'h15][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_1_folded_hist = _RANDOM[8'h15][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_0_folded_hist = _RANDOM[8'h15][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_17_folded_hist = - {_RANDOM[8'h15][31:25], _RANDOM[8'h16][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_16_folded_hist = _RANDOM[8'h16][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_15_folded_hist = _RANDOM[8'h16][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_14_folded_hist = _RANDOM[8'h16][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_13_folded_hist = - {_RANDOM[8'h16][31:30], _RANDOM[8'h17][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_12_folded_hist = _RANDOM[8'h17][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_11_folded_hist = _RANDOM[8'h17][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_10_folded_hist = _RANDOM[8'h17][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_9_folded_hist = - {_RANDOM[8'h17][31:28], _RANDOM[8'h18][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_8_folded_hist = _RANDOM[8'h18][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_7_folded_hist = _RANDOM[8'h18][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_6_folded_hist = _RANDOM[8'h18][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_5_folded_hist = - {_RANDOM[8'h18][31:27], _RANDOM[8'h19][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_4_folded_hist = _RANDOM[8'h19][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_3_folded_hist = _RANDOM[8'h19][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_2_folded_hist = _RANDOM[8'h19][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_1_folded_hist = - {_RANDOM[8'h19][31:26], _RANDOM[8'h1A][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_0_folded_hist = _RANDOM[8'h1A][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_17_folded_hist = _RANDOM[8'h1A][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_16_folded_hist = - {_RANDOM[8'h1A][31:24], _RANDOM[8'h1B][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_15_folded_hist = _RANDOM[8'h1B][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_14_folded_hist = _RANDOM[8'h1B][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_13_folded_hist = _RANDOM[8'h1B][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_12_folded_hist = _RANDOM[8'h1B][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_11_folded_hist = - {_RANDOM[8'h1B][31], _RANDOM[8'h1C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_10_folded_hist = _RANDOM[8'h1C][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_9_folded_hist = _RANDOM[8'h1C][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_8_folded_hist = _RANDOM[8'h1C][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_7_folded_hist = - {_RANDOM[8'h1C][31], _RANDOM[8'h1D][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_6_folded_hist = _RANDOM[8'h1D][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_5_folded_hist = _RANDOM[8'h1D][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_4_folded_hist = _RANDOM[8'h1D][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_3_folded_hist = - {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_2_folded_hist = _RANDOM[8'h1E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_1_folded_hist = _RANDOM[8'h1E][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_0_folded_hist = - {_RANDOM[8'h1E][31:25], _RANDOM[8'h1F][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s1_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h23][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h24][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h24][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h24][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_13_folded_hist = - {_RANDOM[8'h24][31:26], _RANDOM[8'h25][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h25][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h25][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h25][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h25][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h25][31], _RANDOM[8'h26][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h26][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h26][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h26][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_4_folded_hist = - {_RANDOM[8'h26][31:30], _RANDOM[8'h27][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h27][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h27][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_1_folded_hist = - {_RANDOM[8'h27][31:22], _RANDOM[8'h28][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h28][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h28][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h28][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_15_folded_hist = - {_RANDOM[8'h28][31], _RANDOM[8'h29][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h29][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h29][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h29][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_11_folded_hist = - {_RANDOM[8'h29][31:27], _RANDOM[8'h2A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h2A][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h2A][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h2A][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_7_folded_hist = - {_RANDOM[8'h2A][31:27], _RANDOM[8'h2B][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h2B][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h2B][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h2B][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_3_folded_hist = - {_RANDOM[8'h2B][31:26], _RANDOM[8'h2C][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h2C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h2C][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h2C][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_17_folded_hist = - {_RANDOM[8'h2C][31:29], _RANDOM[8'h2D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h2D][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h2D][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_14_folded_hist = - {_RANDOM[8'h2D][31:26], _RANDOM[8'h2E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h2E][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h2E][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h2E][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h2E][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h2F][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h2F][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h2F][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h2F][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h2F][31], _RANDOM[8'h30][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h30][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h30][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h30][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_1_folded_hist = - {_RANDOM[8'h30][31:30], _RANDOM[8'h31][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h31][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s2_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h36][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h36][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_15_folded_hist = - {_RANDOM[8'h36][31:27], _RANDOM[8'h37][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h37][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h37][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h37][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h37][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_10_folded_hist = - {_RANDOM[8'h37][31], _RANDOM[8'h38][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h38][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h38][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h38][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_6_folded_hist = - {_RANDOM[8'h38][31:30], _RANDOM[8'h39][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h39][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h39][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h39][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_2_folded_hist = - {_RANDOM[8'h39][31:30], _RANDOM[8'h3A][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h3A][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h3A][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_17_folded_hist = - {_RANDOM[8'h3A][31:25], _RANDOM[8'h3B][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h3B][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h3B][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h3B][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_13_folded_hist = - {_RANDOM[8'h3B][31:30], _RANDOM[8'h3C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h3C][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h3C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h3C][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_9_folded_hist = - {_RANDOM[8'h3C][31:28], _RANDOM[8'h3D][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h3D][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h3D][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h3D][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_5_folded_hist = - {_RANDOM[8'h3D][31:27], _RANDOM[8'h3E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h3E][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h3E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h3E][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_1_folded_hist = - {_RANDOM[8'h3E][31:26], _RANDOM[8'h3F][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h3F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h3F][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_16_folded_hist = - {_RANDOM[8'h3F][31:24], _RANDOM[8'h40][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h40][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h40][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h40][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h40][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_11_folded_hist = - {_RANDOM[8'h40][31], _RANDOM[8'h41][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h41][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h41][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h41][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_7_folded_hist = {_RANDOM[8'h41][31], _RANDOM[8'h42][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h42][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h42][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h42][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_3_folded_hist = - {_RANDOM[8'h42][31:30], _RANDOM[8'h43][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h43][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h43][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_0_folded_hist = - {_RANDOM[8'h43][31:25], _RANDOM[8'h44][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s3_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h48][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h49][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h49][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h49][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_13_folded_hist = - {_RANDOM[8'h49][31:26], _RANDOM[8'h4A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h4A][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h4A][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h4A][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h4A][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h4A][31], _RANDOM[8'h4B][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h4B][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h4B][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h4B][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_4_folded_hist = - {_RANDOM[8'h4B][31:30], _RANDOM[8'h4C][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h4C][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h4C][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_1_folded_hist = - {_RANDOM[8'h4C][31:22], _RANDOM[8'h4D][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h4D][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h4D][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h4D][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_15_folded_hist = - {_RANDOM[8'h4D][31], _RANDOM[8'h4E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h4E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h4E][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h4E][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_11_folded_hist = - {_RANDOM[8'h4E][31:27], _RANDOM[8'h4F][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h4F][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h4F][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h4F][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_7_folded_hist = - {_RANDOM[8'h4F][31:27], _RANDOM[8'h50][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h50][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h50][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h50][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_3_folded_hist = - {_RANDOM[8'h50][31:26], _RANDOM[8'h51][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h51][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h51][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h51][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_17_folded_hist = - {_RANDOM[8'h51][31:29], _RANDOM[8'h52][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h52][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h52][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_14_folded_hist = - {_RANDOM[8'h52][31:26], _RANDOM[8'h53][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h53][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h53][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h53][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h53][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h54][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h54][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h54][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h54][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h54][31], _RANDOM[8'h55][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h55][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h55][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h55][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_1_folded_hist = - {_RANDOM[8'h55][31:30], _RANDOM[8'h56][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h56][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s0_last_br_num_oh_reg_dup_1 = _RANDOM[8'h56][22:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 - s0_last_br_num_oh_reg_dup_2 = _RANDOM[8'h56][25:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 - s0_last_br_num_oh_reg_dup_3 = _RANDOM[8'h56][28:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 - s1_last_br_num_oh_dup_1 = _RANDOM[8'h57][2:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 - s1_last_br_num_oh_dup_2 = _RANDOM[8'h57][5:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 - s1_last_br_num_oh_dup_3 = _RANDOM[8'h57][8:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 - s2_last_br_num_oh_dup_1 = _RANDOM[8'h57][14:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 - s2_last_br_num_oh_dup_2 = _RANDOM[8'h57][17:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 - s2_last_br_num_oh_dup_3 = _RANDOM[8'h57][20:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 - s3_last_br_num_oh_dup_1 = _RANDOM[8'h57][26:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 - s3_last_br_num_oh_dup_2 = _RANDOM[8'h57][29:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 - s3_last_br_num_oh_dup_3 = {_RANDOM[8'h57][31:30], _RANDOM[8'h58][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = _RANDOM[8'h58][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = _RANDOM[8'h58][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = _RANDOM[8'h58][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = _RANDOM[8'h58][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = _RANDOM[8'h58][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = _RANDOM[8'h58][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = _RANDOM[8'h58][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = _RANDOM[8'h59][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = _RANDOM[8'h59][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = _RANDOM[8'h59][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = _RANDOM[8'h59][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = _RANDOM[8'h59][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = _RANDOM[8'h59][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = _RANDOM[8'h59][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = _RANDOM[8'h59][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = _RANDOM[8'h59][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = _RANDOM[8'h59][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = _RANDOM[8'h59][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = _RANDOM[8'h59][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = _RANDOM[8'h59][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = _RANDOM[8'h59][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = _RANDOM[8'h59][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = _RANDOM[8'h59][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = _RANDOM[8'h59][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = _RANDOM[8'h59][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = _RANDOM[8'h59][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = _RANDOM[8'h59][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = _RANDOM[8'h59][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = _RANDOM[8'h59][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = _RANDOM[8'h59][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = _RANDOM[8'h59][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = _RANDOM[8'h59][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = _RANDOM[8'h59][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = _RANDOM[8'h59][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = _RANDOM[8'h59][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = _RANDOM[8'h59][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = _RANDOM[8'h59][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = _RANDOM[8'h59][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = _RANDOM[8'h59][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = _RANDOM[8'h5A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = _RANDOM[8'h5A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = _RANDOM[8'h5A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = _RANDOM[8'h5A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = _RANDOM[8'h5A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = _RANDOM[8'h5A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = _RANDOM[8'h5A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = _RANDOM[8'h5A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = _RANDOM[8'h5A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = _RANDOM[8'h5A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = _RANDOM[8'h5A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = _RANDOM[8'h5A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = _RANDOM[8'h5A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = _RANDOM[8'h5A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = _RANDOM[8'h5A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = _RANDOM[8'h5A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = _RANDOM[8'h5A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = _RANDOM[8'h5A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = _RANDOM[8'h5A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = _RANDOM[8'h5A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = _RANDOM[8'h5A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = _RANDOM[8'h5A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = _RANDOM[8'h5A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = _RANDOM[8'h5A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = _RANDOM[8'h5A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = _RANDOM[8'h5A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = _RANDOM[8'h5A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = _RANDOM[8'h5A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = _RANDOM[8'h5A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = _RANDOM[8'h5A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = _RANDOM[8'h5A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = _RANDOM[8'h5A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = _RANDOM[8'h5B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5C][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5C][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5C][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5C][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5C][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5C][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5C][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5C][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5C][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5C][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5C][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5C][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5C][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5C][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5C][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5C][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5C][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5C][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5C][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5C][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5C][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5C][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5C][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5C][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5C][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h5D][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h5D][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h5D][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h5D][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h5D][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h5D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h5D][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h5D][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h5D][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h5D][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h5D][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h5D][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h5D][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h5D][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h5D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h5D][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h5D][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h5D][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h5D][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h5D][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h5D][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h5D][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h5D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h5D][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h5D][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h5D][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h5D][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h5D][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h5D][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h5D][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h5D][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h5E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5E][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5E][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5E][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5E][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5E][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5E][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5F][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5F][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5F][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5F][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5F][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5F][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5F][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5F][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5F][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5F][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5F][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5F][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5F][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5F][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5F][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5F][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5F][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5F][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5F][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5F][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5F][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5F][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5F][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5F][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h60][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h60][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h60][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h60][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h60][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h60][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h60][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h60][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h60][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h60][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h60][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h60][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h60][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h60][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h60][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h60][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h60][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h60][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h60][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h60][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h60][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h60][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h60][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h60][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h60][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h60][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h60][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h60][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h60][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h60][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h60][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h61][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h61][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h61][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h61][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h61][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h61][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h61][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h61][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h62][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h62][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h62][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h62][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h62][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h62][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h62][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h62][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h62][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h62][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h62][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h62][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h62][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h62][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h62][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h62][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h62][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h62][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h62][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h62][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h62][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h62][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h62][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h62][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h62][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h62][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h62][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h62][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h62][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h62][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h62][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h63][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h63][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h63][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h63][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h63][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h63][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h63][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h63][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h63][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h63][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h63][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h63][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h63][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h63][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h63][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h63][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h63][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h63][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h63][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h63][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h63][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h63][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h63][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h63][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h63][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h63][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h63][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h63][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h63][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h63][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h63][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h64][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 - ghv_0 = _RANDOM[8'h64][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_1 = _RANDOM[8'h64][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_2 = _RANDOM[8'h64][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_3 = _RANDOM[8'h64][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_4 = _RANDOM[8'h64][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_5 = _RANDOM[8'h64][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_6 = _RANDOM[8'h64][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_7 = _RANDOM[8'h64][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_8 = _RANDOM[8'h64][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_9 = _RANDOM[8'h64][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_10 = _RANDOM[8'h64][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_11 = _RANDOM[8'h64][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_12 = _RANDOM[8'h64][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_13 = _RANDOM[8'h64][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_14 = _RANDOM[8'h64][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_15 = _RANDOM[8'h64][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_16 = _RANDOM[8'h64][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_17 = _RANDOM[8'h64][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_18 = _RANDOM[8'h64][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_19 = _RANDOM[8'h64][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_20 = _RANDOM[8'h64][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_21 = _RANDOM[8'h64][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_22 = _RANDOM[8'h64][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_23 = _RANDOM[8'h64][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_24 = _RANDOM[8'h64][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_25 = _RANDOM[8'h64][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_26 = _RANDOM[8'h64][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_27 = _RANDOM[8'h64][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_28 = _RANDOM[8'h64][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_29 = _RANDOM[8'h64][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_30 = _RANDOM[8'h64][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 - ghv_31 = _RANDOM[8'h65][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_32 = _RANDOM[8'h65][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_33 = _RANDOM[8'h65][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_34 = _RANDOM[8'h65][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_35 = _RANDOM[8'h65][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_36 = _RANDOM[8'h65][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_37 = _RANDOM[8'h65][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_38 = _RANDOM[8'h65][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_39 = _RANDOM[8'h65][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_40 = _RANDOM[8'h65][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_41 = _RANDOM[8'h65][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_42 = _RANDOM[8'h65][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_43 = _RANDOM[8'h65][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_44 = _RANDOM[8'h65][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_45 = _RANDOM[8'h65][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_46 = _RANDOM[8'h65][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_47 = _RANDOM[8'h65][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_48 = _RANDOM[8'h65][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_49 = _RANDOM[8'h65][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_50 = _RANDOM[8'h65][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_51 = _RANDOM[8'h65][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_52 = _RANDOM[8'h65][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_53 = _RANDOM[8'h65][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_54 = _RANDOM[8'h65][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_55 = _RANDOM[8'h65][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_56 = _RANDOM[8'h65][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_57 = _RANDOM[8'h65][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_58 = _RANDOM[8'h65][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_59 = _RANDOM[8'h65][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_60 = _RANDOM[8'h65][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_61 = _RANDOM[8'h65][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_62 = _RANDOM[8'h65][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_63 = _RANDOM[8'h66][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_64 = _RANDOM[8'h66][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_65 = _RANDOM[8'h66][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_66 = _RANDOM[8'h66][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_67 = _RANDOM[8'h66][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_68 = _RANDOM[8'h66][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_69 = _RANDOM[8'h66][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_70 = _RANDOM[8'h66][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_71 = _RANDOM[8'h66][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_72 = _RANDOM[8'h66][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_73 = _RANDOM[8'h66][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_74 = _RANDOM[8'h66][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_75 = _RANDOM[8'h66][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_76 = _RANDOM[8'h66][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_77 = _RANDOM[8'h66][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_78 = _RANDOM[8'h66][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_79 = _RANDOM[8'h66][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_80 = _RANDOM[8'h66][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_81 = _RANDOM[8'h66][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_82 = _RANDOM[8'h66][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_83 = _RANDOM[8'h66][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_84 = _RANDOM[8'h66][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_85 = _RANDOM[8'h66][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_86 = _RANDOM[8'h66][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_87 = _RANDOM[8'h66][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_88 = _RANDOM[8'h66][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_89 = _RANDOM[8'h66][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_90 = _RANDOM[8'h66][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_91 = _RANDOM[8'h66][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_92 = _RANDOM[8'h66][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_93 = _RANDOM[8'h66][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_94 = _RANDOM[8'h66][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_95 = _RANDOM[8'h67][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_96 = _RANDOM[8'h67][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_97 = _RANDOM[8'h67][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_98 = _RANDOM[8'h67][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_99 = _RANDOM[8'h67][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_100 = _RANDOM[8'h67][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_101 = _RANDOM[8'h67][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_102 = _RANDOM[8'h67][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_103 = _RANDOM[8'h67][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_104 = _RANDOM[8'h67][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_105 = _RANDOM[8'h67][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_106 = _RANDOM[8'h67][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_107 = _RANDOM[8'h67][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_108 = _RANDOM[8'h67][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_109 = _RANDOM[8'h67][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_110 = _RANDOM[8'h67][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_111 = _RANDOM[8'h67][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_112 = _RANDOM[8'h67][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_113 = _RANDOM[8'h67][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_114 = _RANDOM[8'h67][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_115 = _RANDOM[8'h67][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_116 = _RANDOM[8'h67][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_117 = _RANDOM[8'h67][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_118 = _RANDOM[8'h67][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_119 = _RANDOM[8'h67][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_120 = _RANDOM[8'h67][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_121 = _RANDOM[8'h67][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_122 = _RANDOM[8'h67][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_123 = _RANDOM[8'h67][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_124 = _RANDOM[8'h67][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_125 = _RANDOM[8'h67][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_126 = _RANDOM[8'h67][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_127 = _RANDOM[8'h68][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_128 = _RANDOM[8'h68][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_129 = _RANDOM[8'h68][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_130 = _RANDOM[8'h68][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_131 = _RANDOM[8'h68][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_132 = _RANDOM[8'h68][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_133 = _RANDOM[8'h68][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_134 = _RANDOM[8'h68][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_135 = _RANDOM[8'h68][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_136 = _RANDOM[8'h68][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_137 = _RANDOM[8'h68][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_138 = _RANDOM[8'h68][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_139 = _RANDOM[8'h68][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_140 = _RANDOM[8'h68][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_141 = _RANDOM[8'h68][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_142 = _RANDOM[8'h68][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_143 = _RANDOM[8'h68][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_144 = _RANDOM[8'h68][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_145 = _RANDOM[8'h68][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_146 = _RANDOM[8'h68][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_147 = _RANDOM[8'h68][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_148 = _RANDOM[8'h68][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_149 = _RANDOM[8'h68][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_150 = _RANDOM[8'h68][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_151 = _RANDOM[8'h68][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_152 = _RANDOM[8'h68][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_153 = _RANDOM[8'h68][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_154 = _RANDOM[8'h68][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_155 = _RANDOM[8'h68][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_156 = _RANDOM[8'h68][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_157 = _RANDOM[8'h68][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_158 = _RANDOM[8'h68][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_159 = _RANDOM[8'h69][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_160 = _RANDOM[8'h69][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_161 = _RANDOM[8'h69][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_162 = _RANDOM[8'h69][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_163 = _RANDOM[8'h69][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_164 = _RANDOM[8'h69][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_165 = _RANDOM[8'h69][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_166 = _RANDOM[8'h69][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_167 = _RANDOM[8'h69][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_168 = _RANDOM[8'h69][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_169 = _RANDOM[8'h69][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_170 = _RANDOM[8'h69][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_171 = _RANDOM[8'h69][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_172 = _RANDOM[8'h69][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_173 = _RANDOM[8'h69][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_174 = _RANDOM[8'h69][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_175 = _RANDOM[8'h69][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_176 = _RANDOM[8'h69][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_177 = _RANDOM[8'h69][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_178 = _RANDOM[8'h69][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_179 = _RANDOM[8'h69][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_180 = _RANDOM[8'h69][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_181 = _RANDOM[8'h69][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_182 = _RANDOM[8'h69][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_183 = _RANDOM[8'h69][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_184 = _RANDOM[8'h69][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_185 = _RANDOM[8'h69][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_186 = _RANDOM[8'h69][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_187 = _RANDOM[8'h69][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_188 = _RANDOM[8'h69][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_189 = _RANDOM[8'h69][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_190 = _RANDOM[8'h69][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_191 = _RANDOM[8'h6A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_192 = _RANDOM[8'h6A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_193 = _RANDOM[8'h6A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_194 = _RANDOM[8'h6A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_195 = _RANDOM[8'h6A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_196 = _RANDOM[8'h6A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_197 = _RANDOM[8'h6A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_198 = _RANDOM[8'h6A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_199 = _RANDOM[8'h6A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_200 = _RANDOM[8'h6A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_201 = _RANDOM[8'h6A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_202 = _RANDOM[8'h6A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_203 = _RANDOM[8'h6A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_204 = _RANDOM[8'h6A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_205 = _RANDOM[8'h6A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_206 = _RANDOM[8'h6A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_207 = _RANDOM[8'h6A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_208 = _RANDOM[8'h6A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_209 = _RANDOM[8'h6A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_210 = _RANDOM[8'h6A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_211 = _RANDOM[8'h6A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_212 = _RANDOM[8'h6A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_213 = _RANDOM[8'h6A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_214 = _RANDOM[8'h6A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_215 = _RANDOM[8'h6A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_216 = _RANDOM[8'h6A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_217 = _RANDOM[8'h6A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_218 = _RANDOM[8'h6A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_219 = _RANDOM[8'h6A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_220 = _RANDOM[8'h6A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_221 = _RANDOM[8'h6A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_222 = _RANDOM[8'h6A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_223 = _RANDOM[8'h6B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_224 = _RANDOM[8'h6B][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_225 = _RANDOM[8'h6B][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_226 = _RANDOM[8'h6B][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_227 = _RANDOM[8'h6B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_228 = _RANDOM[8'h6B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_229 = _RANDOM[8'h6B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_230 = _RANDOM[8'h6B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_231 = _RANDOM[8'h6B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_232 = _RANDOM[8'h6B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_233 = _RANDOM[8'h6B][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_234 = _RANDOM[8'h6B][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_235 = _RANDOM[8'h6B][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_236 = _RANDOM[8'h6B][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_237 = _RANDOM[8'h6B][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_238 = _RANDOM[8'h6B][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_239 = _RANDOM[8'h6B][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_240 = _RANDOM[8'h6B][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_241 = _RANDOM[8'h6B][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_242 = _RANDOM[8'h6B][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_243 = _RANDOM[8'h6B][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_244 = _RANDOM[8'h6B][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_245 = _RANDOM[8'h6B][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_246 = _RANDOM[8'h6B][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_247 = _RANDOM[8'h6B][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_248 = _RANDOM[8'h6B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_249 = _RANDOM[8'h6B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_250 = _RANDOM[8'h6B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_251 = _RANDOM[8'h6B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_252 = _RANDOM[8'h6B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_253 = _RANDOM[8'h6B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_254 = _RANDOM[8'h6B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - ghv_255 = _RANDOM[8'h6C][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 - s0_ghist_ptr_reg_dup_0_flag = _RANDOM[8'h6C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_0_value = _RANDOM[8'h6C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_1_flag = _RANDOM[8'h6C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_1_value = _RANDOM[8'h6C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_2_flag = _RANDOM[8'h6C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_2_value = _RANDOM[8'h6C][27:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_3_flag = _RANDOM[8'h6C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s0_ghist_ptr_reg_dup_3_value = {_RANDOM[8'h6C][31:29], _RANDOM[8'h6D][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 - s1_ghist_ptr_dup_0_flag = _RANDOM[8'h6D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_0_value = _RANDOM[8'h6D][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_1_flag = _RANDOM[8'h6D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_1_value = _RANDOM[8'h6D][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_2_flag = _RANDOM[8'h6D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_2_value = _RANDOM[8'h6D][31:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 - s1_ghist_ptr_dup_3_flag = _RANDOM[8'h6E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_3_value = _RANDOM[8'h6E][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s2_ghist_ptr_dup_0_flag = _RANDOM[8'h6E][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_0_value = _RANDOM[8'h6E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_1_flag = _RANDOM[8'h6E][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_1_value = _RANDOM[8'h6E][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_2_flag = _RANDOM[8'h6E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_2_value = {_RANDOM[8'h6E][31:28], _RANDOM[8'h6F][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 - s2_ghist_ptr_dup_3_flag = _RANDOM[8'h6F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_3_value = _RANDOM[8'h6F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s3_ghist_ptr_dup_0_flag = _RANDOM[8'h6F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 - s3_ghist_ptr_dup_0_value = _RANDOM[8'h6F][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 - s3_ghist_ptr_dup_1_flag = _RANDOM[8'h6F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 - s3_ghist_ptr_dup_1_value = _RANDOM[8'h6F][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 - s3_ghist_ptr_dup_2_flag = _RANDOM[8'h6F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 - s3_ghist_ptr_dup_2_value = _RANDOM[8'h70][7:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_3_flag = _RANDOM[8'h70][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_3_value = _RANDOM[8'h70][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - do_redirect_dup_3_valid = _RANDOM[8'h70][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, :350:40 - do_redirect_dup_3_bits_level = _RANDOM[8'h71][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pc = - {_RANDOM[8'h71][31:9], _RANDOM[8'h72][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = _RANDOM[8'h72][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isCall = _RANDOM[8'h72][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRet = _RANDOM[8'h72][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_ssp = _RANDOM[8'h72][25:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_sctr = _RANDOM[8'h72][27:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = _RANDOM[8'h72][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_value = - {_RANDOM[8'h72][31:29], _RANDOM[8'h73][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = _RANDOM[8'h73][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_value = _RANDOM[8'h73][7:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_flag = _RANDOM[8'h73][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_value = _RANDOM[8'h73][13:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist = - _RANDOM[8'h74][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist = - _RANDOM[8'h75][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist = - _RANDOM[8'h75][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist = - _RANDOM[8'h75][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist = - {_RANDOM[8'h75][31:26], _RANDOM[8'h76][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist = - _RANDOM[8'h76][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist = - _RANDOM[8'h76][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist = - _RANDOM[8'h76][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist = - _RANDOM[8'h76][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist = - {_RANDOM[8'h76][31], _RANDOM[8'h77][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist = - _RANDOM[8'h77][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist = - _RANDOM[8'h77][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist = - _RANDOM[8'h77][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist = - {_RANDOM[8'h77][31:30], _RANDOM[8'h78][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist = - _RANDOM[8'h78][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist = - _RANDOM[8'h78][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist = - {_RANDOM[8'h78][31:22], _RANDOM[8'h79][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist = - _RANDOM[8'h79][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = _RANDOM[8'h79][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = _RANDOM[8'h79][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = _RANDOM[8'h79][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = _RANDOM[8'h79][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = _RANDOM[8'h79][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = _RANDOM[8'h79][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = _RANDOM[8'h79][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = _RANDOM[8'h79][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = _RANDOM[8'h79][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = _RANDOM[8'h79][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = _RANDOM[8'h79][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = _RANDOM[8'h79][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = _RANDOM[8'h79][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = _RANDOM[8'h79][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = _RANDOM[8'h79][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = _RANDOM[8'h79][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = _RANDOM[8'h79][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = _RANDOM[8'h79][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = _RANDOM[8'h79][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = _RANDOM[8'h79][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = _RANDOM[8'h79][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = _RANDOM[8'h79][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = _RANDOM[8'h7A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = _RANDOM[8'h7A][3:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = _RANDOM[8'h7A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_value = _RANDOM[8'h7A][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_target = - {_RANDOM[8'h7B][31:9], _RANDOM[8'h7C][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_taken = _RANDOM[8'h7C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - thisBrNumOH_dup_shiftAmount = _RANDOM[8'h7C][19:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_addIntoHist = _RANDOM[8'h7C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - previous_s1_pred_info_hit_0 = _RANDOM[8'h7F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_hit_1 = _RANDOM[8'h7F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_hit_2 = _RANDOM[8'h7F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_hit_3 = _RANDOM[8'h7F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_target_0 = {_RANDOM[8'h7F][31:7], _RANDOM[8'h80][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_target_1 = {_RANDOM[8'h80][31:14], _RANDOM[8'h81][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_target_2 = {_RANDOM[8'h81][31:21], _RANDOM[8'h82][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_target_3 = - {_RANDOM[8'h82][31:28], _RANDOM[8'h83], _RANDOM[8'h84][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_0_0 = _RANDOM[8'h84][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_0_1 = _RANDOM[8'h84][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_0_2 = _RANDOM[8'h84][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_1_0 = _RANDOM[8'h84][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_1_1 = _RANDOM[8'h84][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_1_2 = _RANDOM[8'h84][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_2_0 = _RANDOM[8'h84][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_2_1 = _RANDOM[8'h84][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_2_2 = _RANDOM[8'h84][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_3_0 = _RANDOM[8'h84][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_3_1 = _RANDOM[8'h84][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_lastBrPosOH_3_2 = _RANDOM[8'h84][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_taken_0 = _RANDOM[8'h84][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_taken_1 = _RANDOM[8'h84][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_taken_2 = _RANDOM[8'h84][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_taken_3 = _RANDOM[8'h84][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_0_0 = _RANDOM[8'h84][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_0_1 = _RANDOM[8'h84][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_1_0 = _RANDOM[8'h84][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_1_1 = _RANDOM[8'h84][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_2_0 = _RANDOM[8'h84][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_2_1 = _RANDOM[8'h84][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_3_0 = _RANDOM[8'h84][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_takenMask_3_1 = _RANDOM[8'h84][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_cfiIndex_0 = _RANDOM[8'h84][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_cfiIndex_1 = {_RANDOM[8'h84][31], _RANDOM[8'h85][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_cfiIndex_2 = _RANDOM[8'h85][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s1_pred_info_cfiIndex_3 = _RANDOM[8'h85][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 - previous_s2_pred_pc_0 = {_RANDOM[8'h85][31:11], _RANDOM[8'h86][17:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40, :673:35 - previous_s2_pred_pc_1 = {_RANDOM[8'h86][31:18], _RANDOM[8'h87][24:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_pc_2 = {_RANDOM[8'h87][31:25], _RANDOM[8'h88]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_pc_3 = {_RANDOM[8'h89], _RANDOM[8'h8A][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_0 = _RANDOM[8'h8A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_1 = _RANDOM[8'h8A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_slot_valids_0 = _RANDOM[8'h8A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_slot_valids_1 = _RANDOM[8'h8A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + for (logic [7:0] i = 8'h0; i < 8'hD3; i += 8'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + end // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + s1_valid_dup_3 = _RANDOM[8'h3][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65] + s2_valid_dup_3 = _RANDOM[8'h3][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65] + s3_valid_dup_3 = _RANDOM[8'h3][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65] + s0_pc_reg_dup_0 = {_RANDOM[8'h3][31:30], _RANDOM[8'h4], _RANDOM[8'h5][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65, :277:49] + s0_pc_reg_dup_1 = {_RANDOM[8'h5][31:7], _RANDOM[8'h6][15:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :277:49] + s0_pc_reg_dup_2 = {_RANDOM[8'h6][31:16], _RANDOM[8'h7][24:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :277:49] + s0_pc_reg_dup_3 = {_RANDOM[8'h7][31:25], _RANDOM[8'h8], _RANDOM[8'h9][1:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :277:49] + REG = _RANDOM[8'h9][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :277:49, :278:24] + REG_1 = _RANDOM[8'h9][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :277:49, :278:16] + s0_folded_gh_reg_dup_1_hist_17_folded_hist = _RANDOM[8'h11][29:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_16_folded_hist = + {_RANDOM[8'h11][31:30], _RANDOM[8'h12][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_15_folded_hist = _RANDOM[8'h12][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_14_folded_hist = _RANDOM[8'h12][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_13_folded_hist = + {_RANDOM[8'h12][31:24], _RANDOM[8'h13][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_12_folded_hist = _RANDOM[8'h13][4:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_11_folded_hist = _RANDOM[8'h13][12:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_10_folded_hist = _RANDOM[8'h13][21:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_9_folded_hist = _RANDOM[8'h13][28:22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_8_folded_hist = + {_RANDOM[8'h13][31:29], _RANDOM[8'h14][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_7_folded_hist = _RANDOM[8'h14][11:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_6_folded_hist = _RANDOM[8'h14][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_5_folded_hist = _RANDOM[8'h14][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_4_folded_hist = + {_RANDOM[8'h14][31:28], _RANDOM[8'h15][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_3_folded_hist = _RANDOM[8'h15][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_2_folded_hist = _RANDOM[8'h15][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_1_folded_hist = _RANDOM[8'h15][30:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_0_folded_hist = + {_RANDOM[8'h15][31], _RANDOM[8'h16][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_17_folded_hist = _RANDOM[8'h16][17:7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_16_folded_hist = _RANDOM[8'h16][28:18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_15_folded_hist = + {_RANDOM[8'h16][31:29], _RANDOM[8'h17][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_14_folded_hist = _RANDOM[8'h17][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_13_folded_hist = _RANDOM[8'h17][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_12_folded_hist = _RANDOM[8'h17][24:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_11_folded_hist = + {_RANDOM[8'h17][31:25], _RANDOM[8'h18][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_10_folded_hist = _RANDOM[8'h18][9:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_9_folded_hist = _RANDOM[8'h18][16:10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_8_folded_hist = _RANDOM[8'h18][24:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_7_folded_hist = _RANDOM[8'h18][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_6_folded_hist = _RANDOM[8'h19][8:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_5_folded_hist = _RANDOM[8'h19][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_4_folded_hist = _RANDOM[8'h19][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_3_folded_hist = _RANDOM[8'h19][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_2_folded_hist = _RANDOM[8'h1A][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_1_folded_hist = _RANDOM[8'h1A][18:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_0_folded_hist = _RANDOM[8'h1A][26:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_17_folded_hist = + {_RANDOM[8'h1A][31:27], _RANDOM[8'h1B][5:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_16_folded_hist = _RANDOM[8'h1B][16:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_15_folded_hist = _RANDOM[8'h1B][23:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_14_folded_hist = _RANDOM[8'h1B][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_13_folded_hist = _RANDOM[8'h1C][8:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_12_folded_hist = _RANDOM[8'h1C][12:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_11_folded_hist = _RANDOM[8'h1C][20:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_10_folded_hist = _RANDOM[8'h1C][29:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_9_folded_hist = + {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_8_folded_hist = _RANDOM[8'h1D][12:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_7_folded_hist = _RANDOM[8'h1D][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_6_folded_hist = _RANDOM[8'h1D][28:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_5_folded_hist = + {_RANDOM[8'h1D][31:29], _RANDOM[8'h1E][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_4_folded_hist = _RANDOM[8'h1E][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_3_folded_hist = _RANDOM[8'h1E][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_2_folded_hist = _RANDOM[8'h1E][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_1_folded_hist = + {_RANDOM[8'h1E][31:28], _RANDOM[8'h1F][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_0_folded_hist = _RANDOM[8'h1F][14:7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s1_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h24][13:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h24][24:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h24][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h25][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h25][16:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h25][20:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h25][28:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_10_folded_hist = + {_RANDOM[8'h25][31:29], _RANDOM[8'h26][5:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h26][12:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h26][20:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h26][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_6_folded_hist = + {_RANDOM[8'h26][31:28], _RANDOM[8'h27][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h27][11:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h27][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h27][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_2_folded_hist = + {_RANDOM[8'h27][31:28], _RANDOM[8'h28][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h28][14:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h28][22:15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_17_folded_hist = + {_RANDOM[8'h28][31:23], _RANDOM[8'h29][1:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h29][12:2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h29][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h29][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_13_folded_hist = + {_RANDOM[8'h29][31:28], _RANDOM[8'h2A][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h2A][8:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h2A][16:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h2A][25:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_9_folded_hist = + {_RANDOM[8'h2A][31:26], _RANDOM[8'h2B][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h2B][8:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h2B][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h2B][24:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h2B][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h2C][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h2C][15:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h2C][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_1_folded_hist = + {_RANDOM[8'h2C][31:24], _RANDOM[8'h2D][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h2D][10:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h2D][21:11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_16_folded_hist = + {_RANDOM[8'h2D][31:22], _RANDOM[8'h2E][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h2E][7:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h2E][15:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h2E][24:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h2E][28:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_11_folded_hist = + {_RANDOM[8'h2E][31:29], _RANDOM[8'h2F][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h2F][13:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h2F][20:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h2F][28:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_7_folded_hist = + {_RANDOM[8'h2F][31:29], _RANDOM[8'h30][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h30][12:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h30][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h30][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_3_folded_hist = + {_RANDOM[8'h30][31:28], _RANDOM[8'h31][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h31][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h31][22:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h31][30:23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s2_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h36][29:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_16_folded_hist = + {_RANDOM[8'h36][31:30], _RANDOM[8'h37][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h37][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h37][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_13_folded_hist = + {_RANDOM[8'h37][31:24], _RANDOM[8'h38][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h38][4:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h38][12:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h38][21:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h38][28:22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_8_folded_hist = + {_RANDOM[8'h38][31:29], _RANDOM[8'h39][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h39][11:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h39][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h39][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_4_folded_hist = + {_RANDOM[8'h39][31:28], _RANDOM[8'h3A][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h3A][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h3A][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h3A][30:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_0_folded_hist = {_RANDOM[8'h3A][31], _RANDOM[8'h3B][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h3B][17:7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h3B][28:18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_15_folded_hist = + {_RANDOM[8'h3B][31:29], _RANDOM[8'h3C][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h3C][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h3C][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h3C][24:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_11_folded_hist = + {_RANDOM[8'h3C][31:25], _RANDOM[8'h3D][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h3D][9:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h3D][16:10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h3D][24:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h3D][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h3E][8:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h3E][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h3E][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h3E][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h3F][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h3F][18:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h3F][26:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_17_folded_hist = + {_RANDOM[8'h3F][31:27], _RANDOM[8'h40][5:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h40][16:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h40][23:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h40][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h41][8:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h41][12:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h41][20:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h41][29:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_9_folded_hist = + {_RANDOM[8'h41][31:30], _RANDOM[8'h42][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h42][12:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h42][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h42][28:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_5_folded_hist = + {_RANDOM[8'h42][31:29], _RANDOM[8'h43][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h43][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h43][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h43][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_1_folded_hist = + {_RANDOM[8'h43][31:28], _RANDOM[8'h44][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h44][14:7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s3_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h49][13:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h49][24:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h49][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h4A][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h4A][16:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h4A][20:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h4A][28:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_10_folded_hist = + {_RANDOM[8'h4A][31:29], _RANDOM[8'h4B][5:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h4B][12:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h4B][20:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h4B][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_6_folded_hist = + {_RANDOM[8'h4B][31:28], _RANDOM[8'h4C][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h4C][11:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h4C][19:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h4C][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_2_folded_hist = + {_RANDOM[8'h4C][31:28], _RANDOM[8'h4D][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h4D][14:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h4D][22:15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_17_folded_hist = + {_RANDOM[8'h4D][31:23], _RANDOM[8'h4E][1:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h4E][12:2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h4E][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h4E][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_13_folded_hist = + {_RANDOM[8'h4E][31:28], _RANDOM[8'h4F][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h4F][8:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h4F][16:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h4F][25:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_9_folded_hist = + {_RANDOM[8'h4F][31:26], _RANDOM[8'h50][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h50][8:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h50][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h50][24:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h50][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h51][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h51][15:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h51][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_1_folded_hist = + {_RANDOM[8'h51][31:24], _RANDOM[8'h52][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h52][10:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h52][21:11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_16_folded_hist = + {_RANDOM[8'h52][31:22], _RANDOM[8'h53][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h53][7:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h53][15:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h53][24:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h53][28:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_11_folded_hist = + {_RANDOM[8'h53][31:29], _RANDOM[8'h54][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h54][13:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h54][20:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h54][28:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_7_folded_hist = + {_RANDOM[8'h54][31:29], _RANDOM[8'h55][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h55][12:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h55][19:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h55][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_3_folded_hist = + {_RANDOM[8'h55][31:28], _RANDOM[8'h56][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h56][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h56][22:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h56][30:23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s0_last_br_num_oh_reg_dup_1 = _RANDOM[8'h57][4:2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73] + s0_last_br_num_oh_reg_dup_2 = _RANDOM[8'h57][7:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73] + s0_last_br_num_oh_reg_dup_3 = _RANDOM[8'h57][10:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73] + s1_last_br_num_oh_dup_1 = _RANDOM[8'h57][16:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73, :293:40] + s1_last_br_num_oh_dup_2 = _RANDOM[8'h57][19:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73, :293:40] + s1_last_br_num_oh_dup_3 = _RANDOM[8'h57][22:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73, :293:40] + s2_last_br_num_oh_dup_1 = _RANDOM[8'h57][28:26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73, :294:40] + s2_last_br_num_oh_dup_2 = _RANDOM[8'h57][31:29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :292:73, :294:40] + s2_last_br_num_oh_dup_3 = _RANDOM[8'h58][2:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :294:40] + s3_last_br_num_oh_dup_1 = _RANDOM[8'h58][8:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :294:40, :295:40] + s3_last_br_num_oh_dup_2 = _RANDOM[8'h58][11:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :294:40, :295:40] + s3_last_br_num_oh_dup_3 = _RANDOM[8'h58][14:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :294:40, :295:40] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = _RANDOM[8'h59][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = _RANDOM[8'h59][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = _RANDOM[8'h59][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = _RANDOM[8'h59][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = _RANDOM[8'h59][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = _RANDOM[8'h59][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = _RANDOM[8'h59][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = _RANDOM[8'h59][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = _RANDOM[8'h59][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = _RANDOM[8'h59][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = _RANDOM[8'h59][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = _RANDOM[8'h59][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = _RANDOM[8'h59][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = _RANDOM[8'h59][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = _RANDOM[8'h59][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = _RANDOM[8'h59][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = _RANDOM[8'h59][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = _RANDOM[8'h59][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = _RANDOM[8'h59][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = _RANDOM[8'h59][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = _RANDOM[8'h59][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = _RANDOM[8'h59][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = _RANDOM[8'h59][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = _RANDOM[8'h59][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = _RANDOM[8'h59][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = _RANDOM[8'h5A][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = _RANDOM[8'h5A][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = _RANDOM[8'h5A][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = _RANDOM[8'h5A][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = _RANDOM[8'h5A][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = _RANDOM[8'h5A][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = _RANDOM[8'h5A][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = _RANDOM[8'h5A][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = _RANDOM[8'h5A][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = _RANDOM[8'h5A][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = _RANDOM[8'h5A][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = _RANDOM[8'h5A][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = _RANDOM[8'h5A][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = _RANDOM[8'h5A][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = _RANDOM[8'h5A][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = _RANDOM[8'h5A][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = _RANDOM[8'h5A][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = _RANDOM[8'h5A][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = _RANDOM[8'h5A][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = _RANDOM[8'h5A][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = _RANDOM[8'h5A][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = _RANDOM[8'h5A][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = _RANDOM[8'h5A][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = _RANDOM[8'h5A][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = _RANDOM[8'h5A][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = _RANDOM[8'h5A][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = _RANDOM[8'h5A][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = _RANDOM[8'h5A][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = _RANDOM[8'h5A][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = _RANDOM[8'h5A][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = _RANDOM[8'h5A][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = _RANDOM[8'h5A][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = _RANDOM[8'h5B][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = _RANDOM[8'h5B][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = _RANDOM[8'h5B][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = _RANDOM[8'h5B][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = _RANDOM[8'h5B][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = _RANDOM[8'h5B][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = _RANDOM[8'h5B][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = _RANDOM[8'h5B][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = _RANDOM[8'h5B][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = _RANDOM[8'h5B][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = _RANDOM[8'h5B][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = _RANDOM[8'h5B][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = _RANDOM[8'h5B][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = _RANDOM[8'h5B][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = _RANDOM[8'h5B][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :298:85] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5C][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5C][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5C][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5C][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5C][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5C][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5C][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5C][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5C][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5C][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5C][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5C][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5C][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5C][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5C][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5C][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5C][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5C][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5C][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5C][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5C][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5C][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5C][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5C][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5D][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5D][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5D][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5D][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5D][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5D][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5D][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5D][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5D][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5D][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5D][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5D][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5D][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5D][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h5D][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h5D][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h5D][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h5D][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h5D][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h5D][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h5D][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h5D][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h5D][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h5D][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h5D][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h5D][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h5D][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h5D][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h5D][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h5D][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h5D][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h5E][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h5E][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h5E][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h5E][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h5E][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h5E][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h5E][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h5E][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h5E][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h5E][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h5E][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h5E][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h5E][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h5E][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h5E][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :299:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5F][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5F][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5F][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5F][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5F][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5F][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5F][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5F][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5F][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5F][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5F][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5F][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5F][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5F][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5F][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5F][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5F][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5F][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5F][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5F][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5F][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5F][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5F][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5F][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h60][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h60][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h60][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h60][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h60][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h60][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h60][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h60][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h60][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h60][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h60][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h60][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h60][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h60][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h60][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h60][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h60][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h60][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h60][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h60][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h60][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h60][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h60][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h60][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h60][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h60][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h60][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h60][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h60][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h60][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h60][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h61][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h61][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h61][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h61][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h61][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h61][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h61][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h61][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h61][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h61][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h61][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h61][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h61][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h61][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h61][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :300:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h62][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h62][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h62][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h62][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h62][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h62][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h62][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h62][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h62][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h62][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h62][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h62][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h62][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h62][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h62][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h62][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h62][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h62][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h62][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h62][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h62][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h62][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h62][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h62][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h63][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h63][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h63][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h63][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h63][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h63][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h63][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h63][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h63][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h63][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h63][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h63][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h63][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h63][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h63][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h63][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h63][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h63][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h63][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h63][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h63][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h63][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h63][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h63][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h63][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h63][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h63][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h63][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h63][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h63][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h63][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h64][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h64][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h64][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h64][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h64][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h64][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h64][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h64][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h64][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h64][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h64][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h64][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h64][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h64][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h64][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] + ghv_0 = _RANDOM[8'h64][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_1 = _RANDOM[8'h64][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_2 = _RANDOM[8'h64][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_3 = _RANDOM[8'h64][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_4 = _RANDOM[8'h64][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_5 = _RANDOM[8'h64][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_6 = _RANDOM[8'h64][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_7 = _RANDOM[8'h64][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_8 = _RANDOM[8'h64][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_9 = _RANDOM[8'h64][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_10 = _RANDOM[8'h64][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_11 = _RANDOM[8'h64][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_12 = _RANDOM[8'h64][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_13 = _RANDOM[8'h64][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_14 = _RANDOM[8'h64][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_15 = _RANDOM[8'h64][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_16 = _RANDOM[8'h64][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46, :312:20] + ghv_17 = _RANDOM[8'h65][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_18 = _RANDOM[8'h65][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_19 = _RANDOM[8'h65][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_20 = _RANDOM[8'h65][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_21 = _RANDOM[8'h65][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_22 = _RANDOM[8'h65][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_23 = _RANDOM[8'h65][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_24 = _RANDOM[8'h65][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_25 = _RANDOM[8'h65][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_26 = _RANDOM[8'h65][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_27 = _RANDOM[8'h65][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_28 = _RANDOM[8'h65][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_29 = _RANDOM[8'h65][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_30 = _RANDOM[8'h65][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_31 = _RANDOM[8'h65][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_32 = _RANDOM[8'h65][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_33 = _RANDOM[8'h65][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_34 = _RANDOM[8'h65][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_35 = _RANDOM[8'h65][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_36 = _RANDOM[8'h65][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_37 = _RANDOM[8'h65][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_38 = _RANDOM[8'h65][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_39 = _RANDOM[8'h65][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_40 = _RANDOM[8'h65][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_41 = _RANDOM[8'h65][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_42 = _RANDOM[8'h65][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_43 = _RANDOM[8'h65][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_44 = _RANDOM[8'h65][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_45 = _RANDOM[8'h65][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_46 = _RANDOM[8'h65][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_47 = _RANDOM[8'h65][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_48 = _RANDOM[8'h65][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_49 = _RANDOM[8'h66][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_50 = _RANDOM[8'h66][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_51 = _RANDOM[8'h66][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_52 = _RANDOM[8'h66][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_53 = _RANDOM[8'h66][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_54 = _RANDOM[8'h66][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_55 = _RANDOM[8'h66][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_56 = _RANDOM[8'h66][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_57 = _RANDOM[8'h66][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_58 = _RANDOM[8'h66][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_59 = _RANDOM[8'h66][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_60 = _RANDOM[8'h66][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_61 = _RANDOM[8'h66][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_62 = _RANDOM[8'h66][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_63 = _RANDOM[8'h66][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_64 = _RANDOM[8'h66][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_65 = _RANDOM[8'h66][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_66 = _RANDOM[8'h66][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_67 = _RANDOM[8'h66][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_68 = _RANDOM[8'h66][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_69 = _RANDOM[8'h66][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_70 = _RANDOM[8'h66][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_71 = _RANDOM[8'h66][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_72 = _RANDOM[8'h66][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_73 = _RANDOM[8'h66][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_74 = _RANDOM[8'h66][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_75 = _RANDOM[8'h66][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_76 = _RANDOM[8'h66][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_77 = _RANDOM[8'h66][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_78 = _RANDOM[8'h66][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_79 = _RANDOM[8'h66][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_80 = _RANDOM[8'h66][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_81 = _RANDOM[8'h67][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_82 = _RANDOM[8'h67][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_83 = _RANDOM[8'h67][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_84 = _RANDOM[8'h67][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_85 = _RANDOM[8'h67][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_86 = _RANDOM[8'h67][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_87 = _RANDOM[8'h67][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_88 = _RANDOM[8'h67][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_89 = _RANDOM[8'h67][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_90 = _RANDOM[8'h67][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_91 = _RANDOM[8'h67][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_92 = _RANDOM[8'h67][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_93 = _RANDOM[8'h67][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_94 = _RANDOM[8'h67][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_95 = _RANDOM[8'h67][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_96 = _RANDOM[8'h67][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_97 = _RANDOM[8'h67][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_98 = _RANDOM[8'h67][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_99 = _RANDOM[8'h67][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_100 = _RANDOM[8'h67][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_101 = _RANDOM[8'h67][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_102 = _RANDOM[8'h67][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_103 = _RANDOM[8'h67][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_104 = _RANDOM[8'h67][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_105 = _RANDOM[8'h67][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_106 = _RANDOM[8'h67][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_107 = _RANDOM[8'h67][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_108 = _RANDOM[8'h67][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_109 = _RANDOM[8'h67][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_110 = _RANDOM[8'h67][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_111 = _RANDOM[8'h67][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_112 = _RANDOM[8'h67][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_113 = _RANDOM[8'h68][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_114 = _RANDOM[8'h68][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_115 = _RANDOM[8'h68][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_116 = _RANDOM[8'h68][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_117 = _RANDOM[8'h68][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_118 = _RANDOM[8'h68][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_119 = _RANDOM[8'h68][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_120 = _RANDOM[8'h68][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_121 = _RANDOM[8'h68][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_122 = _RANDOM[8'h68][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_123 = _RANDOM[8'h68][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_124 = _RANDOM[8'h68][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_125 = _RANDOM[8'h68][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_126 = _RANDOM[8'h68][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_127 = _RANDOM[8'h68][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_128 = _RANDOM[8'h68][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_129 = _RANDOM[8'h68][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_130 = _RANDOM[8'h68][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_131 = _RANDOM[8'h68][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_132 = _RANDOM[8'h68][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_133 = _RANDOM[8'h68][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_134 = _RANDOM[8'h68][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_135 = _RANDOM[8'h68][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_136 = _RANDOM[8'h68][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_137 = _RANDOM[8'h68][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_138 = _RANDOM[8'h68][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_139 = _RANDOM[8'h68][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_140 = _RANDOM[8'h68][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_141 = _RANDOM[8'h68][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_142 = _RANDOM[8'h68][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_143 = _RANDOM[8'h68][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_144 = _RANDOM[8'h68][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_145 = _RANDOM[8'h69][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_146 = _RANDOM[8'h69][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_147 = _RANDOM[8'h69][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_148 = _RANDOM[8'h69][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_149 = _RANDOM[8'h69][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_150 = _RANDOM[8'h69][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_151 = _RANDOM[8'h69][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_152 = _RANDOM[8'h69][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_153 = _RANDOM[8'h69][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_154 = _RANDOM[8'h69][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_155 = _RANDOM[8'h69][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_156 = _RANDOM[8'h69][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_157 = _RANDOM[8'h69][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_158 = _RANDOM[8'h69][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_159 = _RANDOM[8'h69][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_160 = _RANDOM[8'h69][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_161 = _RANDOM[8'h69][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_162 = _RANDOM[8'h69][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_163 = _RANDOM[8'h69][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_164 = _RANDOM[8'h69][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_165 = _RANDOM[8'h69][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_166 = _RANDOM[8'h69][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_167 = _RANDOM[8'h69][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_168 = _RANDOM[8'h69][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_169 = _RANDOM[8'h69][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_170 = _RANDOM[8'h69][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_171 = _RANDOM[8'h69][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_172 = _RANDOM[8'h69][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_173 = _RANDOM[8'h69][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_174 = _RANDOM[8'h69][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_175 = _RANDOM[8'h69][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_176 = _RANDOM[8'h69][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_177 = _RANDOM[8'h6A][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_178 = _RANDOM[8'h6A][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_179 = _RANDOM[8'h6A][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_180 = _RANDOM[8'h6A][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_181 = _RANDOM[8'h6A][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_182 = _RANDOM[8'h6A][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_183 = _RANDOM[8'h6A][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_184 = _RANDOM[8'h6A][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_185 = _RANDOM[8'h6A][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_186 = _RANDOM[8'h6A][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_187 = _RANDOM[8'h6A][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_188 = _RANDOM[8'h6A][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_189 = _RANDOM[8'h6A][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_190 = _RANDOM[8'h6A][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_191 = _RANDOM[8'h6A][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_192 = _RANDOM[8'h6A][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_193 = _RANDOM[8'h6A][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_194 = _RANDOM[8'h6A][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_195 = _RANDOM[8'h6A][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_196 = _RANDOM[8'h6A][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_197 = _RANDOM[8'h6A][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_198 = _RANDOM[8'h6A][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_199 = _RANDOM[8'h6A][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_200 = _RANDOM[8'h6A][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_201 = _RANDOM[8'h6A][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_202 = _RANDOM[8'h6A][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_203 = _RANDOM[8'h6A][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_204 = _RANDOM[8'h6A][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_205 = _RANDOM[8'h6A][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_206 = _RANDOM[8'h6A][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_207 = _RANDOM[8'h6A][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_208 = _RANDOM[8'h6A][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_209 = _RANDOM[8'h6B][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_210 = _RANDOM[8'h6B][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_211 = _RANDOM[8'h6B][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_212 = _RANDOM[8'h6B][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_213 = _RANDOM[8'h6B][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_214 = _RANDOM[8'h6B][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_215 = _RANDOM[8'h6B][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_216 = _RANDOM[8'h6B][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_217 = _RANDOM[8'h6B][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_218 = _RANDOM[8'h6B][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_219 = _RANDOM[8'h6B][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_220 = _RANDOM[8'h6B][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_221 = _RANDOM[8'h6B][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_222 = _RANDOM[8'h6B][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_223 = _RANDOM[8'h6B][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_224 = _RANDOM[8'h6B][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_225 = _RANDOM[8'h6B][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_226 = _RANDOM[8'h6B][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_227 = _RANDOM[8'h6B][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_228 = _RANDOM[8'h6B][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_229 = _RANDOM[8'h6B][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_230 = _RANDOM[8'h6B][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_231 = _RANDOM[8'h6B][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_232 = _RANDOM[8'h6B][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_233 = _RANDOM[8'h6B][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_234 = _RANDOM[8'h6B][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_235 = _RANDOM[8'h6B][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_236 = _RANDOM[8'h6B][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_237 = _RANDOM[8'h6B][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_238 = _RANDOM[8'h6B][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_239 = _RANDOM[8'h6B][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_240 = _RANDOM[8'h6B][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_241 = _RANDOM[8'h6C][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_242 = _RANDOM[8'h6C][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_243 = _RANDOM[8'h6C][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_244 = _RANDOM[8'h6C][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_245 = _RANDOM[8'h6C][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_246 = _RANDOM[8'h6C][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_247 = _RANDOM[8'h6C][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_248 = _RANDOM[8'h6C][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_249 = _RANDOM[8'h6C][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_250 = _RANDOM[8'h6C][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_251 = _RANDOM[8'h6C][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_252 = _RANDOM[8'h6C][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_253 = _RANDOM[8'h6C][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_254 = _RANDOM[8'h6C][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + ghv_255 = _RANDOM[8'h6C][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20] + s0_ghist_ptr_reg_dup_0_flag = _RANDOM[8'h6C][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20, :323:63] + s0_ghist_ptr_reg_dup_0_value = _RANDOM[8'h6C][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20, :323:63] + s0_ghist_ptr_reg_dup_1_flag = _RANDOM[8'h6C][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20, :323:63] + s0_ghist_ptr_reg_dup_1_value = {_RANDOM[8'h6C][31:25], _RANDOM[8'h6D][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :312:20, :323:63] + s0_ghist_ptr_reg_dup_2_flag = _RANDOM[8'h6D][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_2_value = _RANDOM[8'h6D][9:2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_3_flag = _RANDOM[8'h6D][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_3_value = _RANDOM[8'h6D][18:11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s1_ghist_ptr_dup_0_flag = _RANDOM[8'h6D][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63, :324:35] + s1_ghist_ptr_dup_0_value = _RANDOM[8'h6D][27:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63, :324:35] + s1_ghist_ptr_dup_1_flag = _RANDOM[8'h6D][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63, :324:35] + s1_ghist_ptr_dup_1_value = {_RANDOM[8'h6D][31:29], _RANDOM[8'h6E][4:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63, :324:35] + s1_ghist_ptr_dup_2_flag = _RANDOM[8'h6E][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_2_value = _RANDOM[8'h6E][13:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_3_flag = _RANDOM[8'h6E][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_3_value = _RANDOM[8'h6E][22:15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s2_ghist_ptr_dup_0_flag = _RANDOM[8'h6E][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, :325:35] + s2_ghist_ptr_dup_0_value = _RANDOM[8'h6E][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, :325:35] + s2_ghist_ptr_dup_1_flag = _RANDOM[8'h6F][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_1_value = _RANDOM[8'h6F][8:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_2_flag = _RANDOM[8'h6F][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_2_value = _RANDOM[8'h6F][17:10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_3_flag = _RANDOM[8'h6F][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_3_value = _RANDOM[8'h6F][26:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s3_ghist_ptr_dup_0_flag = _RANDOM[8'h6F][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, :326:35] + s3_ghist_ptr_dup_0_value = {_RANDOM[8'h6F][31:28], _RANDOM[8'h70][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, :326:35] + s3_ghist_ptr_dup_1_flag = _RANDOM[8'h70][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_1_value = _RANDOM[8'h70][12:5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_2_flag = _RANDOM[8'h70][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_2_value = _RANDOM[8'h70][21:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_3_flag = _RANDOM[8'h70][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_3_value = _RANDOM[8'h70][30:23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + do_redirect_dup_next_valid_last_r = _RANDOM[8'h70][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + do_redirect_dup_next_bits_r_level = _RANDOM[8'h71][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pc = + {_RANDOM[8'h71][31:23], _RANDOM[8'h72]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[8'h73][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[8'h73][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[8'h73][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_ssp = _RANDOM[8'h73][9:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_sctr = _RANDOM[8'h73][11:10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[8'h73][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[8'h73][17:13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[8'h73][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[8'h73][23:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[8'h73][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_NOS_value = _RANDOM[8'h73][29:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist = + _RANDOM[8'h75][17:7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist = + _RANDOM[8'h75][28:18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist = + {_RANDOM[8'h75][31:29], _RANDOM[8'h76][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist = + _RANDOM[8'h76][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist = + _RANDOM[8'h76][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist = + _RANDOM[8'h76][24:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist = + {_RANDOM[8'h76][31:25], _RANDOM[8'h77][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist = + _RANDOM[8'h77][9:1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist = + _RANDOM[8'h77][16:10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist = + _RANDOM[8'h77][24:17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist = + _RANDOM[8'h77][31:25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist = + _RANDOM[8'h78][8:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist = + _RANDOM[8'h78][15:9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist = + _RANDOM[8'h78][23:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist = + _RANDOM[8'h78][31:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist = + _RANDOM[8'h79][7:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist = + _RANDOM[8'h79][18:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist = + _RANDOM[8'h79][26:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 = _RANDOM[8'h79][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 = _RANDOM[8'h79][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 = _RANDOM[8'h79][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3 = _RANDOM[8'h79][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 = _RANDOM[8'h79][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 = _RANDOM[8'h7A][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2 = _RANDOM[8'h7A][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 = _RANDOM[8'h7A][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 = _RANDOM[8'h7A][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 = _RANDOM[8'h7A][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3 = _RANDOM[8'h7A][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 = _RANDOM[8'h7A][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 = _RANDOM[8'h7A][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 = _RANDOM[8'h7A][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3 = _RANDOM[8'h7A][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 = _RANDOM[8'h7A][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 = _RANDOM[8'h7A][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 = _RANDOM[8'h7A][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3 = _RANDOM[8'h7A][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 = _RANDOM[8'h7A][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 = _RANDOM[8'h7A][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 = _RANDOM[8'h7A][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3 = _RANDOM[8'h7A][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH = _RANDOM[8'h7A][21:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag = _RANDOM[8'h7A][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value = + {_RANDOM[8'h7A][31:27], _RANDOM[8'h7B][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_target = + {_RANDOM[8'h7B][31:27], _RANDOM[8'h7C], _RANDOM[8'h7D][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_taken = _RANDOM[8'h7D][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_shift = _RANDOM[8'h7D][7:6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist = _RANDOM[8'h7D][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, utility/src/main/scala/utility/BitUtils.scala:33:27] + previous_s1_pred_info_hit_0 = _RANDOM[8'h7F][23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_hit_1 = _RANDOM[8'h7F][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_hit_2 = _RANDOM[8'h7F][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_hit_3 = _RANDOM[8'h7F][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_target_0 = + {_RANDOM[8'h7F][31:27], _RANDOM[8'h80], _RANDOM[8'h81][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_target_1 = {_RANDOM[8'h81][31:4], _RANDOM[8'h82][12:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_target_2 = {_RANDOM[8'h82][31:13], _RANDOM[8'h83][21:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_target_3 = {_RANDOM[8'h83][31:22], _RANDOM[8'h84][30:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_0_0 = _RANDOM[8'h84][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_0_1 = _RANDOM[8'h85][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_0_2 = _RANDOM[8'h85][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_1_0 = _RANDOM[8'h85][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_1_1 = _RANDOM[8'h85][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_1_2 = _RANDOM[8'h85][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_2_0 = _RANDOM[8'h85][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_2_1 = _RANDOM[8'h85][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_2_2 = _RANDOM[8'h85][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_3_0 = _RANDOM[8'h85][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_3_1 = _RANDOM[8'h85][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_lastBrPosOH_3_2 = _RANDOM[8'h85][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_taken_0 = _RANDOM[8'h85][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_taken_1 = _RANDOM[8'h85][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_taken_2 = _RANDOM[8'h85][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_taken_3 = _RANDOM[8'h85][14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_0_0 = _RANDOM[8'h85][15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_0_1 = _RANDOM[8'h85][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_1_0 = _RANDOM[8'h85][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_1_1 = _RANDOM[8'h85][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_2_0 = _RANDOM[8'h85][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_2_1 = _RANDOM[8'h85][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_3_0 = _RANDOM[8'h85][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_takenMask_3_1 = _RANDOM[8'h85][22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_cfiIndex_0 = _RANDOM[8'h85][26:23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_cfiIndex_1 = _RANDOM[8'h85][30:27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_cfiIndex_2 = {_RANDOM[8'h85][31], _RANDOM[8'h86][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s1_pred_info_cfiIndex_3 = _RANDOM[8'h86][6:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40] + previous_s2_pred_pc_0 = {_RANDOM[8'h86][31:7], _RANDOM[8'h87][15:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :601:40, :674:35] + previous_s2_pred_pc_1 = {_RANDOM[8'h87][31:16], _RANDOM[8'h88][24:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_pc_2 = + {_RANDOM[8'h88][31:25], _RANDOM[8'h89], _RANDOM[8'h8A][1:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_pc_3 = {_RANDOM[8'h8A][31:2], _RANDOM[8'h8B][10:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_0 = _RANDOM[8'h8B][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_1 = _RANDOM[8'h8B][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_slot_valids_0 = _RANDOM[8'h8B][28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_slot_valids_1 = _RANDOM[8'h8B][29]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_0_targets_0 = - {_RANDOM[8'h8A][31:26], _RANDOM[8'h8B], _RANDOM[8'h8C][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h8B][31:30], _RANDOM[8'h8C], _RANDOM[8'h8D][6:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_0_targets_1 = - {_RANDOM[8'h8C][31:1], _RANDOM[8'h8D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h8D][31:7], _RANDOM[8'h8E][15:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_0_fallThroughAddr = - {_RANDOM[8'h8E][31:23], _RANDOM[8'h8F][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_is_br_sharing = _RANDOM[8'h90][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_0_hit = _RANDOM[8'h90][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_0 = _RANDOM[8'h90][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_1 = _RANDOM[8'h90][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_slot_valids_0 = _RANDOM[8'h90][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_slot_valids_1 = _RANDOM[8'h90][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h90][31:1], _RANDOM[8'h91][9:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_is_br_sharing = _RANDOM[8'h91][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_0_hit = _RANDOM[8'h91][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_0 = _RANDOM[8'h91][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_1 = _RANDOM[8'h91][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_slot_valids_0 = _RANDOM[8'h91][20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_slot_valids_1 = _RANDOM[8'h91][21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_1_targets_0 = - {_RANDOM[8'h90][31:10], _RANDOM[8'h91][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h91][31:22], _RANDOM[8'h92][30:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_1_targets_1 = - {_RANDOM[8'h91][31:17], _RANDOM[8'h92][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h92][31], _RANDOM[8'h93], _RANDOM[8'h94][7:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_1_fallThroughAddr = - {_RANDOM[8'h94][31:7], _RANDOM[8'h95][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_is_br_sharing = _RANDOM[8'h95][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_1_hit = _RANDOM[8'h95][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_0 = _RANDOM[8'h95][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_1 = _RANDOM[8'h95][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_slot_valids_0 = _RANDOM[8'h95][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_slot_valids_1 = _RANDOM[8'h95][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h95][31:25], _RANDOM[8'h96], _RANDOM[8'h97][1:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_is_br_sharing = _RANDOM[8'h97][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_1_hit = _RANDOM[8'h97][9]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_0 = _RANDOM[8'h97][10]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_1 = _RANDOM[8'h97][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_slot_valids_0 = _RANDOM[8'h97][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_slot_valids_1 = _RANDOM[8'h97][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_2_targets_0 = - {_RANDOM[8'h95][31:26], _RANDOM[8'h96], _RANDOM[8'h97][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_targets_1 = - {_RANDOM[8'h97][31:1], _RANDOM[8'h98][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h97][31:14], _RANDOM[8'h98][22:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_targets_1 = {_RANDOM[8'h98][31:23], _RANDOM[8'h99]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_2_fallThroughAddr = - {_RANDOM[8'h99][31:23], _RANDOM[8'h9A][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_is_br_sharing = _RANDOM[8'h9B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_2_hit = _RANDOM[8'h9B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_0 = _RANDOM[8'h9B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_1 = _RANDOM[8'h9B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_slot_valids_0 = _RANDOM[8'h9B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_slot_valids_1 = _RANDOM[8'h9B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h9B][31:17], _RANDOM[8'h9C][25:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_is_br_sharing = _RANDOM[8'h9D][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_2_hit = _RANDOM[8'h9D][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_0 = _RANDOM[8'h9D][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_1 = _RANDOM[8'h9D][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_slot_valids_0 = _RANDOM[8'h9D][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_slot_valids_1 = _RANDOM[8'h9D][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_3_targets_0 = - {_RANDOM[8'h9B][31:10], _RANDOM[8'h9C][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h9D][31:6], _RANDOM[8'h9E][14:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_3_targets_1 = - {_RANDOM[8'h9C][31:17], _RANDOM[8'h9D][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + {_RANDOM[8'h9E][31:15], _RANDOM[8'h9F][23:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] previous_s2_pred_full_pred_3_fallThroughAddr = - {_RANDOM[8'h9F][31:7], _RANDOM[8'hA0][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_is_br_sharing = _RANDOM[8'hA0][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - previous_s2_pred_full_pred_3_hit = _RANDOM[8'hA0][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 - s2_ftq_idx_flag = _RANDOM[8'hA0][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29 - s2_ftq_idx_value = _RANDOM[8'hA0][28:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29 - s3_ftq_idx_flag = _RANDOM[8'hA0][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29 - s3_ftq_idx_value = {_RANDOM[8'hA0][31:30], _RANDOM[8'hA1][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29 - predictors_io_update_REG_valid = _RANDOM[8'hA1][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34 - predictors_io_update_REG_bits_pc = {_RANDOM[8'hA1][31:5], _RANDOM[8'hA2][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist = - _RANDOM[8'hA2][22:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist = - {_RANDOM[8'hA2][31:23], _RANDOM[8'hA3][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist = - _RANDOM[8'hA3][8:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist = - _RANDOM[8'hA3][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist = - _RANDOM[8'hA3][25:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist = - _RANDOM[8'hA3][29:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist = - {_RANDOM[8'hA3][31:30], _RANDOM[8'hA4][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist = - _RANDOM[8'hA4][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist = - _RANDOM[8'hA4][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist = - _RANDOM[8'hA4][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist = - {_RANDOM[8'hA4][31:30], _RANDOM[8'hA5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist = - _RANDOM[8'hA5][13:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist = - _RANDOM[8'hA5][20:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist = - _RANDOM[8'hA5][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist = - {_RANDOM[8'hA5][31:29], _RANDOM[8'hA6][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist = - _RANDOM[8'hA6][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist = - _RANDOM[8'hA6][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_valid = _RANDOM[8'hAA][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset = _RANDOM[8'hAA][7:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower = _RANDOM[8'hAA][19:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat = _RANDOM[8'hAA][21:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing = _RANDOM[8'hAA][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid = _RANDOM[8'hAA][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_offset = _RANDOM[8'hAA][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_lower = - {_RANDOM[8'hAA][31:28], _RANDOM[8'hAB][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat = _RANDOM[8'hAB][17:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing = _RANDOM[8'hAB][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_tailSlot_valid = _RANDOM[8'hAB][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_pftAddr = _RANDOM[8'hAB][23:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_carry = _RANDOM[8'hAB][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_isCall = _RANDOM[8'hAB][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_isRet = _RANDOM[8'hAB][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_isJalr = _RANDOM[8'hAB][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call = _RANDOM[8'hAB][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_always_taken_0 = _RANDOM[8'hAB][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_ftb_entry_always_taken_1 = _RANDOM[8'hAB][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_cfi_idx_valid = _RANDOM[8'hAB][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_cfi_idx_bits = _RANDOM[8'hAC][3:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_br_taken_mask_0 = _RANDOM[8'hAC][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_br_taken_mask_1 = _RANDOM[8'hAC][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_jmp_taken = _RANDOM[8'hAC][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_mispred_mask_0 = _RANDOM[8'hAC][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_mispred_mask_1 = _RANDOM[8'hAC][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_mispred_mask_2 = _RANDOM[8'hAC][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_old_entry = _RANDOM[8'hAC][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_meta = - {_RANDOM[8'hAC][31:17], - _RANDOM[8'hAD], - _RANDOM[8'hAE], + {_RANDOM[8'hA1][31:9], _RANDOM[8'hA2][17:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_is_br_sharing = _RANDOM[8'hA2][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + previous_s2_pred_full_pred_3_hit = _RANDOM[8'hA2][25]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35] + s2_ftq_idx_flag = _RANDOM[8'hA2][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35, :709:29] + s2_ftq_idx_value = {_RANDOM[8'hA2][31:27], _RANDOM[8'hA3][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :674:35, :709:29] + s3_ftq_idx_flag = _RANDOM[8'hA3][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29, :710:29] + s3_ftq_idx_value = _RANDOM[8'hA3][7:2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29, :710:29] + predictors_io_update_valid_REG = _RANDOM[8'hA3][8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29, :728:40] + predictors_io_update_bits_r_pc = {_RANDOM[8'hA3][31:9], _RANDOM[8'hA4][17:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist = + _RANDOM[8'hA4][28:18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist = + {_RANDOM[8'hA4][31:29], _RANDOM[8'hA5][7:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist = + _RANDOM[8'hA5][14:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist = + _RANDOM[8'hA5][22:15]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist = + _RANDOM[8'hA5][31:23]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist = + _RANDOM[8'hA6][3:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist = + _RANDOM[8'hA6][11:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist = + _RANDOM[8'hA6][20:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist = + _RANDOM[8'hA6][27:21]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist = + {_RANDOM[8'hA6][31:28], _RANDOM[8'hA7][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist = + _RANDOM[8'hA7][10:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist = + _RANDOM[8'hA7][19:11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist = + _RANDOM[8'hA7][26:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist = + {_RANDOM[8'hA7][31:27], _RANDOM[8'hA8][2:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist = + _RANDOM[8'hA8][10:3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist = + _RANDOM[8'hA8][18:11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist = + _RANDOM[8'hA8][29:19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_valid = _RANDOM[8'hAC][11]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_offset = _RANDOM[8'hAC][15:12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_lower = _RANDOM[8'hAC][27:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat = _RANDOM[8'hAC][29:28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing = _RANDOM[8'hAC][30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_brSlots_0_valid = _RANDOM[8'hAC][31]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_offset = _RANDOM[8'hAD][3:0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_lower = _RANDOM[8'hAD][23:4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat = _RANDOM[8'hAD][25:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_sharing = _RANDOM[8'hAD][26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_tailSlot_valid = _RANDOM[8'hAD][27]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_pftAddr = _RANDOM[8'hAD][31:28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_carry = _RANDOM[8'hAE][0]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_isCall = _RANDOM[8'hAE][1]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_isRet = _RANDOM[8'hAE][2]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_isJalr = _RANDOM[8'hAE][3]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call = _RANDOM[8'hAE][4]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_always_taken_0 = _RANDOM[8'hAE][5]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_ftb_entry_always_taken_1 = _RANDOM[8'hAE][6]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_cfi_idx_valid = _RANDOM[8'hAE][7]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_cfi_idx_bits = _RANDOM[8'hAE][11:8]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_br_taken_mask_0 = _RANDOM[8'hAE][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_br_taken_mask_1 = _RANDOM[8'hAE][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_jmp_taken = _RANDOM[8'hAE][16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_mispred_mask_0 = _RANDOM[8'hAE][17]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_mispred_mask_1 = _RANDOM[8'hAE][18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_mispred_mask_2 = _RANDOM[8'hAE][19]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_old_entry = _RANDOM[8'hAE][24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_meta = + {_RANDOM[8'hAE][31:25], _RANDOM[8'hAF], _RANDOM[8'hB0], _RANDOM[8'hB1], _RANDOM[8'hB2], - _RANDOM[8'hB3][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 - predictors_io_update_REG_bits_full_target = - {_RANDOM[8'hB3][31:12], _RANDOM[8'hB4][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + _RANDOM[8'hB3], + _RANDOM[8'hB4], + _RANDOM[8'hB5][23:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + predictors_io_update_bits_r_full_target = + {_RANDOM[8'hB5][31:24], _RANDOM[8'hB6], _RANDOM[8'hB7][0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :729:41] + io_perf_0_value_REG = _RANDOM[8'hCF][18:13]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_0_value_REG_1 = _RANDOM[8'hCF][24:19]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_1_value_REG = _RANDOM[8'hCF][30:25]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_1_value_REG_1 = {_RANDOM[8'hCF][31], _RANDOM[8'hD0][4:0]}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_2_value_REG = _RANDOM[8'hD0][10:5]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_2_value_REG_1 = _RANDOM[8'hD0][16:11]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_3_value_REG = _RANDOM[8'hD0][22:17]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_3_value_REG_1 = _RANDOM[8'hD0][28:23]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_4_value_REG = {_RANDOM[8'hD0][31:29], _RANDOM[8'hD1][2:0]}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_4_value_REG_1 = _RANDOM[8'hD1][8:3]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_5_value_REG = _RANDOM[8'hD1][14:9]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_5_value_REG_1 = _RANDOM[8'hD1][20:15]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_6_value_REG = _RANDOM[8'hD1][26:21]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + io_perf_6_value_REG_1 = {_RANDOM[8'hD1][31:27], _RANDOM[8'hD2][0]}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}, src/main/scala/xiangshan/frontend/BPU.scala:222:7] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - s1_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s2_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s3_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 - s0_folded_gh_reg_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 - s0_folded_gh_reg_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s0_folded_gh_reg_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} - s0_folded_gh_reg_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 - s1_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 - s1_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s1_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 - s1_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 - s2_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 - s2_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s2_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 - s2_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 - s3_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 - s3_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s3_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 - s3_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 - s0_last_br_num_oh_reg_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s0_last_br_num_oh_reg_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s0_last_br_num_oh_reg_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 - s1_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s1_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s1_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} - s2_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s2_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s2_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 - s3_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s3_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s3_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 - ghv_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_4 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_5 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_6 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_7 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_8 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_9 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_10 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_11 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_12 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_13 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_14 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_15 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_16 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_17 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_18 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_19 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_20 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_21 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_22 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_23 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_24 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_25 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_26 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_27 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_28 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_29 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_30 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_31 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_32 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_33 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_34 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_35 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_36 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_37 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_38 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_39 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_40 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_41 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_42 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_43 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_44 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_45 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_46 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_47 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_48 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_49 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_50 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_51 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_52 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_53 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_54 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_55 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_56 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_57 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_58 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_59 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_60 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_61 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_62 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_63 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_64 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_65 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_66 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_67 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_68 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_69 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_70 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_71 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_72 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_73 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_74 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_75 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_76 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_77 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_78 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_79 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_80 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_81 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_82 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_83 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_84 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_85 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_86 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_87 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_88 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_89 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_90 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_91 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_92 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_93 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_94 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_95 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_96 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_97 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_98 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_99 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_100 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_101 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_102 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_103 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_104 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_105 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_106 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_107 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_108 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_109 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_110 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_111 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_112 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_113 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_114 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_115 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_116 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_117 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_118 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_119 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_120 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_121 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_122 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_123 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_124 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_125 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_126 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_127 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_128 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_129 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_130 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_131 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_132 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_133 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_134 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_135 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_136 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_137 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_138 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_139 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_140 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_141 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_142 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_143 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_144 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_145 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_146 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_147 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_148 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_149 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_150 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_151 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_152 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_153 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_154 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_155 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_156 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_157 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_158 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_159 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_160 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_161 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_162 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_163 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_164 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_165 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_166 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_167 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_168 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_169 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_170 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_171 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_172 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_173 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_174 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_175 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_176 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_177 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_178 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_179 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_180 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_181 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_182 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_183 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_184 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_185 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_186 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_187 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_188 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_189 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_190 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_191 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_192 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_193 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_194 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_195 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_196 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_197 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_198 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_199 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_200 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_201 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_202 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_203 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_204 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_205 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_206 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_207 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_208 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_209 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_210 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_211 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_212 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_213 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_214 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_215 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_216 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_217 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_218 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_219 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_220 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_221 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_222 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_223 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_224 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_225 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_226 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_227 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_228 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_229 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_230 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_231 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_232 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_233 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_234 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_235 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_236 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_237 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_238 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_239 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_240 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_241 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_242 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_243 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_244 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_245 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_246 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_247 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_248 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_249 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_250 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_251 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_252 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_253 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_254 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - ghv_255 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 - s0_ghist_ptr_reg_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s0_ghist_ptr_reg_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 - s0_ghist_ptr_reg_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 - s1_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s1_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 - s1_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 - s2_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s2_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 - s2_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 - s3_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - s3_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 - s3_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 - do_redirect_dup_3_valid = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_level = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pc = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isCall = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_pd_isRet = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_ssp = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_sctr = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSW_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_TOSR_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_NOS_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 - do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - do_redirect_dup_3_bits_cfiUpdate_histPtr_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 - do_redirect_dup_3_bits_cfiUpdate_target = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_taken = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - thisBrNumOH_dup_shiftAmount = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 - do_redirect_dup_3_bits_cfiUpdate_addIntoHist = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 - previous_s1_pred_info_hit_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_hit_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_target_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_target_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 - previous_s1_pred_info_lastBrPosOH_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_0_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_1_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_2_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_lastBrPosOH_3_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_taken_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_takenMask_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_0 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_1 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_2 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s1_pred_info_cfiIndex_3 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 - previous_s2_pred_pc_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_pc_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_0_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_0_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_1_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_1_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_2_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_2_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 - previous_s2_pred_full_pred_3_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 - previous_s2_pred_full_pred_3_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + if (reset) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + s1_valid_dup_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s2_valid_dup_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s3_valid_dup_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :272:65] + s0_folded_gh_reg_dup_1_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_1_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_1_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_1_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_2_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_2_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_2_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:63] + s0_folded_gh_reg_dup_3_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s0_folded_gh_reg_dup_3_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:{63,84}] + s0_folded_gh_reg_dup_3_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :286:63] + s1_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35] + s1_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s1_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35] + s1_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35] + s2_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :288:35] + s2_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s2_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :288:35] + s2_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :288:35] + s3_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :289:35] + s3_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s3_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:286:84, :289:35] + s3_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] + s0_last_br_num_oh_reg_dup_1 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s0_last_br_num_oh_reg_dup_2 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s0_last_br_num_oh_reg_dup_3 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73, :293:76] + s1_last_br_num_oh_dup_1 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s1_last_br_num_oh_dup_2 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s1_last_br_num_oh_dup_3 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:{40,76}] + s2_last_br_num_oh_dup_1 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s2_last_br_num_oh_dup_2 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s2_last_br_num_oh_dup_3 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :294:40] + s3_last_br_num_oh_dup_1 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s3_last_br_num_oh_dup_2 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s3_last_br_num_oh_dup_3 = 3'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:293:76, :295:40] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :298:85] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :299:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :300:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :301:46] + ghv_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_4 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_5 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_6 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_7 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_8 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_9 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_10 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_11 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_12 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_13 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_14 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_15 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_16 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_17 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_18 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_19 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_20 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_21 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_22 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_23 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_24 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_25 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_26 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_27 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_28 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_29 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_30 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_31 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_32 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_33 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_34 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_35 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_36 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_37 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_38 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_39 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_40 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_41 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_42 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_43 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_44 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_45 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_46 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_47 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_48 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_49 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_50 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_51 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_52 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_53 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_54 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_55 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_56 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_57 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_58 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_59 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_60 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_61 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_62 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_63 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_64 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_65 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_66 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_67 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_68 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_69 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_70 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_71 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_72 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_73 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_74 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_75 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_76 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_77 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_78 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_79 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_80 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_81 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_82 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_83 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_84 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_85 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_86 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_87 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_88 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_89 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_90 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_91 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_92 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_93 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_94 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_95 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_96 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_97 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_98 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_99 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_100 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_101 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_102 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_103 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_104 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_105 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_106 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_107 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_108 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_109 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_110 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_111 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_112 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_113 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_114 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_115 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_116 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_117 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_118 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_119 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_120 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_121 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_122 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_123 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_124 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_125 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_126 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_127 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_128 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_129 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_130 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_131 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_132 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_133 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_134 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_135 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_136 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_137 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_138 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_139 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_140 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_141 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_142 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_143 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_144 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_145 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_146 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_147 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_148 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_149 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_150 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_151 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_152 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_153 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_154 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_155 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_156 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_157 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_158 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_159 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_160 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_161 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_162 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_163 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_164 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_165 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_166 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_167 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_168 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_169 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_170 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_171 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_172 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_173 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_174 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_175 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_176 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_177 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_178 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_179 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_180 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_181 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_182 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_183 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_184 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_185 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_186 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_187 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_188 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_189 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_190 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_191 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_192 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_193 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_194 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_195 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_196 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_197 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_198 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_199 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_200 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_201 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_202 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_203 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_204 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_205 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_206 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_207 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_208 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_209 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_210 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_211 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_212 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_213 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_214 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_215 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_216 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_217 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_218 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_219 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_220 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_221 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_222 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_223 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_224 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_225 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_226 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_227 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_228 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_229 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_230 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_231 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_232 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_233 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_234 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_235 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_236 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_237 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_238 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_239 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_240 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_241 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_242 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_243 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_244 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_245 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_246 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_247 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_248 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_249 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_250 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_251 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_252 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_253 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_254 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + ghv_255 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :312:20] + s0_ghist_ptr_reg_dup_0_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_0_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_1_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_1_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_2_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_2_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s0_ghist_ptr_reg_dup_3_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :323:63] + s0_ghist_ptr_reg_dup_3_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :323:63] + s1_ghist_ptr_dup_0_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_0_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_1_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_1_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_2_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_2_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s1_ghist_ptr_dup_3_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :324:35] + s1_ghist_ptr_dup_3_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35] + s2_ghist_ptr_dup_0_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_0_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_1_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_1_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_2_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_2_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s2_ghist_ptr_dup_3_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :325:35] + s2_ghist_ptr_dup_3_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35] + s3_ghist_ptr_dup_0_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_0_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_1_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_1_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_2_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_2_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + s3_ghist_ptr_dup_3_flag = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :326:35] + s3_ghist_ptr_dup_3_value = 8'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + do_redirect_dup_next_valid_last_r = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + previous_s1_pred_info_hit_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_hit_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_target_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_2 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_target_3 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :601:40] + previous_s1_pred_info_lastBrPosOH_0_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_0_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_0_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_1_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_2_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_lastBrPosOH_3_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_2 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_taken_3 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_0_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_0_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_1_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_1_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_2_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_2_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_3_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_takenMask_3_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_0 = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_1 = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_2 = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s1_pred_info_cfiIndex_3 = 4'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :601:40] + previous_s2_pred_pc_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_2 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_pc_3 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_br_taken_mask_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_slot_valids_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_slot_valids_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_targets_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_targets_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_fallThroughAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_0_is_br_sharing = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_0_hit = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_br_taken_mask_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_slot_valids_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_slot_valids_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_targets_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_targets_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_fallThroughAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_1_is_br_sharing = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_1_hit = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_br_taken_mask_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_slot_valids_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_slot_valids_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_targets_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_targets_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_fallThroughAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_2_is_br_sharing = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_2_hit = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_br_taken_mask_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_slot_valids_0 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_slot_valids_1 = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_targets_0 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_targets_1 = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_fallThroughAddr = 41'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:344:53, :674:35] + previous_s2_pred_full_pred_3_is_br_sharing = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + previous_s2_pred_full_pred_3_hit = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :674:35] + predictors_io_update_valid_REG = 1'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:230:73, :728:40] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - DelayN_1 ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_1 ctrl_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in_ubtb_enable (io_ctrl_ubtb_enable), .io_in_btb_enable (io_ctrl_btb_enable), @@ -14347,54 +14784,54 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .io_out_sc_enable (_ctrl_delay_io_out_sc_enable), .io_out_ras_enable (_ctrl_delay_io_out_ras_enable) ); - Composer predictors ( // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + Composer predictors ( // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26] .clock (clock), .reset (reset), .io_reset_vector (io_reset_vector), - .io_in_bits_s0_pc_0 (_s0_pc_dup_0_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .io_in_bits_s0_pc_1 (_s0_pc_dup_1_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .io_in_bits_s0_pc_2 (_s0_pc_dup_2_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .io_in_bits_s0_pc_3 (_s0_pc_dup_3_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_s0_pc_0 (_s0_pc_dup_0_ppm_out_res), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .io_in_bits_s0_pc_1 (_s0_pc_dup_1_ppm_out_res), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .io_in_bits_s0_pc_2 (_s0_pc_dup_2_ppm_out_res), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .io_in_bits_s0_pc_3 (_s0_pc_dup_3_ppm_out_res), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_17_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_16_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_15_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_14_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_9_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_8_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_7_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_5_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_4_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_3_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_1_hist_1_folded_hist - (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_14_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_13_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_12_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_11_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_10_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_6_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_4_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_3_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_in_bits_folded_hist_3_hist_2_folded_hist - (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .io_out_s1_pc_0 (_predictors_io_out_s1_pc_0), .io_out_s1_pc_1 @@ -14742,367 +15179,390 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .io_out_last_stage_ftb_entry_always_taken_1 (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1), .io_ctrl_ubtb_enable - (_ctrl_delay_io_out_ubtb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ctrl_delay_io_out_ubtb_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_ctrl_btb_enable - (_ctrl_delay_io_out_btb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ctrl_delay_io_out_btb_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_ctrl_tage_enable - (_ctrl_delay_io_out_tage_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ctrl_delay_io_out_tage_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_ctrl_sc_enable - (_ctrl_delay_io_out_sc_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + (_ctrl_delay_io_out_sc_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] .io_ctrl_ras_enable - (_ctrl_delay_io_out_ras_enable), // utility/src/main/scala/utility/Hold.scala:97:23 - .io_s0_fire_0 (s0_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 - .io_s0_fire_1 (s0_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 - .io_s0_fire_2 (s0_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 - .io_s0_fire_3 (s0_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 - .io_s1_fire_0 (s1_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - .io_s1_fire_1 (s1_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - .io_s1_fire_2 (s1_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - .io_s1_fire_3 (s1_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 - .io_s2_fire_0 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - .io_s2_fire_1 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - .io_s2_fire_2 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - .io_s2_fire_3 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - .io_s3_fire_2 (s3_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 - .io_s3_redirect_2 (s3_redirect_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:684:28 + (_ctrl_delay_io_out_ras_enable), // @[utility/src/main/scala/utility/Hold.scala:100:23] + .io_s0_fire_0 (s0_fire_dup_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:368:36] + .io_s0_fire_1 (s0_fire_dup_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:368:36] + .io_s0_fire_2 (s0_fire_dup_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:368:36] + .io_s0_fire_3 (s0_fire_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:368:36] + .io_s1_fire_0 (s1_fire_dup_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + .io_s1_fire_1 (s1_fire_dup_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + .io_s1_fire_2 (s1_fire_dup_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + .io_s1_fire_3 (s1_fire_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:375:60] + .io_s2_fire_0 (s2_valid_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + .io_s2_fire_1 (s2_valid_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + .io_s2_fire_2 (s2_valid_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + .io_s2_fire_3 (s2_valid_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + .io_s3_fire_2 (s3_valid_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65] + .io_s3_redirect_2 (s3_redirect_dup_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28] .io_s1_ready (_predictors_io_s1_ready), .io_update_valid - (predictors_io_update_REG_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/BPU.scala:728:40] .io_update_bits_pc - (predictors_io_update_REG_bits_pc), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_pc), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_17_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_16_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_15_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_14_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_13_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_12_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_11_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_10_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_9_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_8_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_7_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_6_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_5_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_4_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_3_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_2_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_spec_info_folded_hist_hist_1_folded_hist - (predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_valid - (predictors_io_update_REG_bits_ftb_entry_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_valid), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_brSlots_0_offset - (predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_brSlots_0_lower - (predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_brSlots_0_tarStat - (predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_brSlots_0_sharing - (predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_brSlots_0_valid - (predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_tailSlot_offset - (predictors_io_update_REG_bits_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_tailSlot_lower - (predictors_io_update_REG_bits_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_tailSlot_tarStat - (predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_tailSlot_sharing - (predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_tailSlot_valid - (predictors_io_update_REG_bits_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_pftAddr - (predictors_io_update_REG_bits_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_carry - (predictors_io_update_REG_bits_ftb_entry_carry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_isCall - (predictors_io_update_REG_bits_ftb_entry_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_isCall), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_isRet - (predictors_io_update_REG_bits_ftb_entry_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_isRet), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_isJalr - (predictors_io_update_REG_bits_ftb_entry_isJalr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_isJalr), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_last_may_be_rvi_call - (predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_always_taken_0 - (predictors_io_update_REG_bits_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_ftb_entry_always_taken_1 - (predictors_io_update_REG_bits_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_cfi_idx_valid - (predictors_io_update_REG_bits_cfi_idx_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_cfi_idx_valid), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_cfi_idx_bits - (predictors_io_update_REG_bits_cfi_idx_bits), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_cfi_idx_bits), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_br_taken_mask_0 - (predictors_io_update_REG_bits_br_taken_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_br_taken_mask_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_br_taken_mask_1 - (predictors_io_update_REG_bits_br_taken_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_br_taken_mask_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_jmp_taken - (predictors_io_update_REG_bits_jmp_taken), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_jmp_taken), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_mispred_mask_0 - (predictors_io_update_REG_bits_mispred_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_mispred_mask_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_mispred_mask_1 - (predictors_io_update_REG_bits_mispred_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_mispred_mask_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_mispred_mask_2 - (predictors_io_update_REG_bits_mispred_mask_2), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_mispred_mask_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_old_entry - (predictors_io_update_REG_bits_old_entry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_old_entry), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_meta - (predictors_io_update_REG_bits_meta), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + (predictors_io_update_bits_r_meta), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] .io_update_bits_full_target - (predictors_io_update_REG_bits_full_target), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 - .io_redirect_valid (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (predictors_io_update_bits_r_full_target), // @[src/main/scala/xiangshan/frontend/BPU.scala:729:41] + .io_redirect_valid + (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .io_redirect_bits_level - (do_redirect_dup_3_bits_level), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_level), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_pc - (do_redirect_dup_3_bits_cfiUpdate_pc), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_pc), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_pd_isRVC - (do_redirect_dup_3_bits_cfiUpdate_pd_isRVC), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_pd_isCall - (do_redirect_dup_3_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_pd_isRet - (do_redirect_dup_3_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_ssp - (do_redirect_dup_3_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_ssp), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_sctr - (do_redirect_dup_3_bits_cfiUpdate_sctr), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_sctr), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_TOSW_flag - (do_redirect_dup_3_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_TOSW_value - (do_redirect_dup_3_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_TOSR_flag - (do_redirect_dup_3_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_TOSR_value - (do_redirect_dup_3_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_NOS_flag - (do_redirect_dup_3_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] .io_redirect_bits_cfiUpdate_NOS_value - (do_redirect_dup_3_bits_cfiUpdate_NOS_value) // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + (do_redirect_dup_next_bits_r_cfiUpdate_NOS_value), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .io_perf_0_value + (_predictors_io_perf_0_value), + .io_perf_1_value + (_predictors_io_perf_1_value), + .io_perf_2_value + (_predictors_io_perf_2_value), + .io_perf_3_value + (_predictors_io_perf_3_value), + .io_perf_4_value + (_predictors_io_perf_4_value), + .io_perf_5_value + (_predictors_io_perf_5_value), + .io_perf_6_value + (_predictors_io_perf_6_value) ); - DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_2 reset_vector_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in (io_reset_vector), .io_out (_reset_vector_delay_io_out) ); - PriorityMuxModule s0_pc_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule s0_pc_dup_0_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_target_sel - (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_target_src - ((_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + ((_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit ? _predictors_io_out_s2_full_pred_0_targets_0 - : 39'h0) - | (~_selVecOH_T_66 & _GEN_21 & _predictors_io_out_s2_full_pred_0_hit + : 41'h0) + | (~_cfiIndex_bits_T_261 & _GEN_21 & _predictors_io_out_s2_full_pred_0_hit ? _predictors_io_out_s2_full_pred_0_targets_1 - : 39'h0) - | ({_GEN_21, _selVecOH_T_66} == 2'h0 & _predictors_io_out_s2_full_pred_0_hit + : 41'h0) + | ({_GEN_21, _cfiIndex_bits_T_261} == 2'h0 & _predictors_io_out_s2_full_pred_0_hit ? _predictors_io_out_s2_full_pred_0_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s2_full_pred_0_hit - ? 39'h0 - : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] .s1_target_sel (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_target_src - ((_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + ((s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1 + : 41'h0) + | (~s1_pred_info_takenMask_0_0 & s1_pred_info_takenMask_0_1 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_0_1, s1_pred_info_takenMask_0_0} == 2'h0 & _predictors_io_out_s1_full_pred_0_hit ? _predictors_io_out_s1_full_pred_0_fallThroughAddr - : 39'h0) | _GEN_4), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 - .s3_target_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + : 41'h0) | _GEN_4), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] + .s3_target_sel (s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_target_src - ((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + ((_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_targets_0 - : 39'h0) - | (~_selVecOH_T_98 & _GEN_32 & _predictors_io_out_s3_full_pred_0_hit + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_8 & _GEN_32 + & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_targets_1 - : 39'h0) - | ({_GEN_32, _selVecOH_T_98} == 2'h0 & _predictors_io_out_s3_full_pred_0_hit + : 41'h0) + | ({_GEN_32, _s3_redirect_on_jalr_target_dup_T_8} == 2'h0 + & _predictors_io_out_s3_full_pred_0_hit ? _predictors_io_out_s3_full_pred_0_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_0_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 - .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .stallPC_src (s0_pc_reg_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + ? 41'h0 + : _s3_redirect_on_target_dup_T_5)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] + .redirect_target_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .stallPC_src (s0_pc_reg_dup_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] .out_res (_s0_pc_dup_0_ppm_out_res) ); - PriorityMuxModule s0_pc_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule s0_pc_dup_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_target_sel - (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_target_src - ((_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit + ((_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit ? _predictors_io_out_s2_full_pred_1_targets_0 - : 39'h0) - | (~_selVecOH_T_74 & _GEN_22 & _predictors_io_out_s2_full_pred_1_hit + : 41'h0) + | (~_cfiIndex_bits_T_282 & _GEN_22 & _predictors_io_out_s2_full_pred_1_hit ? _predictors_io_out_s2_full_pred_1_targets_1 - : 39'h0) - | ({_GEN_22, _selVecOH_T_74} == 2'h0 & _predictors_io_out_s2_full_pred_1_hit + : 41'h0) + | ({_GEN_22, _cfiIndex_bits_T_282} == 2'h0 & _predictors_io_out_s2_full_pred_1_hit ? _predictors_io_out_s2_full_pred_1_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s2_full_pred_1_hit - ? 39'h0 - : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] .s1_target_sel (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_target_src - ((_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + ((s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1 + : 41'h0) + | (~s1_pred_info_takenMask_1_0 & s1_pred_info_takenMask_1_1 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_1_1, s1_pred_info_takenMask_1_0} == 2'h0 & _predictors_io_out_s1_full_pred_1_hit ? _predictors_io_out_s1_full_pred_1_fallThroughAddr - : 39'h0) | _GEN_5), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 - .s3_target_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + : 41'h0) | _GEN_5), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] + .s3_target_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_target_src - ((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + ((_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_targets_0 - : 39'h0) - | (~_selVecOH_T_106 & _GEN_33 & _predictors_io_out_s3_full_pred_1_hit + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_28 & _GEN_33 + & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_targets_1 - : 39'h0) - | ({_GEN_33, _selVecOH_T_106} == 2'h0 & _predictors_io_out_s3_full_pred_1_hit + : 41'h0) + | ({_GEN_33, _s3_redirect_on_jalr_target_dup_T_28} == 2'h0 + & _predictors_io_out_s3_full_pred_1_hit ? _predictors_io_out_s3_full_pred_1_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_1_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_4_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 - .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .stallPC_src (s0_pc_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + ? 41'h0 + : _s3_redirect_on_target_dup_T_19)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] + .redirect_target_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .stallPC_src (s0_pc_reg_dup_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] .out_res (_s0_pc_dup_1_ppm_out_res) ); - PriorityMuxModule s0_pc_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule s0_pc_dup_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_target_sel - (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_target_src - ((_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit + ((_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit ? _predictors_io_out_s2_full_pred_2_targets_0 - : 39'h0) - | (~_selVecOH_T_82 & _GEN_23 & _predictors_io_out_s2_full_pred_2_hit + : 41'h0) + | (~_cfiIndex_bits_T_303 & _GEN_23 & _predictors_io_out_s2_full_pred_2_hit ? _predictors_io_out_s2_full_pred_2_targets_1 - : 39'h0) - | ({_GEN_23, _selVecOH_T_82} == 2'h0 & _predictors_io_out_s2_full_pred_2_hit + : 41'h0) + | ({_GEN_23, _cfiIndex_bits_T_303} == 2'h0 & _predictors_io_out_s2_full_pred_2_hit ? _predictors_io_out_s2_full_pred_2_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s2_full_pred_2_hit - ? 39'h0 - : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] .s1_target_sel (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_target_src - ((_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + ((s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1 + : 41'h0) + | (~s1_pred_info_takenMask_2_0 & s1_pred_info_takenMask_2_1 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_2_1, s1_pred_info_takenMask_2_0} == 2'h0 & _predictors_io_out_s1_full_pred_2_hit ? _predictors_io_out_s1_full_pred_2_fallThroughAddr - : 39'h0) | _GEN_6), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 - .s3_target_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + : 41'h0) | _GEN_6), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] + .s3_target_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_target_src - ((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + ((_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_targets_0 - : 39'h0) - | (~_selVecOH_T_114 & _GEN_34 & _predictors_io_out_s3_full_pred_2_hit + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_48 & _GEN_34 + & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_targets_1 - : 39'h0) - | ({_GEN_34, _selVecOH_T_114} == 2'h0 & _predictors_io_out_s3_full_pred_2_hit + : 41'h0) + | ({_GEN_34, _s3_redirect_on_jalr_target_dup_T_48} == 2'h0 + & _predictors_io_out_s3_full_pred_2_hit ? _predictors_io_out_s3_full_pred_2_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_2_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_7_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 - .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .stallPC_src (s0_pc_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + ? 41'h0 + : _s3_redirect_on_target_dup_T_33)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] + .redirect_target_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .stallPC_src (s0_pc_reg_dup_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] .out_res (_s0_pc_dup_2_ppm_out_res) ); - PriorityMuxModule s0_pc_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule s0_pc_dup_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_target_sel - (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_target_src - ((_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit + ((_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit ? _predictors_io_out_s2_full_pred_3_targets_0 - : 39'h0) - | (~_selVecOH_T_90 & _GEN_24 & _predictors_io_out_s2_full_pred_3_hit + : 41'h0) + | (~_cfiIndex_bits_T_324 & _GEN_24 & _predictors_io_out_s2_full_pred_3_hit ? _predictors_io_out_s2_full_pred_3_targets_1 - : 39'h0) - | ({_GEN_24, _selVecOH_T_90} == 2'h0 & _predictors_io_out_s2_full_pred_3_hit + : 41'h0) + | ({_GEN_24, _cfiIndex_bits_T_324} == 2'h0 & _predictors_io_out_s2_full_pred_3_hit ? _predictors_io_out_s2_full_pred_3_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s2_full_pred_3_hit - ? 39'h0 - : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] .s1_target_sel (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_target_src - ((_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + ((s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_targets_0 - : 39'h0) - | (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1 + : 41'h0) + | (~s1_pred_info_takenMask_3_0 & s1_pred_info_takenMask_3_1 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_targets_1 - : 39'h0) - | ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0 + : 41'h0) + | ({s1_pred_info_takenMask_3_1, s1_pred_info_takenMask_3_0} == 2'h0 & _predictors_io_out_s1_full_pred_3_hit ? _predictors_io_out_s1_full_pred_3_fallThroughAddr - : 39'h0) | _GEN_7), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 - .s3_target_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + : 41'h0) | _GEN_7), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25] + .s3_target_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_target_src - ((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + ((_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_targets_0 - : 39'h0) - | (~_selVecOH_T_122 & _GEN_35 & _predictors_io_out_s3_full_pred_3_hit + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_68 & _GEN_35 + & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_targets_1 - : 39'h0) - | ({_GEN_35, _selVecOH_T_122} == 2'h0 & _predictors_io_out_s3_full_pred_3_hit + : 41'h0) + | ({_GEN_35, _s3_redirect_on_jalr_target_dup_T_68} == 2'h0 + & _predictors_io_out_s3_full_pred_3_hit ? _predictors_io_out_s3_full_pred_3_fallThroughAddr - : 39'h0) + : 41'h0) | (_predictors_io_out_s3_full_pred_3_hit - ? 39'h0 - : _s3_redirect_on_target_dup_WIRE_10_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 - .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .stallPC_src (s0_pc_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + ? 41'h0 + : _s3_redirect_on_target_dup_T_47)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :292:73, :344:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:421:{51,97}, :422:{21,28,32}, :459:69, :460:25, :506:47] + .redirect_target_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), // @[utility/src/main/scala/utility/BitUtils.scala:33:27] + .stallPC_src (s0_pc_reg_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:277:49] .out_res (_s0_pc_dup_3_ppm_out_res) ); - PriorityMuxModule_4 s0_folded_gh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_4 s0_folded_gh_dup_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_FGH_sel - (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_FGH_src_hist_17_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_17_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 @@ -15113,7 +15573,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_17_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 @@ -15130,10 +15590,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s2_folded_gh_dup_1_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_16_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_16_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_16_folded_hist[9], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15145,7 +15605,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_16_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -15162,10 +15622,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_16_folded_hist[10], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_15_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_15_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 @@ -15176,7 +15636,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_15_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 @@ -15193,21 +15653,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s2_folded_gh_dup_1_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_14_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_14_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_14_folded_hist[6:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_1_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_13_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_13_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_13_folded_hist[7:4], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15219,7 +15679,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_13_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_13_folded_hist[6:4], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15237,21 +15697,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_13_folded_hist[8], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_12_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_12_folded_hist : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_12_folded_hist[2:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0} : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s2_full_pred_1_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_11_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_11_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_11_folded_hist[6:2], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15263,7 +15723,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_11_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_11_folded_hist[5:2], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15280,10 +15740,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_11_folded_hist[7], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_10_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_10_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_10_folded_hist[7:5], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15295,7 +15755,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_10_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_10_folded_hist[6:5], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15313,10 +15773,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_10_folded_hist[8], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_9_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_9_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_9_folded_hist[5:4], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15328,7 +15788,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_9_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_9_folded_hist[4], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15346,10 +15806,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_9_folded_hist[6], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_8_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_8_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -15360,7 +15820,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_8_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 @@ -15377,10 +15837,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s2_folded_gh_dup_1_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_7_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_7_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_7_folded_hist[5:1], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15391,7 +15851,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_7_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_7_folded_hist[4:1], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15402,10 +15862,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_6_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_6_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_6_folded_hist[7], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15417,7 +15877,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_6_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s2_last_br_num_oh_dup_1[1] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 @@ -15434,10 +15894,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_6_folded_hist[8], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_5_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_5_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_5_folded_hist[5:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_1[0] @@ -15448,7 +15908,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s2_folded_gh_dup_1_hist_5_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_5_folded_hist[4:0], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15464,10 +15924,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) ^ s2_folded_gh_dup_1_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_4_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_4_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_4_folded_hist[6:5], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15479,7 +15939,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_4_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_4_folded_hist[5], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15497,10 +15957,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_4_folded_hist[7], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_3_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_3_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_3_folded_hist[6:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_1[0] @@ -15511,7 +15971,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s2_folded_gh_dup_1_hist_3_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_3_folded_hist[5:0], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15527,10 +15987,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) ^ s2_folded_gh_dup_1_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_2_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_2_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_2_folded_hist[6:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_1[0] @@ -15541,7 +16001,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) ^ s2_folded_gh_dup_1_hist_2_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_2_folded_hist[5:0], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15557,10 +16017,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_1[2] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) ^ s2_folded_gh_dup_1_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_1_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_1_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_1_folded_hist[9:2], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15572,7 +16032,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_1_br_taken_mask_0 ^ s2_folded_gh_dup_1_hist_1_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_1_folded_hist[8:2], (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s2_last_br_num_oh_dup_1[1] @@ -15589,24 +16049,24 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_1_hist_1_folded_hist[10], _predictors_io_out_s2_full_pred_1_br_taken_mask_1 ^ s2_folded_gh_dup_1_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_0_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_0_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_1 + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 ? {s2_folded_gh_dup_1_hist_0_folded_hist[6:0], _predictors_io_out_s2_full_pred_1_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_1_2 + | (_s2_predicted_fh_dup_T_121 ? {s2_folded_gh_dup_1_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_1_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s1_FGH_sel (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_FGH_src_hist_17_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_17_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 @@ -15614,10 +16074,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_17_folded_hist[9], s1_folded_gh_dup_1_hist_17_folded_hist[8:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_17_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 @@ -15626,7 +16086,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_17_folded_hist[8], s1_folded_gh_dup_1_hist_17_folded_hist[7:0], s1_folded_gh_dup_1_hist_17_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15634,10 +16094,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_16_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_16_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_16_folded_hist[9], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15646,10 +16106,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s1_folded_gh_dup_1_hist_16_folded_hist[8], s1_folded_gh_dup_1_hist_16_folded_hist[7:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_16_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -15664,12 +16124,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_16_folded_hist[7], s1_folded_gh_dup_1_hist_16_folded_hist[6:0], s1_folded_gh_dup_1_hist_16_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_15_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_15_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 @@ -15677,10 +16137,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s1_folded_gh_dup_1_hist_15_folded_hist[5], s1_folded_gh_dup_1_hist_15_folded_hist[4:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_15_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 @@ -15689,7 +16149,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_15_folded_hist[4], s1_folded_gh_dup_1_hist_15_folded_hist[3:0], s1_folded_gh_dup_1_hist_15_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15697,25 +16157,25 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s1_folded_gh_dup_1_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_14_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 + ((_s1_predicted_fh_dup_T_65 ? {s1_folded_gh_dup_1_hist_14_folded_hist[7:1], s1_folded_gh_dup_1_hist_14_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_271} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_14_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_14_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_13_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_13_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_13_folded_hist[7:4], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15724,10 +16184,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s1_folded_gh_dup_1_hist_13_folded_hist[3], s1_folded_gh_dup_1_hist_13_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_13_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_13_folded_hist[6:4], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15743,27 +16203,27 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_13_folded_hist[2], s1_folded_gh_dup_1_hist_13_folded_hist[1:0], s1_folded_gh_dup_1_hist_13_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_12_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 + ((_s1_predicted_fh_dup_T_65 ? {s1_folded_gh_dup_1_hist_12_folded_hist[3:1], s1_folded_gh_dup_1_hist_12_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_271} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_12_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_12_folded_hist[1:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_11_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_11_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_11_folded_hist[6:2], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15772,10 +16232,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) ^ s1_folded_gh_dup_1_hist_11_folded_hist[1], s1_folded_gh_dup_1_hist_11_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_11_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_11_folded_hist[5:2], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15790,12 +16250,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) ^ s1_folded_gh_dup_1_hist_11_folded_hist[0], s1_folded_gh_dup_1_hist_11_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_10_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_10_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_10_folded_hist[7:5], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15804,10 +16264,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_10_folded_hist[4], s1_folded_gh_dup_1_hist_10_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_10_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_10_folded_hist[6:5], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15823,12 +16283,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_10_folded_hist[3], s1_folded_gh_dup_1_hist_10_folded_hist[2:0], s1_folded_gh_dup_1_hist_10_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_9_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_9_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_9_folded_hist[5:4], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15837,10 +16297,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_9_folded_hist[3], s1_folded_gh_dup_1_hist_9_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_9_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_9_folded_hist[4], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15856,12 +16316,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_9_folded_hist[2], s1_folded_gh_dup_1_hist_9_folded_hist[1:0], s1_folded_gh_dup_1_hist_9_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_8_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_8_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -15869,10 +16329,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s1_folded_gh_dup_1_hist_8_folded_hist[6], s1_folded_gh_dup_1_hist_8_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_8_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 @@ -15881,7 +16341,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_8_folded_hist[5], s1_folded_gh_dup_1_hist_8_folded_hist[4:0], s1_folded_gh_dup_1_hist_8_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15889,10 +16349,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s1_folded_gh_dup_1_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_7_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_7_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_7_folded_hist[5:1], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15900,10 +16360,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_7_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_7_folded_hist[4:1], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15912,12 +16372,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_6_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_6_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_6_folded_hist[7], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15926,10 +16386,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) ^ s1_folded_gh_dup_1_hist_6_folded_hist[6], s1_folded_gh_dup_1_hist_6_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_6_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s1_last_br_num_oh_dup_1[1] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 @@ -15944,14 +16404,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_6_folded_hist[5], s1_folded_gh_dup_1_hist_6_folded_hist[4:0], s1_folded_gh_dup_1_hist_6_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_5_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_5_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_5_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15960,7 +16420,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s1_folded_gh_dup_1_hist_5_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_5_folded_hist[4:0], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15968,7 +16428,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s1_folded_gh_dup_1_hist_5_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 | s1_last_br_num_oh_dup_1[1] @@ -15976,10 +16436,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) ^ s1_folded_gh_dup_1_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_4_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_4_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_4_folded_hist[6:5], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -15988,10 +16448,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s1_folded_gh_dup_1_hist_4_folded_hist[4], s1_folded_gh_dup_1_hist_4_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_4_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_4_folded_hist[5], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16007,14 +16467,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_1_hist_4_folded_hist[3], s1_folded_gh_dup_1_hist_4_folded_hist[2:0], s1_folded_gh_dup_1_hist_4_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_3_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_3_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_3_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16023,7 +16483,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_3_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_3_folded_hist[5:0], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16031,7 +16491,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s1_folded_gh_dup_1_hist_3_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 | s1_last_br_num_oh_dup_1[1] @@ -16039,12 +16499,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) ^ s1_folded_gh_dup_1_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_2_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_2_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_2_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16053,7 +16513,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) ^ s1_folded_gh_dup_1_hist_2_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_2_folded_hist[5:0], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16061,7 +16521,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) ^ s1_folded_gh_dup_1_hist_2_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 | s1_last_br_num_oh_dup_1[1] @@ -16069,10 +16529,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_1[2] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) ^ s1_folded_gh_dup_1_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_1_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_1_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_1_folded_hist[9:2], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16081,10 +16541,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s1_folded_gh_dup_1_hist_1_folded_hist[1], s1_folded_gh_dup_1_hist_1_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 ^ s1_folded_gh_dup_1_hist_1_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_1_folded_hist[8:2], (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s1_last_br_num_oh_dup_1[1] @@ -16099,28 +16559,29 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) ^ s1_folded_gh_dup_1_hist_1_folded_hist[0], s1_folded_gh_dup_1_hist_1_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 ^ s1_folded_gh_dup_1_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_0_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_1_0 + ((_s1_predicted_fh_dup_T_65 ? {s1_folded_gh_dup_1_hist_0_folded_hist[7:1], s1_folded_gh_dup_1_hist_0_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_271} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_1 + | (_s1_predicted_fh_dup_T_93 ? {s1_folded_gh_dup_1_hist_0_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_1_2 + | (_s1_predicted_fh_dup_T_121 ? {s1_folded_gh_dup_1_hist_0_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 - .s3_FGH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] + .s3_FGH_sel + (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_FGH_src_hist_17_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_17_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 @@ -16131,7 +16592,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_17_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 @@ -16148,10 +16609,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s3_folded_gh_dup_1_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_16_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_16_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_16_folded_hist[9], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16163,7 +16624,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_16_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -16180,10 +16641,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_16_folded_hist[10], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_15_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_15_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 @@ -16194,7 +16655,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_15_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 @@ -16211,21 +16672,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) ^ s3_folded_gh_dup_1_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_14_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_14_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_14_folded_hist[6:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_1_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_13_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_13_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_13_folded_hist[7:4], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16237,7 +16698,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_13_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_13_folded_hist[6:4], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16255,21 +16716,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_13_folded_hist[8], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_12_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_12_folded_hist : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_12_folded_hist[2:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0} : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s3_full_pred_1_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_11_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_11_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_11_folded_hist[6:2], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16281,7 +16742,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_11_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_11_folded_hist[5:2], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16298,10 +16759,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_11_folded_hist[7], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_10_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_10_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_10_folded_hist[7:5], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16313,7 +16774,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_10_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_10_folded_hist[6:5], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16331,10 +16792,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_10_folded_hist[8], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_9_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_9_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_9_folded_hist[5:4], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16346,7 +16807,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_9_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_9_folded_hist[4], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16364,10 +16825,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_9_folded_hist[6], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_8_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_8_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 @@ -16378,7 +16839,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_8_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 @@ -16395,10 +16856,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s3_folded_gh_dup_1_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_7_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_7_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_7_folded_hist[5:1], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16409,7 +16870,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_7_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_7_folded_hist[4:1], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16420,10 +16881,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_6_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_6_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_6_folded_hist[7], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16435,7 +16896,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_6_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s3_last_br_num_oh_dup_1[1] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 @@ -16452,10 +16913,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_6_folded_hist[8], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_5_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_5_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_5_folded_hist[5:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_1[0] @@ -16466,7 +16927,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) ^ s3_folded_gh_dup_1_hist_5_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_5_folded_hist[4:0], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16482,10 +16943,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) ^ s3_folded_gh_dup_1_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_4_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_4_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_4_folded_hist[6:5], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16497,7 +16958,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_4_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_4_folded_hist[5], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16515,10 +16976,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_4_folded_hist[7], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_3_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_3_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_3_folded_hist[6:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_1[0] @@ -16529,7 +16990,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) ^ s3_folded_gh_dup_1_hist_3_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_3_folded_hist[5:0], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16545,10 +17006,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) ^ s3_folded_gh_dup_1_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_2_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_2_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_2_folded_hist[6:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_1[0] @@ -16559,7 +17020,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) ^ s3_folded_gh_dup_1_hist_2_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_2_folded_hist[5:0], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16575,10 +17036,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_1[2] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) ^ s3_folded_gh_dup_1_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_1_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_1_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_1_folded_hist[9:2], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16590,7 +17051,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_1_br_taken_mask_0 ^ s3_folded_gh_dup_1_hist_1_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_1_folded_hist[8:2], (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 | s3_last_br_num_oh_dup_1[1] @@ -16607,55 +17068,73 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_1_hist_1_folded_hist[10], _predictors_io_out_s3_full_pred_1_br_taken_mask_1 ^ s3_folded_gh_dup_1_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_0_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_0_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_1 + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 ? {s3_folded_gh_dup_1_hist_0_folded_hist[6:0], _predictors_io_out_s3_full_pred_1_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_1_2 + | (_s3_predicted_fh_dup_T_121 ? {s3_folded_gh_dup_1_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_1_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 - .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_FGHT_src_hist_17_folded_hist (_GEN_45[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_16_folded_hist (_GEN_46[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_15_folded_hist (_GEN_47[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_14_folded_hist (_GEN_48[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_13_folded_hist (_GEN_49[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_12_folded_hist (_GEN_50[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_11_folded_hist (_GEN_51[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_10_folded_hist (_GEN_52[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_9_folded_hist (_GEN_53[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_8_folded_hist (_GEN_54[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_7_folded_hist (_GEN_55[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_6_folded_hist (_GEN_56[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_5_folded_hist (_GEN_57[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_4_folded_hist (_GEN_58[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_3_folded_hist (_GEN_59[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_2_folded_hist (_GEN_60[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_1_folded_hist (_GEN_61[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_0_folded_hist (_GEN_62[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_1_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_1_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_1_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_1_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_1_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_1_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_1_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_1_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_1_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_1_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_1_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_1_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_1_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_1_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_1_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_1_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_1_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_1_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_45[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_46[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_47[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_48[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_49[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_50[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_51[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_52[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_53[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_54[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_55[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_56[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_57[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_58[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_59[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_60[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_61[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_62[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_1_hist_17_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_1_hist_16_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_1_hist_15_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_1_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_1_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_1_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_1_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_1_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_1_hist_9_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_1_hist_8_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_1_hist_7_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_1_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_1_hist_5_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_1_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_1_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_1_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_1_hist_1_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_1_hist_0_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] .out_res_hist_17_folded_hist (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), .out_res_hist_16_folded_hist @@ -16693,12 +17172,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_hist_0_folded_hist (_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist) ); - PriorityMuxModule_4 s0_folded_gh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_4 s0_folded_gh_dup_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_FGH_sel - (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_FGH_src_hist_17_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_17_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 @@ -16709,7 +17188,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_17_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 @@ -16726,10 +17205,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s2_folded_gh_dup_2_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_16_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_16_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_16_folded_hist[9], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16741,7 +17220,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_16_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -16758,10 +17237,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_16_folded_hist[10], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_15_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_15_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 @@ -16772,7 +17251,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_15_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 @@ -16789,21 +17268,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s2_folded_gh_dup_2_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_14_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_14_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_14_folded_hist[6:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_2_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_13_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_13_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_13_folded_hist[7:4], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16815,7 +17294,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_13_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_13_folded_hist[6:4], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16833,21 +17312,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_13_folded_hist[8], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_12_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_12_folded_hist : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_12_folded_hist[2:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0} : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s2_full_pred_2_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_11_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_11_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_11_folded_hist[6:2], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16859,7 +17338,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_11_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_11_folded_hist[5:2], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16876,10 +17355,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_11_folded_hist[7], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_10_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_10_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_10_folded_hist[7:5], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16891,7 +17370,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_10_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_10_folded_hist[6:5], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16909,10 +17388,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_10_folded_hist[8], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_9_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_9_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_9_folded_hist[5:4], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16924,7 +17403,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_9_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_9_folded_hist[4], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16942,10 +17421,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_9_folded_hist[6], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_8_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_8_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -16956,7 +17435,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_8_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 @@ -16973,10 +17452,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s2_folded_gh_dup_2_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_7_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_7_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_7_folded_hist[5:1], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16987,7 +17466,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_7_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_7_folded_hist[4:1], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -16998,10 +17477,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_6_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_6_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_6_folded_hist[7], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17013,7 +17492,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_6_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s2_last_br_num_oh_dup_2[1] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 @@ -17030,10 +17509,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_6_folded_hist[8], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_5_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_5_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_5_folded_hist[5:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_2[0] @@ -17044,7 +17523,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s2_folded_gh_dup_2_hist_5_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_5_folded_hist[4:0], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17060,10 +17539,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) ^ s2_folded_gh_dup_2_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_4_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_4_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_4_folded_hist[6:5], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17075,7 +17554,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_4_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_4_folded_hist[5], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17093,10 +17572,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_4_folded_hist[7], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_3_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_3_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_3_folded_hist[6:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_2[0] @@ -17107,7 +17586,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s2_folded_gh_dup_2_hist_3_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_3_folded_hist[5:0], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17123,10 +17602,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) ^ s2_folded_gh_dup_2_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_2_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_2_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_2_folded_hist[6:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_2[0] @@ -17137,7 +17616,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) ^ s2_folded_gh_dup_2_hist_2_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_2_folded_hist[5:0], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17153,10 +17632,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_2[2] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) ^ s2_folded_gh_dup_2_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_1_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_1_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_1_folded_hist[9:2], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17168,7 +17647,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_2_br_taken_mask_0 ^ s2_folded_gh_dup_2_hist_1_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_1_folded_hist[8:2], (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s2_last_br_num_oh_dup_2[1] @@ -17185,24 +17664,24 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_2_hist_1_folded_hist[10], _predictors_io_out_s2_full_pred_2_br_taken_mask_1 ^ s2_folded_gh_dup_2_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_0_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_0_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_1 + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 ? {s2_folded_gh_dup_2_hist_0_folded_hist[6:0], _predictors_io_out_s2_full_pred_2_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_2_2 + | (_s2_predicted_fh_dup_T_182 ? {s2_folded_gh_dup_2_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_2_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s1_FGH_sel (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_FGH_src_hist_17_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_17_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 @@ -17210,10 +17689,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_17_folded_hist[9], s1_folded_gh_dup_2_hist_17_folded_hist[8:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_17_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 @@ -17222,7 +17701,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_17_folded_hist[8], s1_folded_gh_dup_2_hist_17_folded_hist[7:0], s1_folded_gh_dup_2_hist_17_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17230,10 +17709,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_16_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_16_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_16_folded_hist[9], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17242,10 +17721,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s1_folded_gh_dup_2_hist_16_folded_hist[8], s1_folded_gh_dup_2_hist_16_folded_hist[7:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_16_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -17260,12 +17739,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_16_folded_hist[7], s1_folded_gh_dup_2_hist_16_folded_hist[6:0], s1_folded_gh_dup_2_hist_16_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_15_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_15_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 @@ -17273,10 +17752,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s1_folded_gh_dup_2_hist_15_folded_hist[5], s1_folded_gh_dup_2_hist_15_folded_hist[4:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_15_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 @@ -17285,7 +17764,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_15_folded_hist[4], s1_folded_gh_dup_2_hist_15_folded_hist[3:0], s1_folded_gh_dup_2_hist_15_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17293,25 +17772,25 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s1_folded_gh_dup_2_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_14_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 + ((_s1_predicted_fh_dup_T_126 ? {s1_folded_gh_dup_2_hist_14_folded_hist[7:1], s1_folded_gh_dup_2_hist_14_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_274} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_14_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_14_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_13_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_13_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_13_folded_hist[7:4], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17320,10 +17799,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s1_folded_gh_dup_2_hist_13_folded_hist[3], s1_folded_gh_dup_2_hist_13_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_13_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_13_folded_hist[6:4], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17339,27 +17818,27 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_13_folded_hist[2], s1_folded_gh_dup_2_hist_13_folded_hist[1:0], s1_folded_gh_dup_2_hist_13_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_12_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 + ((_s1_predicted_fh_dup_T_126 ? {s1_folded_gh_dup_2_hist_12_folded_hist[3:1], s1_folded_gh_dup_2_hist_12_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_274} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_12_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_12_folded_hist[1:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_11_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_11_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_11_folded_hist[6:2], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17368,10 +17847,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) ^ s1_folded_gh_dup_2_hist_11_folded_hist[1], s1_folded_gh_dup_2_hist_11_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_11_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_11_folded_hist[5:2], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17386,12 +17865,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) ^ s1_folded_gh_dup_2_hist_11_folded_hist[0], s1_folded_gh_dup_2_hist_11_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_10_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_10_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_10_folded_hist[7:5], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17400,10 +17879,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_10_folded_hist[4], s1_folded_gh_dup_2_hist_10_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_10_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_10_folded_hist[6:5], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17419,12 +17898,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_10_folded_hist[3], s1_folded_gh_dup_2_hist_10_folded_hist[2:0], s1_folded_gh_dup_2_hist_10_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_9_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_9_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_9_folded_hist[5:4], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17433,10 +17912,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_9_folded_hist[3], s1_folded_gh_dup_2_hist_9_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_9_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_9_folded_hist[4], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17452,12 +17931,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_9_folded_hist[2], s1_folded_gh_dup_2_hist_9_folded_hist[1:0], s1_folded_gh_dup_2_hist_9_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_8_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_8_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -17465,10 +17944,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s1_folded_gh_dup_2_hist_8_folded_hist[6], s1_folded_gh_dup_2_hist_8_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_8_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 @@ -17477,7 +17956,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_8_folded_hist[5], s1_folded_gh_dup_2_hist_8_folded_hist[4:0], s1_folded_gh_dup_2_hist_8_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17485,10 +17964,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s1_folded_gh_dup_2_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_7_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_7_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_7_folded_hist[5:1], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17496,10 +17975,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_7_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_7_folded_hist[4:1], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17508,12 +17987,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_6_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_6_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_6_folded_hist[7], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17522,10 +18001,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) ^ s1_folded_gh_dup_2_hist_6_folded_hist[6], s1_folded_gh_dup_2_hist_6_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_6_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s1_last_br_num_oh_dup_2[1] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 @@ -17540,14 +18019,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_6_folded_hist[5], s1_folded_gh_dup_2_hist_6_folded_hist[4:0], s1_folded_gh_dup_2_hist_6_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_5_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_5_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_5_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17556,7 +18035,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s1_folded_gh_dup_2_hist_5_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_5_folded_hist[4:0], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17564,7 +18043,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s1_folded_gh_dup_2_hist_5_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 | s1_last_br_num_oh_dup_2[1] @@ -17572,10 +18051,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) ^ s1_folded_gh_dup_2_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_4_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_4_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_4_folded_hist[6:5], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17584,10 +18063,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s1_folded_gh_dup_2_hist_4_folded_hist[4], s1_folded_gh_dup_2_hist_4_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_4_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_4_folded_hist[5], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17603,14 +18082,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_2_hist_4_folded_hist[3], s1_folded_gh_dup_2_hist_4_folded_hist[2:0], s1_folded_gh_dup_2_hist_4_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_3_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_3_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_3_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17619,7 +18098,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_3_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_3_folded_hist[5:0], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17627,7 +18106,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s1_folded_gh_dup_2_hist_3_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 | s1_last_br_num_oh_dup_2[1] @@ -17635,12 +18114,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) ^ s1_folded_gh_dup_2_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_2_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_2_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_2_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17649,7 +18128,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) ^ s1_folded_gh_dup_2_hist_2_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_2_folded_hist[5:0], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17657,7 +18136,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) ^ s1_folded_gh_dup_2_hist_2_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 | s1_last_br_num_oh_dup_2[1] @@ -17665,10 +18144,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_2[2] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) ^ s1_folded_gh_dup_2_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_1_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_1_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_1_folded_hist[9:2], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17677,10 +18156,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s1_folded_gh_dup_2_hist_1_folded_hist[1], s1_folded_gh_dup_2_hist_1_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 ^ s1_folded_gh_dup_2_hist_1_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_1_folded_hist[8:2], (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s1_last_br_num_oh_dup_2[1] @@ -17695,28 +18174,29 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) ^ s1_folded_gh_dup_2_hist_1_folded_hist[0], s1_folded_gh_dup_2_hist_1_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 ^ s1_folded_gh_dup_2_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_0_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_2_0 + ((_s1_predicted_fh_dup_T_126 ? {s1_folded_gh_dup_2_hist_0_folded_hist[7:1], s1_folded_gh_dup_2_hist_0_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_274} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_1 + | (_s1_predicted_fh_dup_T_154 ? {s1_folded_gh_dup_2_hist_0_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_2_2 + | (_s1_predicted_fh_dup_T_182 ? {s1_folded_gh_dup_2_hist_0_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 - .s3_FGH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] + .s3_FGH_sel + (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_FGH_src_hist_17_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_17_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 @@ -17727,7 +18207,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_17_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 @@ -17744,10 +18224,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s3_folded_gh_dup_2_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_16_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_16_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_16_folded_hist[9], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17759,7 +18239,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_16_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -17776,10 +18256,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_16_folded_hist[10], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_15_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_15_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 @@ -17790,7 +18270,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_15_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 @@ -17807,21 +18287,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) ^ s3_folded_gh_dup_2_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_14_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_14_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_14_folded_hist[6:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_2_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_13_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_13_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_13_folded_hist[7:4], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17833,7 +18313,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_13_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_13_folded_hist[6:4], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17851,21 +18331,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_13_folded_hist[8], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_12_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_12_folded_hist : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_12_folded_hist[2:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0} : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s3_full_pred_2_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_11_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_11_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_11_folded_hist[6:2], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17877,7 +18357,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_11_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_11_folded_hist[5:2], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17894,10 +18374,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_11_folded_hist[7], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_10_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_10_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_10_folded_hist[7:5], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17909,7 +18389,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_10_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_10_folded_hist[6:5], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17927,10 +18407,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_10_folded_hist[8], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_9_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_9_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_9_folded_hist[5:4], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17942,7 +18422,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_9_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_9_folded_hist[4], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -17960,10 +18440,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_9_folded_hist[6], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_8_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_8_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 @@ -17974,7 +18454,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_8_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 @@ -17991,10 +18471,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s3_folded_gh_dup_2_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_7_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_7_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_7_folded_hist[5:1], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18005,7 +18485,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_7_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_7_folded_hist[4:1], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18016,10 +18496,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_6_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_6_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_6_folded_hist[7], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18031,7 +18511,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_6_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s3_last_br_num_oh_dup_2[1] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 @@ -18048,10 +18528,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_6_folded_hist[8], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_5_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_5_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_5_folded_hist[5:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_2[0] @@ -18062,7 +18542,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) ^ s3_folded_gh_dup_2_hist_5_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_5_folded_hist[4:0], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18078,10 +18558,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) ^ s3_folded_gh_dup_2_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_4_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_4_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_4_folded_hist[6:5], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18093,7 +18573,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_4_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_4_folded_hist[5], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18111,10 +18591,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_4_folded_hist[7], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_3_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_3_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_3_folded_hist[6:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_2[0] @@ -18125,7 +18605,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) ^ s3_folded_gh_dup_2_hist_3_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_3_folded_hist[5:0], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18141,10 +18621,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) ^ s3_folded_gh_dup_2_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_2_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_2_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_2_folded_hist[6:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_2[0] @@ -18155,7 +18635,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) ^ s3_folded_gh_dup_2_hist_2_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_2_folded_hist[5:0], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18171,10 +18651,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_2[2] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) ^ s3_folded_gh_dup_2_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_1_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_1_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_1_folded_hist[9:2], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18186,7 +18666,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_2_br_taken_mask_0 ^ s3_folded_gh_dup_2_hist_1_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_1_folded_hist[8:2], (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 | s3_last_br_num_oh_dup_2[1] @@ -18203,55 +18683,73 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_2_hist_1_folded_hist[10], _predictors_io_out_s3_full_pred_2_br_taken_mask_1 ^ s3_folded_gh_dup_2_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_0_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_0_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_1 + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 ? {s3_folded_gh_dup_2_hist_0_folded_hist[6:0], _predictors_io_out_s3_full_pred_2_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_2_2 + | (_s3_predicted_fh_dup_T_182 ? {s3_folded_gh_dup_2_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_2_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 - .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_FGHT_src_hist_17_folded_hist (_GEN_63[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_16_folded_hist (_GEN_64[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_15_folded_hist (_GEN_65[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_14_folded_hist (_GEN_66[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_13_folded_hist (_GEN_67[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_12_folded_hist (_GEN_68[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_11_folded_hist (_GEN_69[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_10_folded_hist (_GEN_70[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_9_folded_hist (_GEN_71[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_8_folded_hist (_GEN_72[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_7_folded_hist (_GEN_73[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_6_folded_hist (_GEN_74[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_5_folded_hist (_GEN_75[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_4_folded_hist (_GEN_76[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_3_folded_hist (_GEN_77[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_2_folded_hist (_GEN_78[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_1_folded_hist (_GEN_79[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_0_folded_hist (_GEN_80[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_2_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_2_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_2_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_2_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_2_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_2_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_2_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_2_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_2_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_2_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_2_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_2_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_2_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_2_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_2_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_2_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_2_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_2_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_63[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_64[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_65[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_66[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_67[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_68[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_69[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_70[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_71[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_72[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_73[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_74[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_75[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_76[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_77[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_78[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_79[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_80[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_2_hist_17_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_2_hist_16_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_2_hist_15_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_2_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_2_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_2_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_2_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_2_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_2_hist_9_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_2_hist_8_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_2_hist_7_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_2_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_2_hist_5_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_2_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_2_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_2_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_2_hist_1_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_2_hist_0_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] .out_res_hist_17_folded_hist (_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist), .out_res_hist_16_folded_hist @@ -18289,12 +18787,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_hist_0_folded_hist (_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist) ); - PriorityMuxModule_4 s0_folded_gh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_4 s0_folded_gh_dup_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_FGH_sel - (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_FGH_src_hist_17_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_17_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 @@ -18305,7 +18803,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_17_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 @@ -18322,10 +18820,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s2_folded_gh_dup_3_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_16_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_16_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_16_folded_hist[9], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18337,7 +18835,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_16_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -18354,10 +18852,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_16_folded_hist[10], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_15_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_15_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 @@ -18368,7 +18866,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_15_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 @@ -18385,21 +18883,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s2_folded_gh_dup_3_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_14_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_14_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_14_folded_hist[6:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_3_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_13_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_13_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_13_folded_hist[7:4], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18411,7 +18909,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_13_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_13_folded_hist[6:4], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18429,21 +18927,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_13_folded_hist[8], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_12_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_12_folded_hist : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_12_folded_hist[2:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0} : 4'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s2_full_pred_3_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s2_FGH_src_hist_11_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_11_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_11_folded_hist[6:2], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18455,7 +18953,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_11_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_11_folded_hist[5:2], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18472,10 +18970,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_11_folded_hist[7], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_10_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_10_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_10_folded_hist[7:5], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18487,7 +18985,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_10_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_10_folded_hist[6:5], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18505,10 +19003,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_10_folded_hist[8], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_9_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_9_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_9_folded_hist[5:4], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18520,7 +19018,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_9_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_9_folded_hist[4], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18538,10 +19036,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_9_folded_hist[6], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_8_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_8_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -18552,7 +19050,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_8_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 @@ -18569,10 +19067,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s2_folded_gh_dup_3_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_7_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_7_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_7_folded_hist[5:1], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18583,7 +19081,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_7_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_7_folded_hist[4:1], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18594,10 +19092,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_6_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_6_folded_hist : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_6_folded_hist[7], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18609,7 +19107,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_6_folded_hist[8]} : 9'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s2_last_br_num_oh_dup_3[1] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 @@ -18626,10 +19124,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_6_folded_hist[8], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_5_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_5_folded_hist : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_5_folded_hist[5:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_3[0] @@ -18640,7 +19138,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s2_folded_gh_dup_3_hist_5_folded_hist[6]} : 7'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_5_folded_hist[4:0], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18656,10 +19154,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) ^ s2_folded_gh_dup_3_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_4_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_4_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_4_folded_hist[6:5], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18671,7 +19169,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_4_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_4_folded_hist[5], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18689,10 +19187,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_4_folded_hist[7], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_3_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_3_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_3_folded_hist[6:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_3[0] @@ -18703,7 +19201,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s2_folded_gh_dup_3_hist_3_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_3_folded_hist[5:0], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18719,10 +19217,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) ^ s2_folded_gh_dup_3_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_2_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_2_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_2_folded_hist[6:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ (s2_last_br_num_oh_dup_3[0] @@ -18733,7 +19231,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) ^ s2_folded_gh_dup_3_hist_2_folded_hist[7]} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_2_folded_hist[5:0], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18749,10 +19247,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s2_last_br_num_oh_dup_3[2] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) ^ s2_folded_gh_dup_3_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_1_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_1_folded_hist : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_1_folded_hist[9:2], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18764,7 +19262,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s2_full_pred_3_br_taken_mask_0 ^ s2_folded_gh_dup_3_hist_1_folded_hist[10]} : 11'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_1_folded_hist[8:2], (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s2_last_br_num_oh_dup_3[1] @@ -18781,24 +19279,24 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s2_folded_gh_dup_3_hist_1_folded_hist[10], _predictors_io_out_s2_full_pred_3_br_taken_mask_1 ^ s2_folded_gh_dup_3_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s2_FGH_src_hist_0_folded_hist - ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_0_folded_hist : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_1 + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 ? {s2_folded_gh_dup_3_hist_0_folded_hist[6:0], _predictors_io_out_s2_full_pred_3_br_taken_mask_0} : 8'h0) - | (_s2_predicted_fh_dup_WIRE_56_3_2 + | (_s2_predicted_fh_dup_T_243 ? {s2_folded_gh_dup_3_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s2_full_pred_3_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s1_FGH_sel (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_FGH_src_hist_17_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_17_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 @@ -18806,10 +19304,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_17_folded_hist[9], s1_folded_gh_dup_3_hist_17_folded_hist[8:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_17_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 @@ -18818,7 +19316,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_17_folded_hist[8], s1_folded_gh_dup_3_hist_17_folded_hist[7:0], s1_folded_gh_dup_3_hist_17_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18826,10 +19324,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_16_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_16_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_16_folded_hist[9], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18838,10 +19336,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s1_folded_gh_dup_3_hist_16_folded_hist[8], s1_folded_gh_dup_3_hist_16_folded_hist[7:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_16_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -18856,12 +19354,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_16_folded_hist[7], s1_folded_gh_dup_3_hist_16_folded_hist[6:0], s1_folded_gh_dup_3_hist_16_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_15_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_15_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 @@ -18869,10 +19367,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s1_folded_gh_dup_3_hist_15_folded_hist[5], s1_folded_gh_dup_3_hist_15_folded_hist[4:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_15_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 @@ -18881,7 +19379,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_15_folded_hist[4], s1_folded_gh_dup_3_hist_15_folded_hist[3:0], s1_folded_gh_dup_3_hist_15_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18889,25 +19387,25 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s1_folded_gh_dup_3_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_14_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 + ((_s1_predicted_fh_dup_T_187 ? {s1_folded_gh_dup_3_hist_14_folded_hist[7:1], s1_folded_gh_dup_3_hist_14_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_277} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_14_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_14_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_13_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_13_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_13_folded_hist[7:4], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18916,10 +19414,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s1_folded_gh_dup_3_hist_13_folded_hist[3], s1_folded_gh_dup_3_hist_13_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_13_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_13_folded_hist[6:4], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18935,27 +19433,27 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_13_folded_hist[2], s1_folded_gh_dup_3_hist_13_folded_hist[1:0], s1_folded_gh_dup_3_hist_13_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_12_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 + ((_s1_predicted_fh_dup_T_187 ? {s1_folded_gh_dup_3_hist_12_folded_hist[3:1], s1_folded_gh_dup_3_hist_12_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_277} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_12_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} : 4'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_12_folded_hist[1:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] .s1_FGH_src_hist_11_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_11_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_11_folded_hist[6:2], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18964,10 +19462,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) ^ s1_folded_gh_dup_3_hist_11_folded_hist[1], s1_folded_gh_dup_3_hist_11_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_11_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_11_folded_hist[5:2], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18982,12 +19480,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) ^ s1_folded_gh_dup_3_hist_11_folded_hist[0], s1_folded_gh_dup_3_hist_11_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_10_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_10_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_10_folded_hist[7:5], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -18996,10 +19494,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_10_folded_hist[4], s1_folded_gh_dup_3_hist_10_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_10_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_10_folded_hist[6:5], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19015,12 +19513,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_10_folded_hist[3], s1_folded_gh_dup_3_hist_10_folded_hist[2:0], s1_folded_gh_dup_3_hist_10_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_9_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_9_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_9_folded_hist[5:4], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19029,10 +19527,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_9_folded_hist[3], s1_folded_gh_dup_3_hist_9_folded_hist[2:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_9_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_9_folded_hist[4], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19048,12 +19546,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_9_folded_hist[2], s1_folded_gh_dup_3_hist_9_folded_hist[1:0], s1_folded_gh_dup_3_hist_9_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_8_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_8_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -19061,10 +19559,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s1_folded_gh_dup_3_hist_8_folded_hist[6], s1_folded_gh_dup_3_hist_8_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_8_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 @@ -19073,7 +19571,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_8_folded_hist[5], s1_folded_gh_dup_3_hist_8_folded_hist[4:0], s1_folded_gh_dup_3_hist_8_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19081,10 +19579,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s1_folded_gh_dup_3_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_7_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_7_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_7_folded_hist[5:1], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19092,10 +19590,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_7_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_7_folded_hist[4:1], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19104,12 +19602,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:230:73, :286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_6_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_6_folded_hist : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_6_folded_hist[7], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19118,10 +19616,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) ^ s1_folded_gh_dup_3_hist_6_folded_hist[6], s1_folded_gh_dup_3_hist_6_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_6_folded_hist[8]} : 9'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s1_last_br_num_oh_dup_3[1] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 @@ -19136,14 +19634,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_6_folded_hist[5], s1_folded_gh_dup_3_hist_6_folded_hist[4:0], s1_folded_gh_dup_3_hist_6_folded_hist[8], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_5_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_5_folded_hist : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_5_folded_hist[5:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19152,7 +19650,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s1_folded_gh_dup_3_hist_5_folded_hist[6]} : 7'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_5_folded_hist[4:0], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19160,7 +19658,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s1_folded_gh_dup_3_hist_5_folded_hist[6], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 | s1_last_br_num_oh_dup_3[1] @@ -19168,10 +19666,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) ^ s1_folded_gh_dup_3_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_4_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_4_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_4_folded_hist[6:5], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19180,10 +19678,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s1_folded_gh_dup_3_hist_4_folded_hist[4], s1_folded_gh_dup_3_hist_4_folded_hist[3:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_4_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_4_folded_hist[5], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19199,14 +19697,14 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 ^ s1_folded_gh_dup_3_hist_4_folded_hist[3], s1_folded_gh_dup_3_hist_4_folded_hist[2:0], s1_folded_gh_dup_3_hist_4_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_3_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_3_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_3_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19215,7 +19713,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_3_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_3_folded_hist[5:0], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19223,7 +19721,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s1_folded_gh_dup_3_hist_3_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 | s1_last_br_num_oh_dup_3[1] @@ -19231,12 +19729,12 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) ^ s1_folded_gh_dup_3_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_2_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_2_folded_hist : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_2_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19245,7 +19743,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) ^ s1_folded_gh_dup_3_hist_2_folded_hist[7]} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_2_folded_hist[5:0], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19253,7 +19751,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) ^ s1_folded_gh_dup_3_hist_2_folded_hist[7], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 | s1_last_br_num_oh_dup_3[1] @@ -19261,10 +19759,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s1_last_br_num_oh_dup_3[2] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) ^ s1_folded_gh_dup_3_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_1_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_1_folded_hist : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_1_folded_hist[9:2], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19273,10 +19771,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s1_folded_gh_dup_3_hist_1_folded_hist[1], s1_folded_gh_dup_3_hist_1_folded_hist[0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 ^ s1_folded_gh_dup_3_hist_1_folded_hist[10]} : 11'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_1_folded_hist[8:2], (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s1_last_br_num_oh_dup_3[1] @@ -19291,28 +19789,29 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) ^ s1_folded_gh_dup_3_hist_1_folded_hist[0], s1_folded_gh_dup_3_hist_1_folded_hist[10], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 ^ s1_folded_gh_dup_3_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:286:84, :287:35, :293:40, :299:46, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s1_FGH_src_hist_0_folded_hist - ((_s1_predicted_fh_dup_WIRE_56_3_0 + ((_s1_predicted_fh_dup_T_187 ? {s1_folded_gh_dup_3_hist_0_folded_hist[7:1], s1_folded_gh_dup_3_hist_0_folded_hist[0] | _s1_possible_predicted_fhs_dup_T_277} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_1 + | (_s1_predicted_fh_dup_T_215 ? {s1_folded_gh_dup_3_hist_0_folded_hist[6:0], - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} : 8'h0) - | (_s1_predicted_fh_dup_WIRE_56_3_2 + | (_s1_predicted_fh_dup_T_243 ? {s1_folded_gh_dup_3_hist_0_folded_hist[5:0], 1'h0, - _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 - .s3_FGH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :230:73, :287:35, :475:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:{29,37}, :485:19, :489:97] + .s3_FGH_sel + (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_FGH_src_hist_17_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_17_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 @@ -19323,7 +19822,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_17_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 @@ -19340,10 +19839,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s3_folded_gh_dup_3_hist_17_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_16_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_16_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_16_folded_hist[9], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19355,7 +19854,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_16_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -19372,10 +19871,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_16_folded_hist[10], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_16_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_15_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_15_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 @@ -19386,7 +19885,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_15_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 @@ -19403,21 +19902,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) ^ s3_folded_gh_dup_3_hist_15_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_14_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_14_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_14_folded_hist[6:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_14_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_3_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_13_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_13_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_13_folded_hist[7:4], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19429,7 +19928,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_13_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_13_folded_hist[6:4], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19447,21 +19946,21 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_13_folded_hist[8], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_13_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_12_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_12_folded_hist : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_12_folded_hist[2:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0} : 4'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_12_folded_hist[1:0], 1'h0, _predictors_io_out_s3_full_pred_3_br_taken_mask_1} - : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + : 4'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] .s3_FGH_src_hist_11_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_11_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_11_folded_hist[6:2], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19473,7 +19972,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_11_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_11_folded_hist[5:2], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19490,10 +19989,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_11_folded_hist[7], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_11_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_10_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_10_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_10_folded_hist[7:5], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19505,7 +20004,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_10_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_10_folded_hist[6:5], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19523,10 +20022,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_10_folded_hist[8], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_10_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_9_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_9_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_9_folded_hist[5:4], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19538,7 +20037,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_9_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_9_folded_hist[4], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19556,10 +20055,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_9_folded_hist[6], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_9_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_8_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_8_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 @@ -19570,7 +20069,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_8_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 @@ -19587,10 +20086,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s3_folded_gh_dup_3_hist_8_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_7_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_7_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_7_folded_hist[5:1], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19601,7 +20100,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_7_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_7_folded_hist[4:1], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19612,10 +20111,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 1'h0, _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_7_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :230:73, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_6_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_6_folded_hist : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_6_folded_hist[7], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19627,7 +20126,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_6_folded_hist[8]} : 9'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s3_last_br_num_oh_dup_3[1] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 @@ -19644,10 +20143,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_6_folded_hist[8], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_6_folded_hist[7]} - : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 9'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_5_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_5_folded_hist : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_5_folded_hist[5:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_3[0] @@ -19658,7 +20157,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) ^ s3_folded_gh_dup_3_hist_5_folded_hist[6]} : 7'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_5_folded_hist[4:0], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19674,10 +20173,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) ^ s3_folded_gh_dup_3_hist_5_folded_hist[5]} - : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 7'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_4_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_4_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_4_folded_hist[6:5], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19689,7 +20188,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_4_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_4_folded_hist[5], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19707,10 +20206,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_4_folded_hist[7], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_4_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_3_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_3_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_3_folded_hist[6:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_3[0] @@ -19721,7 +20220,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) ^ s3_folded_gh_dup_3_hist_3_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_3_folded_hist[5:0], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19737,10 +20236,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) ^ s3_folded_gh_dup_3_hist_3_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_2_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_2_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_2_folded_hist[6:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ (s3_last_br_num_oh_dup_3[0] @@ -19751,7 +20250,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) ^ s3_folded_gh_dup_3_hist_2_folded_hist[7]} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_2_folded_hist[5:0], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19767,10 +20266,10 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 | s3_last_br_num_oh_dup_3[2] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) ^ s3_folded_gh_dup_3_hist_2_folded_hist[6]} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_1_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_1_folded_hist : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_1_folded_hist[9:2], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19782,7 +20281,7 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 _predictors_io_out_s3_full_pred_3_br_taken_mask_0 ^ s3_folded_gh_dup_3_hist_1_folded_hist[10]} : 11'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_1_folded_hist[8:2], (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 | s3_last_br_num_oh_dup_3[1] @@ -19799,55 +20298,73 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 s3_folded_gh_dup_3_hist_1_folded_hist[10], _predictors_io_out_s3_full_pred_3_br_taken_mask_1 ^ s3_folded_gh_dup_3_hist_1_folded_hist[9]} - : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + : 11'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :286:84, :289:35, :295:40, :301:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:232:30, :267:48, :269:11, :291:54, :485:19, :489:97] .s3_FGH_src_hist_0_folded_hist - ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_0_folded_hist : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_1 + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 ? {s3_folded_gh_dup_3_hist_0_folded_hist[6:0], _predictors_io_out_s3_full_pred_3_br_taken_mask_0} : 8'h0) - | (_s3_predicted_fh_dup_WIRE_56_3_2 + | (_s3_predicted_fh_dup_T_243 ? {s3_folded_gh_dup_3_hist_0_folded_hist[5:0], 1'h0, _predictors_io_out_s3_full_pred_3_br_taken_mask_1} - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 - .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_FGHT_src_hist_17_folded_hist (_GEN_81[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_16_folded_hist (_GEN_82[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_15_folded_hist (_GEN_83[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_14_folded_hist (_GEN_84[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_13_folded_hist (_GEN_85[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_12_folded_hist (_GEN_86[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_11_folded_hist (_GEN_87[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_10_folded_hist (_GEN_88[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_9_folded_hist (_GEN_89[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_8_folded_hist (_GEN_90[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_7_folded_hist (_GEN_91[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_6_folded_hist (_GEN_92[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_5_folded_hist (_GEN_93[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_4_folded_hist (_GEN_94[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_3_folded_hist (_GEN_95[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_2_folded_hist (_GEN_96[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_1_folded_hist (_GEN_97[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .redirect_FGHT_src_hist_0_folded_hist (_GEN_98[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 - .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_3_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_3_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_3_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_3_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_3_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_3_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_3_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_3_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_3_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_3_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_3_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_3_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_3_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_3_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_3_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_3_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_3_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 - .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_3_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :230:73, :289:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:301:37, :485:19, :489:97] + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_81[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_82[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_83[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_84[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_85[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_86[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_87[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_88[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_89[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_90[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_91[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_92[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_93[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_94[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_95[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_96[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_97[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_98[do_redirect_dup_next_bits_r_cfiUpdate_shift]), // @[utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24] + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_3_hist_17_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_3_hist_16_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_3_hist_15_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_3_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_3_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_3_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_3_hist_11_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_3_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_3_hist_9_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_3_hist_8_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_3_hist_7_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_3_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_3_hist_5_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_3_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_3_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_3_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_3_hist_1_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_3_hist_0_folded_hist), // @[src/main/scala/xiangshan/frontend/BPU.scala:286:63] .out_res_hist_17_folded_hist (_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist), .out_res_hist_16_folded_hist @@ -19885,414 +20402,415 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_hist_0_folded_hist (_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist) ); - PriorityMuxModule_8 s0_ghist_ptr_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_8 s0_ghist_ptr_dup_0_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_GHPtr_sel - (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_GHPtr_src_flag - (_s2_predicted_ghist_ptr_dup_WIRE_56_0_0 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_0_1 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_0_2 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s2_predicted_ghist_ptr_dup_T_4 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s2_predicted_ghist_ptr_dup_T_32 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s2_predicted_ghist_ptr_dup_T_60 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s2_GHPtr_src_value - ((_s2_predicted_ghist_ptr_dup_WIRE_56_0_0 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + ((_s2_predicted_ghist_ptr_dup_T_4 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_0_1 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + | (_s2_predicted_ghist_ptr_dup_T_32 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_0_2 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + | (_s2_predicted_ghist_ptr_dup_T_60 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] .s1_GHPtr_sel (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_GHPtr_src_flag - (_s1_predicted_ghist_ptr_dup_WIRE_56_0_0 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_0_1 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_0_2 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s1_predicted_ghist_ptr_dup_T_4 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s1_predicted_ghist_ptr_dup_T_32 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s1_predicted_ghist_ptr_dup_T_60 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s1_GHPtr_src_value - ((_s1_predicted_ghist_ptr_dup_WIRE_56_0_0 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + ((_s1_predicted_ghist_ptr_dup_T_4 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_0_1 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + | (_s1_predicted_ghist_ptr_dup_T_32 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_0_2 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .s3_GHPtr_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + | (_s1_predicted_ghist_ptr_dup_T_60 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .s3_GHPtr_sel (s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_GHPtr_src_flag - (_s3_predicted_ghist_ptr_dup_WIRE_56_0_0 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_0_1 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_0_2 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s3_predicted_ghist_ptr_dup_T_4 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s3_predicted_ghist_ptr_dup_T_32 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s3_predicted_ghist_ptr_dup_T_60 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s3_GHPtr_src_value - ((_s3_predicted_ghist_ptr_dup_WIRE_56_0_0 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + ((_s3_predicted_ghist_ptr_dup_T_4 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_0_1 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + | (_s3_predicted_ghist_ptr_dup_T_32 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_0_2 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 - .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_0_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_0_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + | (_s3_predicted_ghist_ptr_dup_T_60 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_1[8])), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_1[7:0]), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_0_flag), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_0_value), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] .out_res_flag (_s0_ghist_ptr_dup_0_ppm_out_res_flag), .out_res_value (_s0_ghist_ptr_dup_0_ppm_out_res_value) ); - PriorityMuxModule_8 s0_ghist_ptr_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_8 s0_ghist_ptr_dup_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_GHPtr_sel - (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_GHPtr_src_flag - (_s2_predicted_ghist_ptr_dup_WIRE_56_1_0 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_1_1 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_1_2 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s2_predicted_ghist_ptr_dup_T_65 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s2_predicted_ghist_ptr_dup_T_93 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s2_predicted_ghist_ptr_dup_T_121 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s2_GHPtr_src_value - ((_s2_predicted_ghist_ptr_dup_WIRE_56_1_0 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + ((_s2_predicted_ghist_ptr_dup_T_65 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_1_1 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + | (_s2_predicted_ghist_ptr_dup_T_93 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_1_2 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + | (_s2_predicted_ghist_ptr_dup_T_121 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] .s1_GHPtr_sel (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_GHPtr_src_flag - (_s1_predicted_ghist_ptr_dup_WIRE_56_1_0 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_1_1 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_1_2 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s1_predicted_ghist_ptr_dup_T_65 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s1_predicted_ghist_ptr_dup_T_93 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s1_predicted_ghist_ptr_dup_T_121 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s1_GHPtr_src_value - ((_s1_predicted_ghist_ptr_dup_WIRE_56_1_0 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + ((_s1_predicted_ghist_ptr_dup_T_65 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_1_1 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + | (_s1_predicted_ghist_ptr_dup_T_93 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_1_2 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .s3_GHPtr_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + | (_s1_predicted_ghist_ptr_dup_T_121 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .s3_GHPtr_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_GHPtr_src_flag - (_s3_predicted_ghist_ptr_dup_WIRE_56_1_0 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_1_1 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_1_2 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s3_predicted_ghist_ptr_dup_T_65 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s3_predicted_ghist_ptr_dup_T_93 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s3_predicted_ghist_ptr_dup_T_121 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s3_GHPtr_src_value - ((_s3_predicted_ghist_ptr_dup_WIRE_56_1_0 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + ((_s3_predicted_ghist_ptr_dup_T_65 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_1_1 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + | (_s3_predicted_ghist_ptr_dup_T_93 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_1_2 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 - .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_1_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_1_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + | (_s3_predicted_ghist_ptr_dup_T_121 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_6[8])), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_6[7:0]), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_1_flag), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_1_value), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] .out_res_flag (_s0_ghist_ptr_dup_1_ppm_out_res_flag), .out_res_value (_s0_ghist_ptr_dup_1_ppm_out_res_value) ); - PriorityMuxModule_8 s0_ghist_ptr_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_8 s0_ghist_ptr_dup_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_GHPtr_sel - (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_GHPtr_src_flag - (_s2_predicted_ghist_ptr_dup_WIRE_56_2_0 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_2_1 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_2_2 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s2_predicted_ghist_ptr_dup_T_126 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s2_predicted_ghist_ptr_dup_T_154 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s2_predicted_ghist_ptr_dup_T_182 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s2_GHPtr_src_value - ((_s2_predicted_ghist_ptr_dup_WIRE_56_2_0 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + ((_s2_predicted_ghist_ptr_dup_T_126 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_2_1 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + | (_s2_predicted_ghist_ptr_dup_T_154 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_2_2 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + | (_s2_predicted_ghist_ptr_dup_T_182 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] .s1_GHPtr_sel (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_GHPtr_src_flag - (_s1_predicted_ghist_ptr_dup_WIRE_56_2_0 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_2_1 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_2_2 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s1_predicted_ghist_ptr_dup_T_126 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s1_predicted_ghist_ptr_dup_T_154 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s1_predicted_ghist_ptr_dup_T_182 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s1_GHPtr_src_value - ((_s1_predicted_ghist_ptr_dup_WIRE_56_2_0 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + ((_s1_predicted_ghist_ptr_dup_T_126 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_2_1 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + | (_s1_predicted_ghist_ptr_dup_T_154 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_2_2 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .s3_GHPtr_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + | (_s1_predicted_ghist_ptr_dup_T_182 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .s3_GHPtr_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_GHPtr_src_flag - (_s3_predicted_ghist_ptr_dup_WIRE_56_2_0 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_2_1 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_2_2 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s3_predicted_ghist_ptr_dup_T_126 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s3_predicted_ghist_ptr_dup_T_154 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s3_predicted_ghist_ptr_dup_T_182 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s3_GHPtr_src_value - ((_s3_predicted_ghist_ptr_dup_WIRE_56_2_0 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + ((_s3_predicted_ghist_ptr_dup_T_126 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_2_1 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + | (_s3_predicted_ghist_ptr_dup_T_154 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_2_2 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 - .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_2_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_2_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + | (_s3_predicted_ghist_ptr_dup_T_182 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_11[8])), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_11[7:0]), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_2_flag), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_2_value), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] .out_res_flag (_s0_ghist_ptr_dup_2_ppm_out_res_flag), .out_res_value (_s0_ghist_ptr_dup_2_ppm_out_res_value) ); - PriorityMuxModule_8 s0_ghist_ptr_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_8 s0_ghist_ptr_dup_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_GHPtr_sel - (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_GHPtr_src_flag - (_s2_predicted_ghist_ptr_dup_WIRE_56_3_0 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_3_1 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) - | _s2_predicted_ghist_ptr_dup_WIRE_56_3_2 - & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s2_predicted_ghist_ptr_dup_T_187 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s2_predicted_ghist_ptr_dup_T_215 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s2_predicted_ghist_ptr_dup_T_243 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s2_GHPtr_src_value - ((_s2_predicted_ghist_ptr_dup_WIRE_56_3_0 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + ((_s2_predicted_ghist_ptr_dup_T_187 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_3_1 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + | (_s2_predicted_ghist_ptr_dup_T_215 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] : 8'h0) - | (_s2_predicted_ghist_ptr_dup_WIRE_56_3_2 - ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + | (_s2_predicted_ghist_ptr_dup_T_243 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] .s1_GHPtr_sel (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_GHPtr_src_flag - (_s1_predicted_ghist_ptr_dup_WIRE_56_3_0 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_3_1 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) - | _s1_predicted_ghist_ptr_dup_WIRE_56_3_2 - & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s1_predicted_ghist_ptr_dup_T_187 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s1_predicted_ghist_ptr_dup_T_215 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s1_predicted_ghist_ptr_dup_T_243 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s1_GHPtr_src_value - ((_s1_predicted_ghist_ptr_dup_WIRE_56_3_0 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + ((_s1_predicted_ghist_ptr_dup_T_187 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_3_1 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + | (_s1_predicted_ghist_ptr_dup_T_215 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] : 8'h0) - | (_s1_predicted_ghist_ptr_dup_WIRE_56_3_2 - ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .s3_GHPtr_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + | (_s1_predicted_ghist_ptr_dup_T_243 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .s3_GHPtr_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_GHPtr_src_flag - (_s3_predicted_ghist_ptr_dup_WIRE_56_3_0 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_3_1 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) - | _s3_predicted_ghist_ptr_dup_WIRE_56_3_2 - & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + (_s3_predicted_ghist_ptr_dup_T_187 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s3_predicted_ghist_ptr_dup_T_215 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s3_predicted_ghist_ptr_dup_T_243 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] .s3_GHPtr_src_value - ((_s3_predicted_ghist_ptr_dup_WIRE_56_3_0 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + ((_s3_predicted_ghist_ptr_dup_T_187 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_3_1 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + | (_s3_predicted_ghist_ptr_dup_T_215 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] : 8'h0) - | (_s3_predicted_ghist_ptr_dup_WIRE_56_3_2 - ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] - : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 - .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} - .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_3_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 - .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_3_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + | (_s3_predicted_ghist_ptr_dup_T_243 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:485:19, :489:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_16[8])), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21] + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_16[7:0]), // @[utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}] + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_3_flag), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_3_value), // @[src/main/scala/xiangshan/frontend/BPU.scala:323:63] .out_res_flag (_s0_ghist_ptr_dup_3_ppm_out_res_flag), .out_res_value (_s0_ghist_ptr_dup_3_ppm_out_res_value) ); - PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_AFHOB_sel - (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .s1_AFHOB_sel (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_sel + (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .redirect_AFHOB_src_afhob_5_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_4_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_4_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_2_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_1_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_1_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_0_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] .out_res_afhob_5_bits_0 (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0), .out_res_afhob_5_bits_1 @@ -20342,150 +20860,151 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_afhob_0_bits_3 (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3) ); - PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_AFHOB_sel - (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .s1_AFHOB_sel (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_sel + (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .redirect_AFHOB_src_afhob_5_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_4_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_4_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_2_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_1_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_1_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_0_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] .out_res_afhob_5_bits_0 (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0), .out_res_afhob_5_bits_1 @@ -20535,150 +21054,151 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_afhob_0_bits_3 (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3) ); - PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_AFHOB_sel - (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .s1_AFHOB_sel (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} - .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_sel + (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] .redirect_AFHOB_src_afhob_5_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_5_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_4_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_4_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_3_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_2_bits_0 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_2_bits_3 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_1_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] .redirect_AFHOB_src_afhob_1_bits_2 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] .redirect_AFHOB_src_afhob_0_bits_1 - (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 - .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 - .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 - .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20, utility/src/main/scala/utility/BitUtils.scala:33:27, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46] + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:340:20] + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:298:85] .out_res_afhob_5_bits_0 (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0), .out_res_afhob_5_bits_1 @@ -20728,12050 +21248,12053 @@ module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 .out_res_afhob_0_bits_3 (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3) ); - PriorityMuxModule_16 s0_last_br_num_oh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_16 s0_last_br_num_oh_dup_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_BrNumOH_sel - (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_BrNumOH_src - ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 & ~_GEN_25 + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 & ~_GEN_25 & _predictors_io_out_s2_full_pred_1_hit, _predictors_io_out_s2_full_pred_1_slot_valids_0 - & (_GEN_25 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + & (_GEN_25 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) & _predictors_io_out_s2_full_pred_1_hit, ~_predictors_io_out_s2_full_pred_1_hit | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :615:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] .s1_BrNumOH_sel (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_BrNumOH_src - ({_s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit, + ({_s1_ghv_wdatas_T_190589 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit, _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 & _predictors_io_out_s1_full_pred_1_hit, - ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} - .s3_BrNumOH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :512:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,97}] + .s3_BrNumOH_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_BrNumOH_src - ({_s3_predicted_fh_dup_WIRE_21_1 & ~_GEN_36 & _predictors_io_out_s3_full_pred_1_hit, + ({_s3_ghv_wdatas_T_58023 & ~_GEN_36 & _predictors_io_out_s3_full_pred_1_hit, _predictors_io_out_s3_full_pred_1_slot_valids_0 - & (_GEN_36 | ~_s3_predicted_fh_dup_WIRE_21_1) - & _predictors_io_out_s3_full_pred_1_hit, + & (_GEN_36 | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit, ~_predictors_io_out_s3_full_pred_1_hit - | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 - | _s3_predicted_fh_dup_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} - .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_BrNumOH_src (_thisBrNumOH_dup_T_1[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} - .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :700:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_1[2:0]), // @[src/main/scala/chisel3/util/OneHot.scala:65:{12,27}] + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] .out_res (_s0_last_br_num_oh_dup_1_ppm_out_res) ); - PriorityMuxModule_16 s0_last_br_num_oh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_16 s0_last_br_num_oh_dup_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_BrNumOH_sel - (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_BrNumOH_src - ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 & ~_GEN_26 + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 & ~_GEN_26 & _predictors_io_out_s2_full_pred_2_hit, _predictors_io_out_s2_full_pred_2_slot_valids_0 - & (_GEN_26 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + & (_GEN_26 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) & _predictors_io_out_s2_full_pred_2_hit, ~_predictors_io_out_s2_full_pred_2_hit | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :615:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] .s1_BrNumOH_sel (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_BrNumOH_src - ({_s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit, + ({_s1_ghv_wdatas_T_190650 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit, _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 & _predictors_io_out_s1_full_pred_2_hit, - ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} - .s3_BrNumOH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :512:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,97}] + .s3_BrNumOH_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_BrNumOH_src - ({_s3_predicted_fh_dup_WIRE_35_1 & ~_GEN_37 & _predictors_io_out_s3_full_pred_2_hit, + ({_s3_ghv_wdatas_T_58048 & ~_GEN_37 & _predictors_io_out_s3_full_pred_2_hit, _predictors_io_out_s3_full_pred_2_slot_valids_0 - & (_GEN_37 | ~_s3_predicted_fh_dup_WIRE_35_1) - & _predictors_io_out_s3_full_pred_2_hit, + & (_GEN_37 | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit, ~_predictors_io_out_s3_full_pred_2_hit - | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 - | _s3_predicted_fh_dup_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} - .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_BrNumOH_src (_thisBrNumOH_dup_T_2[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} - .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :700:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_2[2:0]), // @[src/main/scala/chisel3/util/OneHot.scala:65:{12,27}] + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_2), // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] .out_res (_s0_last_br_num_oh_dup_2_ppm_out_res) ); - PriorityMuxModule_16 s0_last_br_num_oh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + PriorityMuxModule_16 s0_last_br_num_oh_dup_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] .s2_BrNumOH_sel - (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_BrNumOH_src - ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 & ~_GEN_27 + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 & ~_GEN_27 & _predictors_io_out_s2_full_pred_3_hit, _predictors_io_out_s2_full_pred_3_slot_valids_0 - & (_GEN_27 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + & (_GEN_27 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) & _predictors_io_out_s2_full_pred_3_hit, ~_predictors_io_out_s2_full_pred_3_hit | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 - | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :615:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] .s1_BrNumOH_sel (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 - & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:272:65, :606:28, :685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_BrNumOH_src - ({_s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit, + ({_s1_ghv_wdatas_T_190711 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit, _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 & _predictors_io_out_s1_full_pred_3_hit, - ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} - .s3_BrNumOH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :512:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,97}] + .s3_BrNumOH_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), // @[src/main/scala/xiangshan/frontend/BPU.scala:685:28, utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_BrNumOH_src - ({_s3_predicted_fh_dup_WIRE_49_1 & ~_GEN_38 & _predictors_io_out_s3_full_pred_3_hit, + ({_s3_ghv_wdatas_T_58073 & ~_GEN_38 & _predictors_io_out_s3_full_pred_3_hit, _predictors_io_out_s3_full_pred_3_slot_valids_0 - & (_GEN_38 | ~_s3_predicted_fh_dup_WIRE_49_1) - & _predictors_io_out_s3_full_pred_3_hit, + & (_GEN_38 | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit, ~_predictors_io_out_s3_full_pred_3_hit - | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 - | _s3_predicted_fh_dup_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} - .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 - .redirect_BrNumOH_src (_thisBrNumOH_dup_T_3[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} - .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073)}), // @[src/main/scala/xiangshan/frontend/BPU.scala:226:26, :700:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :474:32, :485:{14,19,22,41}, :488:9, :489:{34,37,97}] + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22] + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_3[2:0]), // @[src/main/scala/chisel3/util/OneHot.scala:65:{12,27}] + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:292:73] .out_res (_s0_last_br_num_oh_dup_3_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_0_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :583:58, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_0_T & ~_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_0_T & ~_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :495:58, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :664:58, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + (~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :760:50, :763:52 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :763:50, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_0_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_1_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_1_T & ~_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_1_T & ~_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_1_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_2_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_2_T & ~_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_2_T & ~_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_2_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_3_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_3_T & ~_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_3_T & ~_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_3_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_4_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_4_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_4_T & ~_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_4_T & ~_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_4_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_5_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_5_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_5_T & ~_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_5_T & ~_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_5_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_6_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_6_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_6_T & ~_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_6_T & ~_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_6_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_7_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_7_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_7_T & ~_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_7_T & ~_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_7_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_8_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_8_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_8_T & ~_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_8_T & ~_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_8_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_9_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_9_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_9_T & ~_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_9_T & ~_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_9_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_10_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_10_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_10_T & ~_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_10_T & ~_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_10_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_11_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_11_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_11_T & ~_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_11_T & ~_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_11_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_12_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_12_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_12_T & ~_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_12_T & ~_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_12_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_13_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_13_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_13_T & ~_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_13_T & ~_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_13_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_14_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_14_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_14_T & ~_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_14_T & ~_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_14_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_15_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_15_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h10 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_15_T & ~_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_15_T & ~_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_15_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_16_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_16_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h11 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_16_T & ~_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_16_T & ~_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_16_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_17_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_17_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h12 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_17_T & ~_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_17_T & ~_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_17_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_18_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_18_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h13 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_18_T & ~_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_18_T & ~_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_18_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_19_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_19_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h14 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_19_T & ~_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_19_T & ~_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_19_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_20_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_20_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h15 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_20_T & ~_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_20_T & ~_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_20_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_21_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_21_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h16 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_21_T & ~_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_21_T & ~_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_21_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_22_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_22_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h17 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_22_T & ~_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_22_T & ~_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_22_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_23_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_23_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h18 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_23_T & ~_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_23_T & ~_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_23_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_24_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_24_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h19 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_24_T & ~_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_24_T & ~_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_24_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_25_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_25_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_25_T & ~_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_25_T & ~_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_25_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_26_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_26_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_26_T & ~_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_26_T & ~_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_26_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_27_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_27_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_27_T & ~_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_27_T & ~_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_27_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_28_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_28_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_28_T & ~_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_28_T & ~_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_28_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_29_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_29_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_29_T & ~_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_29_T & ~_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_29_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_30_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_30_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h1F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_30_T & ~_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_30_T & ~_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_30_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_31_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_31_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h20 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_31_T & ~_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_31_T & ~_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_31_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_32_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_32_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h21 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_32_T & ~_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_32_T & ~_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_32_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_33_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_33_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h22 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_33_T & ~_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_33_T & ~_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_33_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_34_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_34_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h23 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_34_T & ~_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_34_T & ~_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_34_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_35_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_35_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h24 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_35_T & ~_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_35_T & ~_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_35_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_36_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_36_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h25 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_36_T & ~_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_36_T & ~_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_36_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_37_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_37_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h26 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_37_T & ~_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_37_T & ~_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_37_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_38_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_38_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h27 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_38_T & ~_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_38_T & ~_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_38_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_39_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_39_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h28 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_39_T & ~_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_39_T & ~_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_39_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_40_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_40_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h29 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_40_T & ~_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_40_T & ~_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_40_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_41_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_41_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_41_T & ~_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_41_T & ~_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_41_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_42_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_42_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_42_T & ~_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_42_T & ~_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_42_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_43_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_43_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_43_T & ~_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_43_T & ~_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_43_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_44_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_44_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_44_T & ~_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_44_T & ~_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_44_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_45_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_45_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_45_T & ~_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_45_T & ~_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_45_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_46_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_46_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h2F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_46_T & ~_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_46_T & ~_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_46_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_47_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_47_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h30 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_47_T & ~_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_47_T & ~_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_47_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_48_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_48_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h31 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_48_T & ~_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_48_T & ~_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_48_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_49_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_49_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h32 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_49_T & ~_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_49_T & ~_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_49_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_50_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_50_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h33 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_50_T & ~_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_50_T & ~_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_50_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_51_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_51_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h34 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_51_T & ~_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_51_T & ~_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_51_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_52_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_52_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h35 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_52_T & ~_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_52_T & ~_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_52_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_53_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_53_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h36 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_53_T & ~_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_53_T & ~_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_53_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_54_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_54_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h37 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_54_T & ~_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_54_T & ~_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_54_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_55_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_55_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h38 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_55_T & ~_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_55_T & ~_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_55_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_56_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_56_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h39 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_56_T & ~_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_56_T & ~_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_56_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_57_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_57_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_57_T & ~_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_57_T & ~_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_57_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_58_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_58_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_58_T & ~_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_58_T & ~_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_58_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_59_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_59_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_59_T & ~_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_59_T & ~_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_59_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_60_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_60_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_60_T & ~_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_60_T & ~_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_60_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_61_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_61_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_61_T & ~_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_61_T & ~_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_61_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_62_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_62_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h3F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_62_T & ~_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_62_T & ~_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_62_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_63_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_63_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h40 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_63_T & ~_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_63_T & ~_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_63_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_64_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_64_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h41 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_64_T & ~_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_64_T & ~_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_64_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_65_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_65_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h42 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_65_T & ~_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_65_T & ~_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_65_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_66_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_66_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h43 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_66_T & ~_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_66_T & ~_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_66_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_67_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_67_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h44 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_67_T & ~_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_67_T & ~_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_67_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_68_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_68_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h45 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_68_T & ~_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_68_T & ~_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_68_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_69_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_69_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h46 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_69_T & ~_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_69_T & ~_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_69_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_70_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_70_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h47 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_70_T & ~_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_70_T & ~_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_70_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_71_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_71_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h48 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_71_T & ~_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_71_T & ~_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_71_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_72_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_72_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h49 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_72_T & ~_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_72_T & ~_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_72_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_73_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_73_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_73_T & ~_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_73_T & ~_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_73_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_74_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_74_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_74_T & ~_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_74_T & ~_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_74_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_75_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_75_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_75_T & ~_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_75_T & ~_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_75_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_76_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_76_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_76_T & ~_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_76_T & ~_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_76_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_77_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_77_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_77_T & ~_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_77_T & ~_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_77_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_78_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_78_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h4F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_78_T & ~_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_78_T & ~_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_78_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_79_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_79_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h50 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_79_T & ~_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_79_T & ~_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_79_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_80_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_80_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h51 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_80_T & ~_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_80_T & ~_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_80_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_81_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_81_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h52 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_81_T & ~_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_81_T & ~_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_81_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_82_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_82_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h53 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_82_T & ~_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_82_T & ~_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_82_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_83_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_83_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h54 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_83_T & ~_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_83_T & ~_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_83_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_84_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_84_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h55 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_84_T & ~_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_84_T & ~_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_84_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_85_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_85_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h56 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_85_T & ~_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_85_T & ~_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_85_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_86_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_86_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h57 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_86_T & ~_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_86_T & ~_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_86_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_87_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_87_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h58 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_87_T & ~_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_87_T & ~_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_87_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_88_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_88_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h59 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_88_T & ~_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_88_T & ~_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_88_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_89_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_89_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_89_T & ~_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_89_T & ~_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_89_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_90_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_90_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_90_T & ~_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_90_T & ~_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_90_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_91_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_91_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_91_T & ~_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_91_T & ~_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_91_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_92_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_92_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_92_T & ~_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_92_T & ~_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_92_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_93_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_93_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_93_T & ~_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_93_T & ~_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_93_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_94_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_94_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h5F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_94_T & ~_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_94_T & ~_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_94_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_95_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_95_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h60 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_95_T & ~_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_95_T & ~_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_95_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_96_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_96_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h61 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_96_T & ~_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_96_T & ~_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_96_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_97_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_97_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h62 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_97_T & ~_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_97_T & ~_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_97_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_98_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_98_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h63 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_98_T & ~_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_98_T & ~_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_98_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_99_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_99_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h64 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_99_T & ~_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_99_T & ~_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_99_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_100_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_100_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h65 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_100_T & ~_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_100_T & ~_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_100_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_101_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_101_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h66 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_101_T & ~_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_101_T & ~_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_101_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_102_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_102_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h67 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_102_T & ~_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_102_T & ~_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_102_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_103_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_103_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h68 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_103_T & ~_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_103_T & ~_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_103_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_104_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_104_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h69 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_104_T & ~_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_104_T & ~_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_104_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_105_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_105_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_105_T & ~_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_105_T & ~_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_105_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_106_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_106_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_106_T & ~_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_106_T & ~_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_106_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_107_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_107_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_107_T & ~_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_107_T & ~_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_107_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_108_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_108_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_108_T & ~_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_108_T & ~_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_108_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_109_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_109_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_109_T & ~_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_109_T & ~_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_109_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_110_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_110_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h6F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_110_T & ~_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_110_T & ~_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_110_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_111_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_111_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h70 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_111_T & ~_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_111_T & ~_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_111_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_112_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_112_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h71 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_112_T & ~_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_112_T & ~_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_112_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_113_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_113_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h72 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_113_T & ~_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_113_T & ~_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_113_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_114_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_114_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h73 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_114_T & ~_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_114_T & ~_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_114_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_115_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_115_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h74 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_115_T & ~_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_115_T & ~_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_115_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_116_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_116_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h75 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_116_T & ~_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_116_T & ~_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_116_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_117_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_117_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h76 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_117_T & ~_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_117_T & ~_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_117_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_118_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_118_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h77 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_118_T & ~_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_118_T & ~_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_118_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_119_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_119_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h78 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_119_T & ~_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_119_T & ~_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_119_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_120_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_120_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h79 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_120_T & ~_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_120_T & ~_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_120_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_121_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_121_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_121_T & ~_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_121_T & ~_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_121_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_122_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_122_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_122_T & ~_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_122_T & ~_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_122_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_123_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_123_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_123_T & ~_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_123_T & ~_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_123_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_124_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_124_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_124_T & ~_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_124_T & ~_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_124_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_125_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_125_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_125_T & ~_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_125_T & ~_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_125_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_126_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_126_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h7F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_126_T & ~_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_126_T & ~_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_126_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_127_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_127_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h80 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_127_T & ~_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_127_T & ~_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_127_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_128_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_128_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h81 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_128_T & ~_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_128_T & ~_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_128_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_129_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_129_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h82 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_129_T & ~_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_129_T & ~_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_129_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_130_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_130_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h83 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_130_T & ~_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_130_T & ~_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_130_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_131_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_131_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h84 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_131_T & ~_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_131_T & ~_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_131_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_132_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_132_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h85 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_132_T & ~_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_132_T & ~_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_132_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_133_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_133_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h86 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_133_T & ~_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_133_T & ~_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_133_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_134_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_134_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h87 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_134_T & ~_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_134_T & ~_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_134_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_135_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_135_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h88 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_135_T & ~_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_135_T & ~_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_135_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_136_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_136_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h89 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_136_T & ~_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_136_T & ~_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_136_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_137_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_137_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_137_T & ~_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_137_T & ~_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_137_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_138_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_138_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_138_T & ~_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_138_T & ~_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_138_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_139_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_139_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_139_T & ~_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_139_T & ~_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_139_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_140_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_140_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_140_T & ~_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_140_T & ~_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_140_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_141_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_141_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_141_T & ~_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_141_T & ~_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_141_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_142_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_142_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h8F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_142_T & ~_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_142_T & ~_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_142_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_143_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_143_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h90 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_143_T & ~_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_143_T & ~_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_143_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_144_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_144_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h91 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_144_T & ~_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_144_T & ~_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_144_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_145_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_145_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h92 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_145_T & ~_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_145_T & ~_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_145_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_146_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_146_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h93 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_146_T & ~_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_146_T & ~_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_146_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_147_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_147_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h94 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_147_T & ~_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_147_T & ~_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_147_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_148_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_148_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h95 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_148_T & ~_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_148_T & ~_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_148_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_149_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_149_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h96 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_149_T & ~_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_149_T & ~_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_149_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_150_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_150_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h97 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_150_T & ~_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_150_T & ~_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_150_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_151_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_151_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h98 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_151_T & ~_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_151_T & ~_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_151_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_152_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_152_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h99 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_152_T & ~_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_152_T & ~_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_152_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_153_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_153_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9A - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_153_T & ~_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_153_T & ~_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_153_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_154_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_154_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9B - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_154_T & ~_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_154_T & ~_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_154_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_155_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_155_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9C - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_155_T & ~_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_155_T & ~_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_155_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_156_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_156_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9D - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_156_T & ~_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_156_T & ~_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_156_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_157_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_157_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9E - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_157_T & ~_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_157_T & ~_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_157_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_158_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_158_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'h9F - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_158_T & ~_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_158_T & ~_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_158_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_159_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_159_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_159_T & ~_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_159_T & ~_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_159_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_160_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_160_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_160_T & ~_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_160_T & ~_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_160_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_161_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_161_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_161_T & ~_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_161_T & ~_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_161_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_162_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_162_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_162_T & ~_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_162_T & ~_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_162_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_163_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_163_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_163_T & ~_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_163_T & ~_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_163_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_164_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_164_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_164_T & ~_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_164_T & ~_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_164_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_165_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_165_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_165_T & ~_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_165_T & ~_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_165_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_166_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_166_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_166_T & ~_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_166_T & ~_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_166_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_167_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_167_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_167_T & ~_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_167_T & ~_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_167_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_168_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_168_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hA9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_168_T & ~_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_168_T & ~_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_168_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_169_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_169_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_169_T & ~_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_169_T & ~_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_169_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_170_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_170_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_170_T & ~_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_170_T & ~_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_170_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_171_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_171_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_171_T & ~_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_171_T & ~_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_171_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_172_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_172_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_172_T & ~_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_172_T & ~_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_172_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_173_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_173_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_173_T & ~_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_173_T & ~_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_173_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_174_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_174_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hAF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_174_T & ~_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_174_T & ~_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_174_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_175_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_175_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_175_T & ~_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_175_T & ~_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_175_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_176_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_176_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_176_T & ~_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_176_T & ~_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_176_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_177_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_177_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_177_T & ~_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_177_T & ~_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_177_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_178_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_178_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_178_T & ~_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_178_T & ~_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_178_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_179_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_179_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_179_T & ~_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_179_T & ~_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_179_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_180_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_180_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_180_T & ~_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_180_T & ~_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_180_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_181_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_181_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_181_T & ~_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_181_T & ~_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_181_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_182_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_182_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_182_T & ~_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_182_T & ~_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_182_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_183_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_183_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_183_T & ~_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_183_T & ~_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_183_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_184_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_184_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hB9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_184_T & ~_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_184_T & ~_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_184_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_185_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_185_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_185_T & ~_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_185_T & ~_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_185_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_186_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_186_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_186_T & ~_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_186_T & ~_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_186_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_187_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_187_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_187_T & ~_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_187_T & ~_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_187_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_188_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_188_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_188_T & ~_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_188_T & ~_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_188_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_189_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_189_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_189_T & ~_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_189_T & ~_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_189_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_190_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_190_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hBF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_190_T & ~_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_190_T & ~_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_190_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_191_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_191_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_191_T & ~_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_191_T & ~_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_191_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_192_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_192_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_192_T & ~_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_192_T & ~_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_192_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_193_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_193_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_193_T & ~_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_193_T & ~_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_193_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_194_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_194_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_194_T & ~_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_194_T & ~_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_194_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_195_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_195_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_195_T & ~_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_195_T & ~_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_195_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_196_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_196_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_196_T & ~_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_196_T & ~_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_196_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_197_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_197_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_197_T & ~_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_197_T & ~_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_197_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_198_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_198_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_198_T & ~_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_198_T & ~_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_198_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_199_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_199_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_199_T & ~_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_199_T & ~_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_199_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_200_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_200_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hC9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_200_T & ~_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_200_T & ~_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_200_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_201_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_201_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_201_T & ~_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_201_T & ~_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_201_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_202_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_202_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_202_T & ~_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_202_T & ~_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_202_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_203_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_203_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_203_T & ~_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_203_T & ~_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_203_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_204_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_204_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_204_T & ~_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_204_T & ~_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_204_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_205_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_205_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_205_T & ~_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_205_T & ~_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_205_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_206_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_206_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hCF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_206_T & ~_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_206_T & ~_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_206_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_207_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_207_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_207_T & ~_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_207_T & ~_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_207_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_208_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_208_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_208_T & ~_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_208_T & ~_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_208_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_209_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_209_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_209_T & ~_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_209_T & ~_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_209_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_210_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_210_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_210_T & ~_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_210_T & ~_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_210_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_211_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_211_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_211_T & ~_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_211_T & ~_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:222:7, :740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_211_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_212_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_212_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_212_T & ~_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_212_T & ~_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_212_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_213_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_213_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_213_T & ~_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_213_T & ~_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_213_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_214_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_214_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_214_T & ~_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_214_T & ~_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_214_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_215_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_215_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_215_T & ~_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_215_T & ~_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_215_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_216_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_216_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hD9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_216_T & ~_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_216_T & ~_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_216_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_217_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_217_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_217_T & ~_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_217_T & ~_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_217_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_218_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_218_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_218_T & ~_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_218_T & ~_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_218_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_219_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_219_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_219_T & ~_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_219_T & ~_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_219_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_220_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_220_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_220_T & ~_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_220_T & ~_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_220_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_221_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_221_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_221_T & ~_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_221_T & ~_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_221_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_222_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_222_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hDF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_222_T & ~_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_222_T & ~_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_222_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_223_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_223_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_223_T & ~_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_223_T & ~_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_223_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_224_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_224_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_224_T & ~_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_224_T & ~_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_224_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_225_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_225_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_225_T & ~_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_225_T & ~_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_225_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_226_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_226_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_226_T & ~_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_226_T & ~_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_226_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_227_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_227_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_227_T & ~_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_227_T & ~_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_227_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_228_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_228_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_228_T & ~_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_228_T & ~_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_228_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_229_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_229_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_229_T & ~_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_229_T & ~_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_229_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_230_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_230_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_230_T & ~_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_230_T & ~_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_230_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_231_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_231_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_231_T & ~_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_231_T & ~_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_231_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_232_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_232_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hE9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_232_T & ~_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_232_T & ~_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_232_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_233_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_233_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hEA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_233_T & ~_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_233_T & ~_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_233_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_234_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_234_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hEB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_234_T & ~_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_234_T & ~_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_234_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_235_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_235_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hEC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_235_T & ~_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_235_T & ~_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_235_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_236_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_236_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hED - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_236_T & ~_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_236_T & ~_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_236_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_237_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_237_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hEE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_237_T & ~_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_237_T & ~_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_237_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_238_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_238_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hEF - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_238_T & ~_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_238_T & ~_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_238_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_239_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_239_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF0 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_239_T & ~_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_239_T & ~_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_239_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_240_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_240_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF1 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_240_T & ~_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_240_T & ~_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_240_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_241_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_241_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF2 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_241_T & ~_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_241_T & ~_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_241_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_242_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_242_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF3 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_242_T & ~_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_242_T & ~_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_242_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_243_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_243_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF4 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_243_T & ~_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_243_T & ~_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_243_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_244_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_244_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF5 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_244_T & ~_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_244_T & ~_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_244_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_245_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_245_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF6 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_245_T & ~_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_245_T & ~_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_245_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_246_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_246_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF7 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_246_T & ~_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_246_T & ~_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_246_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_247_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_247_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF8 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_247_T & ~_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_247_T & ~_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_247_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_248_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_248_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hF9 - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_248_T & ~_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_248_T & ~_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_248_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_249_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_249_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hFA - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_249_T & ~_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_249_T & ~_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_249_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_250_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_250_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hFB - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_250_T & ~_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_250_T & ~_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_250_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_251_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_251_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hFC - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_251_T & ~_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_251_T & ~_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_251_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_252_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_252_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hFD - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_252_T & ~_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_252_T & ~_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_252_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_253_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_253_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | s2_ghist_ptr_dup_0_value == 8'hFE - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_253_T & ~_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_253_T & ~_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 - | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_1 - & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_253_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_254_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_254_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src (s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | (&s2_ghist_ptr_dup_0_value) - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_254_T & ~_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_254_T & ~_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src (s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src (s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, :454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) - & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :766:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:193:15, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_254_ppm_out_res) ); - PriorityMuxModule_20 ghv_write_datas_255_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 - .s2_new_bit_0_sel (_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + PriorityMuxModule_20 ghv_write_datas_255_ppm ( // @[utility/src/main/scala/utility/PriorityMuxGen.scala:134:25] + .s2_new_bit_0_sel (_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s2_new_bit_0_src ((&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 - & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit | ~(|s2_ghist_ptr_dup_0_value) - & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 - & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 & _predictors_io_out_s2_full_pred_0_is_br_sharing - & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s2_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :325:35, :583:58, :587:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .s1_new_bit_0_sel - (_ghv_wens_255_T & ~_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + (_ghv_wens_255_T & ~_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:517:26, :620:26, :705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s1_new_bit_0_src ((&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit - | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit - | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) & (_predictors_io_out_s1_full_pred_0_slot_valids_0 & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 - & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 & _predictors_io_out_s1_full_pred_0_hit) - & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) - & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} - .s3_new_bit_0_sel (_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :324:35, :495:58, :499:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :482:12, :488:9, :489:{34,37}, :494:{74,90}] + .s3_new_bit_0_sel (_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // @[src/main/scala/xiangshan/frontend/BPU.scala:705:26, :858:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}] .s3_new_bit_0_src ((&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 - & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit - | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 - & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing - & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + & _predictors_io_out_s3_full_pred_0_hit), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:226:26, :326:35, :664:58, :668:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:454:48, :459:69, :474:32, :475:27, :482:12] .redirect_new_bit_0_src - ((&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 - & real_br_taken_mask_dup_0_0 | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) - & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :760:50, :763:52 + ((&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:740:54, :750:65, :763:50, :766:52, utility/src/main/scala/utility/BitUtils.scala:33:27] .out_res (_ghv_write_datas_255_ppm_out_res) ); assign io_bpu_to_ftq_resp_valid = s1_valid_dup_3 | s2_valid_dup_3 & s2_redirect_dup_2 | s3_valid_dup_3 - & s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :419:{20,42}, :420:20, :605:28, :684:28 - assign io_bpu_to_ftq_resp_bits_s1_pc_3 = _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + & s3_redirect_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65, :420:{20,42}, :421:20, :606:28, :685:28] + assign io_bpu_to_ftq_resp_bits_s1_pc_3 = _predictors_io_out_s1_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0 = - _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1 = - _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0 = - _predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1 = - _predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0 = - _predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1 = - _predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0 = - _predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1 = - _predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr = - _predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing = - _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s1_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit = - _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 - assign io_bpu_to_ftq_resp_bits_s2_pc_3 = _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 - assign io_bpu_to_ftq_resp_bits_s2_valid_3 = s2_valid_dup_3 & ~s2_flush_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :358:26, :717:{32,35} - assign io_bpu_to_ftq_resp_bits_s2_hasRedirect_3 = s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :605:28 - assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag = s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29 - assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_value = s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29 + _predictors_io_out_s1_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] + assign io_bpu_to_ftq_resp_bits_s2_pc_3 = _predictors_io_out_s2_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] + assign io_bpu_to_ftq_resp_bits_s2_valid_3 = s2_valid_dup_3 & ~s2_flush_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65, :359:26, :718:{32,35}] + assign io_bpu_to_ftq_resp_bits_s2_hasRedirect_3 = s2_redirect_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :606:28] + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag = s2_ftq_idx_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29] + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_value = s2_ftq_idx_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :709:29] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0 = - _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1 = - _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0 = - _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1 = - _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0 = - _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1 = - _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0 = - _predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1 = - _predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr = - _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing = - _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit = - _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 - assign io_bpu_to_ftq_resp_bits_s3_pc_3 = _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] + assign io_bpu_to_ftq_resp_bits_s3_pc_3 = _predictors_io_out_s3_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_valid_3 = - s3_valid_dup_3 & ~io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :722:{32,35} - assign io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 = s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :684:28 - assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag = s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29 - assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_value = s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29 + s3_valid_dup_3 & ~io_ftq_to_bpu_redirect_valid; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :272:65, :723:{32,35}] + assign io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 = s3_redirect_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :685:28] + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag = s3_ftq_idx_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :710:29] + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_value = s3_ftq_idx_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :710:29] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0 = - _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1 = - _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0 = - _predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1 = - _predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0 = - _predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1 = - _predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr = - _predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr = - _predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing = - _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit = - _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + _predictors_io_out_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :226:26] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist = - s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_17_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist = - s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_16_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist = - s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_15_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist = - s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist = - s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist = - s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist = - s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_11_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist = - s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist = - s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_9_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist = - s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_8_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist = - s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_7_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist = - s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist = - s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_5_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist = - s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist = - s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist = - s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist = - s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_1_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist = - s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_0_folded_hist; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :289:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0 = - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1 = - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2 = - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3 = - s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :301:46] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH = - s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40 + s3_last_br_num_oh_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :295:40] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag = - s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_2_flag; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value = - s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_2_value; // @[src/main/scala/xiangshan/frontend/BPU.scala:222:7, :326:35] + assign io_perf_0_value = io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_1_value = io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_2_value = io_perf_2_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_3_value = io_perf_3_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_4_value = io_perf_4_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_5_value = io_perf_5_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] + assign io_perf_6_value = io_perf_6_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/BPU.scala:222:7] endmodule diff --git a/rtl/uFTB/FauFTB.sv b/rtl/uFTB/FauFTB.sv index 567d9c7..3edf23d 100644 --- a/rtl/uFTB/FauFTB.sv +++ b/rtl/uFTB/FauFTB.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,644 +55,647 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - input clock, - input reset, - input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [3:0] io_out_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [38:0] io_out_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output io_out_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - input io_update_bits_br_taken_mask_1 // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +module FauFTB( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + input clock, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + input reset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + input [35:0] io_reset_vector, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [3:0] io_out_s1_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [40:0] io_out_s1_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output io_out_s1_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_ctrl_ubtb_enable, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s1_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [3:0] io_update_bits_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input io_update_bits_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + output [5:0] io_perf_0_value, // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] + output [5:0] io_perf_1_value // @[src/main/scala/utils/PerfCounterUtils.scala:321:40] ); - reg [4:0] resp_meta_pred_way_r_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:34 - reg resp_meta_hit_r_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:29 - wire [3:0] _ways_31_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_31_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_31_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_31_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_31_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_31_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_31_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_31_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_30_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_30_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_30_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_30_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_30_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_30_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_30_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_30_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_29_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_29_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_29_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_29_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_29_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_29_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_29_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_29_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_28_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_28_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_28_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_28_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_28_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_28_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_28_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_28_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_27_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_27_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_27_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_27_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_27_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_27_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_27_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_27_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_26_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_26_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_26_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_26_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_26_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_26_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_26_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_26_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_25_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_25_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_25_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_25_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_25_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_25_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_25_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_25_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_24_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_24_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_24_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_24_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_24_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_24_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_24_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_24_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_23_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_23_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_23_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_23_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_23_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_23_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_23_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_23_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_22_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_22_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_22_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_22_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_22_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_22_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_22_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_22_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_21_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_21_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_21_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_21_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_21_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_21_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_21_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_21_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_20_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_20_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_20_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_20_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_20_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_20_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_20_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_20_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_19_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_19_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_19_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_19_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_19_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_19_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_19_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_19_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_18_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_18_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_18_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_18_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_18_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_18_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_18_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_18_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_17_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_17_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_17_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_17_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_17_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_17_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_17_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_17_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_16_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_16_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_16_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_16_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_16_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_16_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_16_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_16_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_15_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_15_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_15_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_15_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_15_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_15_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_15_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_15_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_14_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_14_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_14_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_14_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_14_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_14_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_14_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_14_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_13_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_13_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_13_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_13_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_13_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_13_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_13_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_13_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_12_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_12_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_12_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_12_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_12_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_12_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_12_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_12_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_11_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_11_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_11_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_11_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_11_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_11_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_11_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_11_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_10_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_10_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_10_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_10_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_10_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_10_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_10_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_10_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_9_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_9_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_9_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_9_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_9_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_9_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_9_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_9_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_8_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_8_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_8_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_8_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_8_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_8_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_8_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_8_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_7_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_7_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_7_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_7_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_7_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_7_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_7_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_7_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_6_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_6_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_6_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_6_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_6_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_6_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_6_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_6_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_5_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_5_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_5_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_5_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_5_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_5_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_5_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_5_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_4_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_4_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_4_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_4_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_4_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_4_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_4_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_4_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_3_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_3_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_3_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_3_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_3_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_3_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_3_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_3_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_2_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_2_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_2_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_2_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_2_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_2_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_2_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_2_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_1_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_1_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_1_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_1_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_1_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_1_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_1_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_1_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_0_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [11:0] _ways_0_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_0_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_0_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [19:0] _ways_0_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [1:0] _ways_0_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _ways_0_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _ways_0_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 - reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - reg [1:0] ctrs_0_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_0_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_1_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_1_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_2_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_2_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_3_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_3_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_4_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_4_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_5_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_5_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_6_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_6_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_7_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_7_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_8_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_8_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_9_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_9_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_10_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_10_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_11_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_11_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_12_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_12_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_13_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_13_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_14_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_14_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_15_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_15_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_16_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_16_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_17_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_17_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_18_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_18_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_19_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_19_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_20_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_20_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_21_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_21_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_22_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_22_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_23_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_23_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_24_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_24_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_25_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_25_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_26_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_26_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_27_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_27_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_28_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_28_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_29_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_29_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_30_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_30_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_31_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [1:0] ctrs_31_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - reg [30:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + reg [4:0] resp_meta_pred_way_r_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:123:34] + reg resp_meta_hit_r_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:122:29] + wire [3:0] _ways_31_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_31_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_31_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_31_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_31_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_31_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_31_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_31_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_30_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_30_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_30_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_30_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_30_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_30_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_30_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_30_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_29_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_29_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_29_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_29_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_29_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_29_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_29_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_29_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_28_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_28_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_28_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_28_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_28_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_28_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_28_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_28_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_27_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_27_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_27_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_27_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_27_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_27_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_27_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_27_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_26_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_26_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_26_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_26_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_26_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_26_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_26_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_26_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_25_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_25_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_25_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_25_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_25_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_25_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_25_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_25_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_24_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_24_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_24_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_24_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_24_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_24_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_24_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_24_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_23_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_23_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_23_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_23_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_23_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_23_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_23_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_23_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_22_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_22_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_22_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_22_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_22_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_22_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_22_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_22_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_21_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_21_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_21_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_21_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_21_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_21_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_21_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_21_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_20_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_20_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_20_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_20_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_20_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_20_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_20_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_20_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_19_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_19_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_19_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_19_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_19_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_19_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_19_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_19_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_18_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_18_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_18_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_18_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_18_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_18_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_18_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_18_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_17_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_17_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_17_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_17_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_17_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_17_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_17_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_17_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_16_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_16_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_16_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_16_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_16_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_16_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_16_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_16_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_15_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_15_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_15_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_15_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_15_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_15_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_15_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_15_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_14_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_14_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_14_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_14_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_14_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_14_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_14_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_14_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_13_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_13_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_13_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_13_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_13_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_13_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_13_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_13_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_12_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_12_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_12_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_12_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_12_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_12_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_12_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_12_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_11_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_11_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_11_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_11_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_11_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_11_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_11_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_11_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_10_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_10_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_10_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_10_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_10_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_10_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_10_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_10_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_9_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_9_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_9_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_9_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_9_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_9_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_9_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_9_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_8_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_8_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_8_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_8_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_8_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_8_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_8_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_8_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_7_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_7_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_7_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_7_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_7_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_7_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_7_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_7_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_6_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_6_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_6_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_6_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_6_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_6_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_6_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_6_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_5_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_5_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_5_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_5_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_5_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_5_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_5_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_5_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_4_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_4_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_4_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_4_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_4_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_4_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_4_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_4_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_3_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_3_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_3_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_3_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_3_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_3_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_3_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_3_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_2_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_2_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_2_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_2_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_2_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_2_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_2_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_2_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_1_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_1_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_1_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_1_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_1_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_1_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_1_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_1_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_0_io_resp_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [11:0] _ways_0_io_resp_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_0_io_resp_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_0_io_resp_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [19:0] _ways_0_io_resp_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [1:0] _ways_0_io_resp_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _ways_0_io_resp_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_resp_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _ways_0_io_update_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [35:0] _reset_vector_delay_io_out; // @[utility/src/main/scala/utility/Hold.scala:100:23] + reg [40:0] s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg [40:0] s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + reg REG; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + reg REG_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + reg [1:0] ctrs_0_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_0_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_1_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_1_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_2_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_2_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_3_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_3_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_4_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_4_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_5_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_5_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_6_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_6_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_7_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_7_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_8_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_8_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_9_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_9_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_10_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_10_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_11_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_11_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_12_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_12_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_13_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_13_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_14_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_14_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_15_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_15_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_16_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_16_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_17_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_17_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_18_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_18_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_19_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_19_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_20_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_20_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_21_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_21_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_22_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_22_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_23_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_23_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_24_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_24_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_25_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_25_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_26_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_26_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_27_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_27_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_28_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_28_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_29_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_29_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_30_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_30_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_31_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [1:0] ctrs_31_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + reg [30:0] state_reg; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] wire [31:0] s1_hit_oh = {_ways_31_io_resp_hit, _ways_30_io_resp_hit, @@ -725,169 +728,169 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 _ways_3_io_resp_hit, _ways_2_io_resp_hit, _ways_1_io_resp_hit, - _ways_0_io_resp_hit}; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :101:52 - wire _target_T_18 = _ways_0_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_19 = _ways_0_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_20 = _ways_0_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + _ways_0_io_resp_hit}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :101:52] + wire _target_T_18 = _ways_0_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_19 = _ways_0_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_20 = _ways_0_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_0_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_0_io_resp_carry, _ways_0_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire [38:0] _s1_possible_full_preds_31_fallThroughAddr_T = 39'(s1_pc_dup_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:47 - wire _target_T_45 = _ways_1_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_46 = _ways_1_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_47 = _ways_1_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_0_io_resp_carry, _ways_0_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire [40:0] _s1_possible_full_preds_31_fallThroughAddr_T = 41'(s1_pc_dup_0 + 41'h20); // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FrontendBundle.scala:551:47] + wire _target_T_45 = _ways_1_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_46 = _ways_1_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_47 = _ways_1_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_1_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_1_io_resp_carry, _ways_1_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_72 = _ways_2_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_73 = _ways_2_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_74 = _ways_2_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_1_io_resp_carry, _ways_1_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_72 = _ways_2_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_73 = _ways_2_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_74 = _ways_2_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_2_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_2_io_resp_carry, _ways_2_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_99 = _ways_3_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_100 = _ways_3_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_101 = _ways_3_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_2_io_resp_carry, _ways_2_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_99 = _ways_3_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_100 = _ways_3_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_101 = _ways_3_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_3_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_3_io_resp_carry, _ways_3_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_126 = _ways_4_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_127 = _ways_4_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_128 = _ways_4_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_3_io_resp_carry, _ways_3_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_126 = _ways_4_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_127 = _ways_4_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_128 = _ways_4_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_4_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_4_io_resp_carry, _ways_4_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_153 = _ways_5_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_154 = _ways_5_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_155 = _ways_5_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_4_io_resp_carry, _ways_4_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_153 = _ways_5_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_154 = _ways_5_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_155 = _ways_5_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_5_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_5_io_resp_carry, _ways_5_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_180 = _ways_6_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_181 = _ways_6_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_182 = _ways_6_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_5_io_resp_carry, _ways_5_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_180 = _ways_6_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_181 = _ways_6_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_182 = _ways_6_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_6_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_6_io_resp_carry, _ways_6_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_207 = _ways_7_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_208 = _ways_7_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_209 = _ways_7_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_6_io_resp_carry, _ways_6_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_207 = _ways_7_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_208 = _ways_7_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_209 = _ways_7_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_7_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_7_io_resp_carry, _ways_7_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_234 = _ways_8_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_235 = _ways_8_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_236 = _ways_8_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_7_io_resp_carry, _ways_7_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_234 = _ways_8_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_235 = _ways_8_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_236 = _ways_8_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_8_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_8_io_resp_carry, _ways_8_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_261 = _ways_9_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_262 = _ways_9_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_263 = _ways_9_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_8_io_resp_carry, _ways_8_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_261 = _ways_9_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_262 = _ways_9_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_263 = _ways_9_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_9_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_9_io_resp_carry, _ways_9_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_288 = _ways_10_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_289 = _ways_10_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_290 = _ways_10_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_9_io_resp_carry, _ways_9_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_288 = _ways_10_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_289 = _ways_10_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_290 = _ways_10_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_10_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_10_io_resp_carry, _ways_10_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_315 = _ways_11_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_316 = _ways_11_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_317 = _ways_11_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_10_io_resp_carry, _ways_10_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_315 = _ways_11_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_316 = _ways_11_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_317 = _ways_11_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_11_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_11_io_resp_carry, _ways_11_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_342 = _ways_12_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_343 = _ways_12_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_344 = _ways_12_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_11_io_resp_carry, _ways_11_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_342 = _ways_12_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_343 = _ways_12_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_344 = _ways_12_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_12_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_12_io_resp_carry, _ways_12_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_369 = _ways_13_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_370 = _ways_13_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_371 = _ways_13_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_12_io_resp_carry, _ways_12_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_369 = _ways_13_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_370 = _ways_13_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_371 = _ways_13_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_13_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_13_io_resp_carry, _ways_13_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_396 = _ways_14_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_397 = _ways_14_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_398 = _ways_14_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_13_io_resp_carry, _ways_13_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_396 = _ways_14_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_397 = _ways_14_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_398 = _ways_14_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_14_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_14_io_resp_carry, _ways_14_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_423 = _ways_15_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_424 = _ways_15_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_425 = _ways_15_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_14_io_resp_carry, _ways_14_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_423 = _ways_15_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_424 = _ways_15_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_425 = _ways_15_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_15_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_15_io_resp_carry, _ways_15_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_450 = _ways_16_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_451 = _ways_16_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_452 = _ways_16_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_15_io_resp_carry, _ways_15_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_450 = _ways_16_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_451 = _ways_16_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_452 = _ways_16_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_16_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_16_io_resp_carry, _ways_16_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_477 = _ways_17_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_478 = _ways_17_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_479 = _ways_17_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_16_io_resp_carry, _ways_16_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_477 = _ways_17_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_478 = _ways_17_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_479 = _ways_17_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_17_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_17_io_resp_carry, _ways_17_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_504 = _ways_18_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_505 = _ways_18_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_506 = _ways_18_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_17_io_resp_carry, _ways_17_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_504 = _ways_18_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_505 = _ways_18_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_506 = _ways_18_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_18_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_18_io_resp_carry, _ways_18_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_531 = _ways_19_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_532 = _ways_19_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_533 = _ways_19_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_18_io_resp_carry, _ways_18_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_531 = _ways_19_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_532 = _ways_19_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_533 = _ways_19_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_19_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_19_io_resp_carry, _ways_19_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_558 = _ways_20_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_559 = _ways_20_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_560 = _ways_20_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_19_io_resp_carry, _ways_19_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_558 = _ways_20_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_559 = _ways_20_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_560 = _ways_20_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_20_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_20_io_resp_carry, _ways_20_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_585 = _ways_21_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_586 = _ways_21_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_587 = _ways_21_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_20_io_resp_carry, _ways_20_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_585 = _ways_21_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_586 = _ways_21_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_587 = _ways_21_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_21_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_21_io_resp_carry, _ways_21_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_612 = _ways_22_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_613 = _ways_22_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_614 = _ways_22_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_21_io_resp_carry, _ways_21_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_612 = _ways_22_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_613 = _ways_22_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_614 = _ways_22_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_22_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_22_io_resp_carry, _ways_22_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_639 = _ways_23_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_640 = _ways_23_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_641 = _ways_23_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_22_io_resp_carry, _ways_22_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_639 = _ways_23_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_640 = _ways_23_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_641 = _ways_23_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_23_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_23_io_resp_carry, _ways_23_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_666 = _ways_24_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_667 = _ways_24_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_668 = _ways_24_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_23_io_resp_carry, _ways_23_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_666 = _ways_24_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_667 = _ways_24_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_668 = _ways_24_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_24_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_24_io_resp_carry, _ways_24_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_693 = _ways_25_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_694 = _ways_25_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_695 = _ways_25_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_24_io_resp_carry, _ways_24_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_693 = _ways_25_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_694 = _ways_25_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_695 = _ways_25_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_25_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_25_io_resp_carry, _ways_25_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_720 = _ways_26_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_721 = _ways_26_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_722 = _ways_26_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_25_io_resp_carry, _ways_25_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_720 = _ways_26_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_721 = _ways_26_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_722 = _ways_26_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_26_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_26_io_resp_carry, _ways_26_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_747 = _ways_27_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_748 = _ways_27_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_749 = _ways_27_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_26_io_resp_carry, _ways_26_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_747 = _ways_27_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_748 = _ways_27_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_749 = _ways_27_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_27_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_27_io_resp_carry, _ways_27_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_774 = _ways_28_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_775 = _ways_28_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_776 = _ways_28_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_27_io_resp_carry, _ways_27_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_774 = _ways_28_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_775 = _ways_28_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_776 = _ways_28_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_28_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_28_io_resp_carry, _ways_28_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_801 = _ways_29_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_802 = _ways_29_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_803 = _ways_29_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_28_io_resp_carry, _ways_28_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_801 = _ways_29_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_802 = _ways_29_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_803 = _ways_29_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_29_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_29_io_resp_carry, _ways_29_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_828 = _ways_30_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_829 = _ways_30_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_830 = _ways_30_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_29_io_resp_carry, _ways_29_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_828 = _ways_30_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_829 = _ways_30_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_830 = _ways_30_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_30_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_30_io_resp_carry, _ways_30_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _target_T_855 = _ways_31_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _target_T_856 = _ways_31_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire _target_T_857 = _ways_31_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_30_io_resp_carry, _ways_30_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _target_T_855 = _ways_31_io_resp_tailSlot_tarStat == 2'h1; // @[src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _target_T_856 = _ways_31_io_resp_tailSlot_tarStat == 2'h2; // @[src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire _target_T_857 = _ways_31_io_resp_tailSlot_tarStat == 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] wire s1_possible_full_preds_31_fallThroughErr = - {1'h0, s1_pc_dup_0[4:1]} >= {_ways_31_io_resp_carry, _ways_31_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 - wire _s1_hit_full_pred_WIRE_1 = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_31_io_resp_carry, _ways_31_io_resp_pftAddr}; // @[src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:548:{32,48}, :549:32, :550:34] + wire _s1_hit_full_pred_T_157 = _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid & _ways_0_io_resp_tailSlot_sharing | _ways_1_io_resp_hit & _ways_1_io_resp_tailSlot_valid & _ways_1_io_resp_tailSlot_sharing @@ -935,295 +938,295 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 & _ways_29_io_resp_tailSlot_valid & _ways_29_io_resp_tailSlot_sharing | _ways_30_io_resp_hit & _ways_30_io_resp_tailSlot_valid & _ways_30_io_resp_tailSlot_sharing | _ways_31_io_resp_hit - & _ways_31_io_resp_tailSlot_valid & _ways_31_io_resp_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [38:0] _s1_hit_full_pred_WIRE_8 = + & _ways_31_io_resp_tailSlot_valid & _ways_31_io_resp_tailSlot_sharing; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [40:0] _s1_hit_full_pred_T_598 = (_ways_0_io_resp_hit ? (s1_possible_full_preds_0_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T - : {_ways_0_io_resp_carry ? 34'(s1_pc_dup_0[38:5] + 34'h1) : s1_pc_dup_0[38:5], + : {_ways_0_io_resp_carry ? 36'(s1_pc_dup_0[40:5] + 36'h1) : s1_pc_dup_0[40:5], _ways_0_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_1_io_resp_hit ? (s1_possible_full_preds_1_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_1_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_1_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_2_io_resp_hit ? (s1_possible_full_preds_2_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_2_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_2_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_3_io_resp_hit ? (s1_possible_full_preds_3_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_3_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_3_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_4_io_resp_hit ? (s1_possible_full_preds_4_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_4_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_4_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_5_io_resp_hit ? (s1_possible_full_preds_5_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_5_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_5_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_6_io_resp_hit ? (s1_possible_full_preds_6_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_6_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_6_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_7_io_resp_hit ? (s1_possible_full_preds_7_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_7_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_7_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_8_io_resp_hit ? (s1_possible_full_preds_8_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_8_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_8_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_9_io_resp_hit ? (s1_possible_full_preds_9_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_9_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_9_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_10_io_resp_hit ? (s1_possible_full_preds_10_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_10_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_10_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_11_io_resp_hit ? (s1_possible_full_preds_11_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_11_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_11_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_12_io_resp_hit ? (s1_possible_full_preds_12_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_12_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_12_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_13_io_resp_hit ? (s1_possible_full_preds_13_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_13_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_13_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_14_io_resp_hit ? (s1_possible_full_preds_14_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_14_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_14_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_15_io_resp_hit ? (s1_possible_full_preds_15_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_15_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_15_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_16_io_resp_hit ? (s1_possible_full_preds_16_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_16_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_16_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_17_io_resp_hit ? (s1_possible_full_preds_17_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_17_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_17_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_18_io_resp_hit ? (s1_possible_full_preds_18_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_18_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_18_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_19_io_resp_hit ? (s1_possible_full_preds_19_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_19_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_19_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_20_io_resp_hit ? (s1_possible_full_preds_20_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_20_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_20_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_21_io_resp_hit ? (s1_possible_full_preds_21_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_21_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_21_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_22_io_resp_hit ? (s1_possible_full_preds_22_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_22_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_22_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_23_io_resp_hit ? (s1_possible_full_preds_23_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_23_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_23_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_24_io_resp_hit ? (s1_possible_full_preds_24_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_24_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_24_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_25_io_resp_hit ? (s1_possible_full_preds_25_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_25_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_25_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_26_io_resp_hit ? (s1_possible_full_preds_26_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_26_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_26_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_27_io_resp_hit ? (s1_possible_full_preds_27_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_27_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_27_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_28_io_resp_hit ? (s1_possible_full_preds_28_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_28_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_28_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_29_io_resp_hit ? (s1_possible_full_preds_29_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_29_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_29_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_30_io_resp_hit ? (s1_possible_full_preds_30_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_30_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_30_io_resp_pftAddr, 1'h0}) - : 39'h0) + : 41'h0) | (_ways_31_io_resp_hit ? (s1_possible_full_preds_31_fallThroughErr ? _s1_possible_full_preds_31_fallThroughAddr_T : {_ways_31_io_resp_carry - ? 34'(s1_pc_dup_0[38:5] + 34'h1) - : s1_pc_dup_0[38:5], + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], _ways_31_io_resp_pftAddr, 1'h0}) - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} - wire [3:0] _s1_hit_full_pred_WIRE_10 = + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:111:28, :112:{8,12,26}, :176:26, :187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34, :551:{27,47}] + wire [3:0] _s1_hit_full_pred_T_661 = (_ways_0_io_resp_hit ? _ways_0_io_resp_brSlots_0_offset : 4'h0) | (_ways_1_io_resp_hit ? _ways_1_io_resp_brSlots_0_offset : 4'h0) | (_ways_2_io_resp_hit ? _ways_2_io_resp_brSlots_0_offset : 4'h0) @@ -1255,8 +1258,8 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 | (_ways_28_io_resp_hit ? _ways_28_io_resp_brSlots_0_offset : 4'h0) | (_ways_29_io_resp_hit ? _ways_29_io_resp_brSlots_0_offset : 4'h0) | (_ways_30_io_resp_hit ? _ways_30_io_resp_brSlots_0_offset : 4'h0) - | (_ways_31_io_resp_hit ? _ways_31_io_resp_brSlots_0_offset : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [3:0] _s1_hit_full_pred_WIRE_11 = + | (_ways_31_io_resp_hit ? _ways_31_io_resp_brSlots_0_offset : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [3:0] _s1_hit_full_pred_T_724 = (_ways_0_io_resp_hit ? _ways_0_io_resp_tailSlot_offset : 4'h0) | (_ways_1_io_resp_hit ? _ways_1_io_resp_tailSlot_offset : 4'h0) | (_ways_2_io_resp_hit ? _ways_2_io_resp_tailSlot_offset : 4'h0) @@ -1288,750 +1291,750 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 | (_ways_28_io_resp_hit ? _ways_28_io_resp_tailSlot_offset : 4'h0) | (_ways_29_io_resp_hit ? _ways_29_io_resp_tailSlot_offset : 4'h0) | (_ways_30_io_resp_hit ? _ways_30_io_resp_tailSlot_offset : 4'h0) - | (_ways_31_io_resp_hit ? _ways_31_io_resp_tailSlot_offset : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [38:0] _GEN = + | (_ways_31_io_resp_hit ? _ways_31_io_resp_tailSlot_offset : 4'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [40:0] _GEN = (_ways_0_io_resp_hit ? {(_ways_0_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_0_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_0_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_0_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_0_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_1_io_resp_hit ? {(_ways_1_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_1_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_1_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_1_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_1_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_2_io_resp_hit ? {(_ways_2_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_2_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_2_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_2_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_2_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_3_io_resp_hit ? {(_ways_3_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_3_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_3_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_3_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_3_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_4_io_resp_hit ? {(_ways_4_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_4_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_4_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_4_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_4_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_5_io_resp_hit ? {(_ways_5_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_5_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_5_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_5_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_5_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_6_io_resp_hit ? {(_ways_6_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_6_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_6_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_6_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_6_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_7_io_resp_hit ? {(_ways_7_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_7_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_7_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_7_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_7_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_8_io_resp_hit ? {(_ways_8_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_8_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_8_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_8_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_8_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_9_io_resp_hit ? {(_ways_9_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_9_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_9_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_9_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_9_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_10_io_resp_hit ? {(_ways_10_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_10_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_10_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_10_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_10_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_11_io_resp_hit ? {(_ways_11_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_11_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_11_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_11_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_11_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_12_io_resp_hit ? {(_ways_12_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_12_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_12_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_12_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_12_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_13_io_resp_hit ? {(_ways_13_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_13_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_13_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_13_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_13_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_14_io_resp_hit ? {(_ways_14_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_14_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_14_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_14_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_14_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_15_io_resp_hit ? {(_ways_15_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_15_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_15_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_15_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_15_io_resp_brSlots_0_lower, 1'h0} - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:97:10, :175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire [38:0] _GEN_0 = + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:10, :176:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire [40:0] _GEN_0 = (_ways_16_io_resp_hit ? {(_ways_16_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_16_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_16_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_16_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_16_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_17_io_resp_hit ? {(_ways_17_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_17_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_17_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_17_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_17_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_18_io_resp_hit ? {(_ways_18_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_18_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_18_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_18_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_18_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_19_io_resp_hit ? {(_ways_19_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_19_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_19_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_19_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_19_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_20_io_resp_hit ? {(_ways_20_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_20_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_20_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_20_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_20_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_21_io_resp_hit ? {(_ways_21_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_21_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_21_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_21_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_21_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_22_io_resp_hit ? {(_ways_22_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_22_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_22_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_22_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_22_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_23_io_resp_hit ? {(_ways_23_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_23_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_23_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_23_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_23_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_24_io_resp_hit ? {(_ways_24_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_24_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_24_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_24_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_24_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_25_io_resp_hit ? {(_ways_25_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_25_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_25_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_25_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_25_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_26_io_resp_hit ? {(_ways_26_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_26_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_26_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_26_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_26_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_27_io_resp_hit ? {(_ways_27_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_27_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_27_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_27_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_27_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_28_io_resp_hit ? {(_ways_28_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_28_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_28_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_28_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_28_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_29_io_resp_hit ? {(_ways_29_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_29_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_29_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_29_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_29_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_30_io_resp_hit ? {(_ways_30_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_30_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_30_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_30_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_30_io_resp_brSlots_0_lower, 1'h0} - : 39'h0) + : 41'h0) | (_ways_31_io_resp_hit ? {(_ways_31_io_resp_brSlots_0_tarStat == 2'h1 - ? 26'(s1_pc_dup_0[38:13] + 26'h1) - : 26'h0) + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) | (_ways_31_io_resp_brSlots_0_tarStat == 2'h2 - ? 26'(s1_pc_dup_0[38:13] - 26'h1) - : 26'h0) - | (_ways_31_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_31_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), _ways_31_io_resp_brSlots_0_lower, 1'h0} - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:97:10, :175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 - wire [38:0] _s1_hit_full_pred_WIRE_14 = _GEN | _GEN_0; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire [38:0] _GEN_1 = + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:10, :176:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73] + wire [40:0] _s1_hit_full_pred_T_850 = _GEN | _GEN_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire [40:0] _GEN_1 = (_ways_0_io_resp_hit ? {_ways_0_io_resp_tailSlot_sharing - ? {(_target_T_18 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_19 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_20 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_18 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_19 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_20 ? s1_pc_dup_0[40:13] : 28'h0), _ways_0_io_resp_tailSlot_lower[11:0]} - : {(_target_T_18 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_19 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_20 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_18 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_19 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_20 ? s1_pc_dup_0[40:21] : 20'h0), _ways_0_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_1_io_resp_hit ? {_ways_1_io_resp_tailSlot_sharing - ? {(_target_T_45 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_46 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_47 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_45 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_46 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_47 ? s1_pc_dup_0[40:13] : 28'h0), _ways_1_io_resp_tailSlot_lower[11:0]} - : {(_target_T_45 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_46 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_47 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_45 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_46 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_47 ? s1_pc_dup_0[40:21] : 20'h0), _ways_1_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_2_io_resp_hit ? {_ways_2_io_resp_tailSlot_sharing - ? {(_target_T_72 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_73 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_74 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_72 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_73 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_74 ? s1_pc_dup_0[40:13] : 28'h0), _ways_2_io_resp_tailSlot_lower[11:0]} - : {(_target_T_72 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_73 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_74 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_72 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_73 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_74 ? s1_pc_dup_0[40:21] : 20'h0), _ways_2_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_3_io_resp_hit ? {_ways_3_io_resp_tailSlot_sharing - ? {(_target_T_99 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_100 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_101 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_99 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_100 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_101 ? s1_pc_dup_0[40:13] : 28'h0), _ways_3_io_resp_tailSlot_lower[11:0]} - : {(_target_T_99 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_100 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_101 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_99 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_100 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_101 ? s1_pc_dup_0[40:21] : 20'h0), _ways_3_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_4_io_resp_hit ? {_ways_4_io_resp_tailSlot_sharing - ? {(_target_T_126 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_127 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_128 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_126 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_127 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_128 ? s1_pc_dup_0[40:13] : 28'h0), _ways_4_io_resp_tailSlot_lower[11:0]} - : {(_target_T_126 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_127 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_128 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_126 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_127 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_128 ? s1_pc_dup_0[40:21] : 20'h0), _ways_4_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_5_io_resp_hit ? {_ways_5_io_resp_tailSlot_sharing - ? {(_target_T_153 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_154 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_155 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_153 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_154 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_155 ? s1_pc_dup_0[40:13] : 28'h0), _ways_5_io_resp_tailSlot_lower[11:0]} - : {(_target_T_153 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_154 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_155 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_153 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_154 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_155 ? s1_pc_dup_0[40:21] : 20'h0), _ways_5_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_6_io_resp_hit ? {_ways_6_io_resp_tailSlot_sharing - ? {(_target_T_180 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_181 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_182 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_180 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_181 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_182 ? s1_pc_dup_0[40:13] : 28'h0), _ways_6_io_resp_tailSlot_lower[11:0]} - : {(_target_T_180 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_181 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_182 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_180 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_181 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_182 ? s1_pc_dup_0[40:21] : 20'h0), _ways_6_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_7_io_resp_hit ? {_ways_7_io_resp_tailSlot_sharing - ? {(_target_T_207 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_208 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_209 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_207 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_208 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_209 ? s1_pc_dup_0[40:13] : 28'h0), _ways_7_io_resp_tailSlot_lower[11:0]} - : {(_target_T_207 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_208 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_209 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_207 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_208 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_209 ? s1_pc_dup_0[40:21] : 20'h0), _ways_7_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_8_io_resp_hit ? {_ways_8_io_resp_tailSlot_sharing - ? {(_target_T_234 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_235 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_236 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_234 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_235 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_236 ? s1_pc_dup_0[40:13] : 28'h0), _ways_8_io_resp_tailSlot_lower[11:0]} - : {(_target_T_234 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_235 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_236 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_234 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_235 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_236 ? s1_pc_dup_0[40:21] : 20'h0), _ways_8_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_9_io_resp_hit ? {_ways_9_io_resp_tailSlot_sharing - ? {(_target_T_261 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_262 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_263 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_261 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_262 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_263 ? s1_pc_dup_0[40:13] : 28'h0), _ways_9_io_resp_tailSlot_lower[11:0]} - : {(_target_T_261 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_262 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_263 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_261 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_262 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_263 ? s1_pc_dup_0[40:21] : 20'h0), _ways_9_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_10_io_resp_hit ? {_ways_10_io_resp_tailSlot_sharing - ? {(_target_T_288 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_289 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_290 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_288 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_289 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_290 ? s1_pc_dup_0[40:13] : 28'h0), _ways_10_io_resp_tailSlot_lower[11:0]} - : {(_target_T_288 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_289 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_290 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_288 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_289 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_290 ? s1_pc_dup_0[40:21] : 20'h0), _ways_10_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_11_io_resp_hit ? {_ways_11_io_resp_tailSlot_sharing - ? {(_target_T_315 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_316 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_317 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_315 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_316 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_317 ? s1_pc_dup_0[40:13] : 28'h0), _ways_11_io_resp_tailSlot_lower[11:0]} - : {(_target_T_315 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_316 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_317 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_315 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_316 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_317 ? s1_pc_dup_0[40:21] : 20'h0), _ways_11_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_12_io_resp_hit ? {_ways_12_io_resp_tailSlot_sharing - ? {(_target_T_342 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_343 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_344 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_342 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_343 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_344 ? s1_pc_dup_0[40:13] : 28'h0), _ways_12_io_resp_tailSlot_lower[11:0]} - : {(_target_T_342 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_343 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_344 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_342 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_343 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_344 ? s1_pc_dup_0[40:21] : 20'h0), _ways_12_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_13_io_resp_hit ? {_ways_13_io_resp_tailSlot_sharing - ? {(_target_T_369 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_370 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_371 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_369 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_370 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_371 ? s1_pc_dup_0[40:13] : 28'h0), _ways_13_io_resp_tailSlot_lower[11:0]} - : {(_target_T_369 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_370 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_371 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_369 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_370 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_371 ? s1_pc_dup_0[40:21] : 20'h0), _ways_13_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_14_io_resp_hit ? {_ways_14_io_resp_tailSlot_sharing - ? {(_target_T_396 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_397 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_398 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_396 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_397 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_398 ? s1_pc_dup_0[40:13] : 28'h0), _ways_14_io_resp_tailSlot_lower[11:0]} - : {(_target_T_396 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_397 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_398 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_396 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_397 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_398 ? s1_pc_dup_0[40:21] : 20'h0), _ways_14_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_15_io_resp_hit ? {_ways_15_io_resp_tailSlot_sharing - ? {(_target_T_423 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_424 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_425 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_423 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_424 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_425 ? s1_pc_dup_0[40:13] : 28'h0), _ways_15_io_resp_tailSlot_lower[11:0]} - : {(_target_T_423 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_424 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_425 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_423 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_424 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_425 ? s1_pc_dup_0[40:21] : 20'h0), _ways_15_io_resp_tailSlot_lower}, 1'h0} - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [38:0] _GEN_2 = + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [40:0] _GEN_2 = (_ways_16_io_resp_hit ? {_ways_16_io_resp_tailSlot_sharing - ? {(_target_T_450 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_451 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_452 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_450 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_451 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_452 ? s1_pc_dup_0[40:13] : 28'h0), _ways_16_io_resp_tailSlot_lower[11:0]} - : {(_target_T_450 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_451 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_452 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_450 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_451 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_452 ? s1_pc_dup_0[40:21] : 20'h0), _ways_16_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_17_io_resp_hit ? {_ways_17_io_resp_tailSlot_sharing - ? {(_target_T_477 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_478 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_479 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_477 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_478 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_479 ? s1_pc_dup_0[40:13] : 28'h0), _ways_17_io_resp_tailSlot_lower[11:0]} - : {(_target_T_477 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_478 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_479 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_477 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_478 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_479 ? s1_pc_dup_0[40:21] : 20'h0), _ways_17_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_18_io_resp_hit ? {_ways_18_io_resp_tailSlot_sharing - ? {(_target_T_504 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_505 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_506 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_504 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_505 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_506 ? s1_pc_dup_0[40:13] : 28'h0), _ways_18_io_resp_tailSlot_lower[11:0]} - : {(_target_T_504 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_505 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_506 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_504 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_505 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_506 ? s1_pc_dup_0[40:21] : 20'h0), _ways_18_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_19_io_resp_hit ? {_ways_19_io_resp_tailSlot_sharing - ? {(_target_T_531 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_532 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_533 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_531 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_532 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_533 ? s1_pc_dup_0[40:13] : 28'h0), _ways_19_io_resp_tailSlot_lower[11:0]} - : {(_target_T_531 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_532 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_533 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_531 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_532 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_533 ? s1_pc_dup_0[40:21] : 20'h0), _ways_19_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_20_io_resp_hit ? {_ways_20_io_resp_tailSlot_sharing - ? {(_target_T_558 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_559 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_560 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_558 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_559 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_560 ? s1_pc_dup_0[40:13] : 28'h0), _ways_20_io_resp_tailSlot_lower[11:0]} - : {(_target_T_558 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_559 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_560 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_558 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_559 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_560 ? s1_pc_dup_0[40:21] : 20'h0), _ways_20_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_21_io_resp_hit ? {_ways_21_io_resp_tailSlot_sharing - ? {(_target_T_585 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_586 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_587 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_585 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_586 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_587 ? s1_pc_dup_0[40:13] : 28'h0), _ways_21_io_resp_tailSlot_lower[11:0]} - : {(_target_T_585 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_586 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_587 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_585 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_586 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_587 ? s1_pc_dup_0[40:21] : 20'h0), _ways_21_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_22_io_resp_hit ? {_ways_22_io_resp_tailSlot_sharing - ? {(_target_T_612 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_613 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_614 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_612 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_613 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_614 ? s1_pc_dup_0[40:13] : 28'h0), _ways_22_io_resp_tailSlot_lower[11:0]} - : {(_target_T_612 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_613 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_614 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_612 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_613 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_614 ? s1_pc_dup_0[40:21] : 20'h0), _ways_22_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_23_io_resp_hit ? {_ways_23_io_resp_tailSlot_sharing - ? {(_target_T_639 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_640 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_641 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_639 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_640 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_641 ? s1_pc_dup_0[40:13] : 28'h0), _ways_23_io_resp_tailSlot_lower[11:0]} - : {(_target_T_639 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_640 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_641 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_639 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_640 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_641 ? s1_pc_dup_0[40:21] : 20'h0), _ways_23_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_24_io_resp_hit ? {_ways_24_io_resp_tailSlot_sharing - ? {(_target_T_666 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_667 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_668 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_666 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_667 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_668 ? s1_pc_dup_0[40:13] : 28'h0), _ways_24_io_resp_tailSlot_lower[11:0]} - : {(_target_T_666 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_667 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_668 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_666 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_667 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_668 ? s1_pc_dup_0[40:21] : 20'h0), _ways_24_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_25_io_resp_hit ? {_ways_25_io_resp_tailSlot_sharing - ? {(_target_T_693 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_694 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_695 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_693 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_694 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_695 ? s1_pc_dup_0[40:13] : 28'h0), _ways_25_io_resp_tailSlot_lower[11:0]} - : {(_target_T_693 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_694 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_695 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_693 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_694 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_695 ? s1_pc_dup_0[40:21] : 20'h0), _ways_25_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_26_io_resp_hit ? {_ways_26_io_resp_tailSlot_sharing - ? {(_target_T_720 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_721 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_722 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_720 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_721 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_722 ? s1_pc_dup_0[40:13] : 28'h0), _ways_26_io_resp_tailSlot_lower[11:0]} - : {(_target_T_720 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_721 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_722 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_720 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_721 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_722 ? s1_pc_dup_0[40:21] : 20'h0), _ways_26_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_27_io_resp_hit ? {_ways_27_io_resp_tailSlot_sharing - ? {(_target_T_747 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_748 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_749 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_747 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_748 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_749 ? s1_pc_dup_0[40:13] : 28'h0), _ways_27_io_resp_tailSlot_lower[11:0]} - : {(_target_T_747 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_748 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_749 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_747 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_748 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_749 ? s1_pc_dup_0[40:21] : 20'h0), _ways_27_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_28_io_resp_hit ? {_ways_28_io_resp_tailSlot_sharing - ? {(_target_T_774 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_775 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_776 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_774 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_775 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_776 ? s1_pc_dup_0[40:13] : 28'h0), _ways_28_io_resp_tailSlot_lower[11:0]} - : {(_target_T_774 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_775 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_776 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_774 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_775 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_776 ? s1_pc_dup_0[40:21] : 20'h0), _ways_28_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_29_io_resp_hit ? {_ways_29_io_resp_tailSlot_sharing - ? {(_target_T_801 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_802 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_803 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_801 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_802 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_803 ? s1_pc_dup_0[40:13] : 28'h0), _ways_29_io_resp_tailSlot_lower[11:0]} - : {(_target_T_801 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_802 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_803 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_801 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_802 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_803 ? s1_pc_dup_0[40:21] : 20'h0), _ways_29_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_30_io_resp_hit ? {_ways_30_io_resp_tailSlot_sharing - ? {(_target_T_828 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_829 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_830 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_828 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_829 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_830 ? s1_pc_dup_0[40:13] : 28'h0), _ways_30_io_resp_tailSlot_lower[11:0]} - : {(_target_T_828 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_829 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_830 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_828 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_829 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_830 ? s1_pc_dup_0[40:21] : 20'h0), _ways_30_io_resp_tailSlot_lower}, 1'h0} - : 39'h0) + : 41'h0) | (_ways_31_io_resp_hit ? {_ways_31_io_resp_tailSlot_sharing - ? {(_target_T_855 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) - | (_target_T_856 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) - | (_target_T_857 ? s1_pc_dup_0[38:13] : 26'h0), + ? {(_target_T_855 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_856 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_857 ? s1_pc_dup_0[40:13] : 28'h0), _ways_31_io_resp_tailSlot_lower[11:0]} - : {(_target_T_855 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) - | (_target_T_856 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) - | (_target_T_857 ? s1_pc_dup_0[38:21] : 18'h0), + : {(_target_T_855 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_856 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_857 ? s1_pc_dup_0[40:21] : 20'h0), _ways_31_io_resp_tailSlot_lower}, 1'h0} - : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [38:0] _s1_hit_full_pred_WIRE_15 = _GEN_1 | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73 - wire _s1_hit_full_pred_WIRE_17 = + : 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:176:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [40:0] _s1_hit_full_pred_T_913 = _GEN_1 | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala:30:73] + wire _s1_hit_full_pred_T_976 = _ways_0_io_resp_hit & _ways_0_io_resp_brSlots_0_valid | _ways_1_io_resp_hit & _ways_1_io_resp_brSlots_0_valid | _ways_2_io_resp_hit & _ways_2_io_resp_brSlots_0_valid | _ways_3_io_resp_hit @@ -2063,8 +2066,8 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 & _ways_28_io_resp_brSlots_0_valid | _ways_29_io_resp_hit & _ways_29_io_resp_brSlots_0_valid | _ways_30_io_resp_hit & _ways_30_io_resp_brSlots_0_valid | _ways_31_io_resp_hit - & _ways_31_io_resp_brSlots_0_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _s1_hit_full_pred_WIRE_18 = + & _ways_31_io_resp_brSlots_0_valid; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _s1_hit_full_pred_T_1039 = _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid | _ways_1_io_resp_hit & _ways_1_io_resp_tailSlot_valid | _ways_2_io_resp_hit & _ways_2_io_resp_tailSlot_valid | _ways_3_io_resp_hit @@ -2096,8 +2099,8 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 & _ways_28_io_resp_tailSlot_valid | _ways_29_io_resp_hit & _ways_29_io_resp_tailSlot_valid | _ways_30_io_resp_hit & _ways_30_io_resp_tailSlot_valid | _ways_31_io_resp_hit - & _ways_31_io_resp_tailSlot_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire _s1_hit_full_pred_WIRE_20 = + & _ways_31_io_resp_tailSlot_valid; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire _s1_hit_full_pred_T_1102 = _ways_0_io_resp_hit & (ctrs_0_0[1] | _ways_0_io_resp_always_taken_0) | _ways_1_io_resp_hit & (ctrs_1_0[1] | _ways_1_io_resp_always_taken_0) | _ways_2_io_resp_hit & (ctrs_2_0[1] | _ways_2_io_resp_always_taken_0) @@ -2129,8 +2132,8 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 | _ways_28_io_resp_hit & (ctrs_28_0[1] | _ways_28_io_resp_always_taken_0) | _ways_29_io_resp_hit & (ctrs_29_0[1] | _ways_29_io_resp_always_taken_0) | _ways_30_io_resp_hit & (ctrs_30_0[1] | _ways_30_io_resp_always_taken_0) - | _ways_31_io_resp_hit & (ctrs_31_0[1] | _ways_31_io_resp_always_taken_0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38} - wire _s1_hit_full_pred_WIRE_21 = + | _ways_31_io_resp_hit & (ctrs_31_0[1] | _ways_31_io_resp_always_taken_0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38}] + wire _s1_hit_full_pred_T_1165 = _ways_0_io_resp_hit & (ctrs_0_1[1] | _ways_0_io_resp_always_taken_1) | _ways_1_io_resp_hit & (ctrs_1_1[1] | _ways_1_io_resp_always_taken_1) | _ways_2_io_resp_hit & (ctrs_2_1[1] | _ways_2_io_resp_always_taken_1) @@ -2162,17 +2165,17 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 | _ways_28_io_resp_hit & (ctrs_28_1[1] | _ways_28_io_resp_always_taken_1) | _ways_29_io_resp_hit & (ctrs_29_1[1] | _ways_29_io_resp_always_taken_1) | _ways_30_io_resp_hit & (ctrs_30_1[1] | _ways_30_io_resp_always_taken_1) - | _ways_31_io_resp_hit & (ctrs_31_1[1] | _ways_31_io_resp_always_taken_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38} - reg fauftb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:116:30 - wire _io_out_s1_full_pred_3_hit_T = (|s1_hit_oh) & fauftb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :116:30, :118:44 - reg resp_meta_hit_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:39 - reg [4:0] resp_meta_pred_way_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:44 - reg replacer_touch_ways_0_valid_REG; // src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 - reg [4:0] replacer_touch_ways_0_bits_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 - reg u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 - reg [15:0] u_s1_tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 - reg [31:0] u_s1_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:149:33 - reg u_s1_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:150:33 + | _ways_31_io_resp_hit & (ctrs_31_1[1] | _ways_31_io_resp_always_taken_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38}] + reg fauftb_enable; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:116:30] + wire io_out_s1_full_pred_3_hit_0 = (|s1_hit_oh) & fauftb_enable; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :116:30, :118:44] + reg resp_meta_hit_r; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:122:39] + reg [4:0] resp_meta_pred_way_r; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:123:44] + reg replacer_touch_ways_0_valid_REG; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:127:42] + reg [4:0] replacer_touch_ways_0_bits_r; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:128:44] + reg u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27] + reg [15:0] u_s1_tag; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] + reg [31:0] u_s1_hit_oh; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:149:33] + reg u_s1_hit; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:150:33] wire [31:0] u_s1_write_way_oh = u_s1_hit ? u_s1_hit_oh @@ -2199,57 +2202,61 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 : {state_reg[6], state_reg[6] ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} - : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FauFTB.scala:149:33, :150:33, :152:30 - reg [3:0] u_s1_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [11:0] u_s1_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [1:0] u_s1_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [3:0] u_s1_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [19:0] u_s1_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [1:0] u_s1_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg [3:0] u_s1_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - reg u_s1_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - wire u_s1_ways_write_valid_0 = u_s1_write_way_oh[0] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_1 = u_s1_write_way_oh[1] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_2 = u_s1_write_way_oh[2] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_3 = u_s1_write_way_oh[3] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_4 = u_s1_write_way_oh[4] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_5 = u_s1_write_way_oh[5] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_6 = u_s1_write_way_oh[6] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_7 = u_s1_write_way_oh[7] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_8 = u_s1_write_way_oh[8] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_9 = u_s1_write_way_oh[9] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_10 = u_s1_write_way_oh[10] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_11 = u_s1_write_way_oh[11] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_12 = u_s1_write_way_oh[12] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_13 = u_s1_write_way_oh[13] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_14 = u_s1_write_way_oh[14] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_15 = u_s1_write_way_oh[15] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_16 = u_s1_write_way_oh[16] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_17 = u_s1_write_way_oh[17] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_18 = u_s1_write_way_oh[18] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_19 = u_s1_write_way_oh[19] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_20 = u_s1_write_way_oh[20] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_21 = u_s1_write_way_oh[21] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_22 = u_s1_write_way_oh[22] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_23 = u_s1_write_way_oh[23] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_24 = u_s1_write_way_oh[24] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_25 = u_s1_write_way_oh[25] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_26 = u_s1_write_way_oh[26] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_27 = u_s1_write_way_oh[27] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_28 = u_s1_write_way_oh[28] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_29 = u_s1_write_way_oh[29] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_30 = u_s1_write_way_oh[30] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - wire u_s1_ways_write_valid_31 = u_s1_write_way_oh[31] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} - reg u_s1_br_update_valids_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:162:40 - reg u_s1_br_update_valids_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:162:40 - reg u_s1_br_takens_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - reg u_s1_br_takens_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - wire [38:0] _GEN_3 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FauFTB.scala:149:33, :150:33, :152:30] + reg [3:0] u_s1_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [11:0] u_s1_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [1:0] u_s1_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [3:0] u_s1_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [19:0] u_s1_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [1:0] u_s1_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg [3:0] u_s1_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + reg u_s1_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + wire u_s1_ways_write_valid_0 = u_s1_write_way_oh[0] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_1 = u_s1_write_way_oh[1] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_2 = u_s1_write_way_oh[2] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_3 = u_s1_write_way_oh[3] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_4 = u_s1_write_way_oh[4] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_5 = u_s1_write_way_oh[5] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_6 = u_s1_write_way_oh[6] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_7 = u_s1_write_way_oh[7] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_8 = u_s1_write_way_oh[8] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_9 = u_s1_write_way_oh[9] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_10 = u_s1_write_way_oh[10] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_11 = u_s1_write_way_oh[11] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_12 = u_s1_write_way_oh[12] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_13 = u_s1_write_way_oh[13] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_14 = u_s1_write_way_oh[14] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_15 = u_s1_write_way_oh[15] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_16 = u_s1_write_way_oh[16] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_17 = u_s1_write_way_oh[17] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_18 = u_s1_write_way_oh[18] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_19 = u_s1_write_way_oh[19] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_20 = u_s1_write_way_oh[20] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_21 = u_s1_write_way_oh[21] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_22 = u_s1_write_way_oh[22] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_23 = u_s1_write_way_oh[23] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_24 = u_s1_write_way_oh[24] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_25 = u_s1_write_way_oh[25] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_26 = u_s1_write_way_oh[26] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_27 = u_s1_write_way_oh[27] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_28 = u_s1_write_way_oh[28] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_29 = u_s1_write_way_oh[29] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_30 = u_s1_write_way_oh[30] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + wire u_s1_ways_write_valid_31 = u_s1_write_way_oh[31] & u_s1_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94}] + reg u_s1_br_update_valids_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:162:40] + reg u_s1_br_update_valids_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:162:40] + reg u_s1_br_takens_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + reg u_s1_br_takens_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + reg io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg io_perf_0_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + reg io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35] + reg io_perf_1_value_REG_1; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27] + wire [40:0] _GEN_3 = {5'h0, _reset_vector_delay_io_out}; // @[src/main/scala/xiangshan/frontend/BPU.scala:192:39, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, utility/src/main/scala/utility/Hold.scala:100:23] wire [31:0] u_s0_hit_oh = {_ways_31_io_update_hit, _ways_30_io_update_hit, @@ -2282,7 +2289,7 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 _ways_3_io_update_hit, _ways_2_io_update_hit, _ways_1_io_update_hit, - _ways_0_io_update_hit}; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :139:56 + _ways_0_io_update_hit}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :139:56] wire [14:0] _s1_hit_way_T_1 = {_ways_31_io_resp_hit, _ways_30_io_resp_hit, @@ -2313,9 +2320,9 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 _ways_4_io_resp_hit, _ways_3_io_resp_hit, _ways_2_io_resp_hit, - _ways_1_io_resp_hit}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - wire [6:0] _s1_hit_way_T_3 = _s1_hit_way_T_1[14:8] | _s1_hit_way_T_1[6:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 - wire [2:0] _s1_hit_way_T_5 = _s1_hit_way_T_3[6:4] | _s1_hit_way_T_3[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + _ways_1_io_resp_hit}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + wire [6:0] _s1_hit_way_T_3 = _s1_hit_way_T_1[14:8] | _s1_hit_way_T_1[6:0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] + wire [2:0] _s1_hit_way_T_5 = _s1_hit_way_T_3[6:4] | _s1_hit_way_T_3[2:0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] wire [4:0] s1_hit_way = {|{_ways_31_io_resp_hit, _ways_30_io_resp_hit, @@ -2336,75 +2343,79 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 |(_s1_hit_way_T_1[14:7]), |(_s1_hit_way_T_3[6:3]), |(_s1_hit_way_T_5[2:1]), - _s1_hit_way_T_5[2] | _s1_hit_way_T_5[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 - always @(posedge clock) begin - if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - s1_pc_dup_0 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_1 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_2 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 - s1_pc_dup_3 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + _s1_hit_way_T_5[2] | _s1_hit_way_T_5[0]}; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + if (REG_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + s1_pc_dup_0 <= _GEN_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_1 <= _GEN_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_2 <= _GEN_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] + s1_pc_dup_3 <= _GEN_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, :192:39] end - else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 - if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 - if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + else begin // @[src/main/scala/xiangshan/frontend/BPU.scala:191:16] + if (io_s0_fire_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_2) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] + if (io_s0_fire_3) // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86] end - REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 - REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} - fauftb_enable <= io_ctrl_ubtb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:116:30 - if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - resp_meta_hit_r <= |s1_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :122:39 - resp_meta_pred_way_r <= s1_hit_way; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:123:44 + REG <= reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24] + REG_1 <= REG & ~reset; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24,39,42}] + fauftb_enable <= io_ctrl_ubtb_enable; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:116:30] + if (io_s1_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + resp_meta_hit_r <= |s1_hit_oh; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :122:39] + resp_meta_pred_way_r <= s1_hit_way; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:123:44] end - if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - resp_meta_hit_r_1 <= resp_meta_hit_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:{29,39} - resp_meta_pred_way_r_1 <= resp_meta_pred_way_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:{34,44} + if (io_s2_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + resp_meta_hit_r_1 <= resp_meta_hit_r; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:122:{29,39}] + resp_meta_pred_way_r_1 <= resp_meta_pred_way_r; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:123:{34,44}] end - replacer_touch_ways_0_valid_REG <= io_s1_fire_0 & (|s1_hit_oh); // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :127:{42,54} - if (io_s1_fire_0 & (|s1_hit_oh)) // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :128:68 - replacer_touch_ways_0_bits_r <= s1_hit_way; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 - u_s1_valid <= io_update_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 - if (io_update_valid) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 - u_s1_tag <= io_update_bits_pc[16:1]; // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28, :148:33 - u_s1_hit_oh <= u_s0_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :149:33 - u_s1_hit <= |u_s0_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :140:30, :150:33 - u_s1_ftb_entry_brSlots_0_offset <= io_update_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_brSlots_0_lower <= io_update_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_brSlots_0_tarStat <= io_update_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_brSlots_0_valid <= io_update_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_tailSlot_offset <= io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_tailSlot_lower <= io_update_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_tailSlot_tarStat <= io_update_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_tailSlot_sharing <= io_update_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_tailSlot_valid <= io_update_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_pftAddr <= io_update_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_carry <= io_update_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_always_taken_0 <= io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - u_s1_ftb_entry_always_taken_1 <= io_update_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + replacer_touch_ways_0_valid_REG <= io_s1_fire_0 & (|s1_hit_oh); // @[src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :127:{42,54}] + if (io_s1_fire_0 & (|s1_hit_oh)) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :128:68] + replacer_touch_ways_0_bits_r <= s1_hit_way; // @[src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44] + u_s1_valid <= io_update_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27] + if (io_update_valid) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14] + u_s1_tag <= io_update_bits_pc[16:1]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28, :148:33] + u_s1_hit_oh <= u_s0_hit_oh; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :149:33] + u_s1_hit <= |u_s0_hit_oh; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :140:30, :150:33] + u_s1_ftb_entry_brSlots_0_offset <= io_update_bits_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_brSlots_0_lower <= io_update_bits_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_brSlots_0_tarStat <= io_update_bits_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_brSlots_0_valid <= io_update_bits_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_tailSlot_offset <= io_update_bits_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_tailSlot_lower <= io_update_bits_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_tailSlot_tarStat <= io_update_bits_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_tailSlot_sharing <= io_update_bits_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_tailSlot_valid <= io_update_bits_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_pftAddr <= io_update_bits_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_carry <= io_update_bits_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_always_taken_0 <= io_update_bits_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + u_s1_ftb_entry_always_taken_1 <= io_update_bits_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] u_s1_br_update_valids_0 <= io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid - & ~io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:143:{47,50}, :162:40 + & ~io_update_bits_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:143:{47,50}, :162:40] u_s1_br_update_valids_1 <= io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_tailSlot_sharing & io_update_valid - & ~io_update_bits_ftb_entry_always_taken_1 & ~io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:143:{50,84}, :144:7, :162:40 - u_s1_br_takens_0 <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - u_s1_br_takens_1 <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + & ~io_update_bits_ftb_entry_always_taken_1 & ~io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:143:{50,84}, :144:7, :162:40] + u_s1_br_takens_0 <= io_update_bits_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + u_s1_br_takens_1 <= io_update_bits_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] end + io_perf_0_value_REG <= io_update_valid & io_update_bits_meta[0]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FauFTB.scala:136:36, :185:65] + io_perf_0_value_REG_1 <= io_perf_0_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] + io_perf_1_value_REG <= io_update_valid & ~(io_update_bits_meta[0]); // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FauFTB.scala:136:36, :189:53, :199:42] + io_perf_1_value_REG_1 <= io_perf_1_value_REG; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{27,35}] end // always @(posedge) wire [14:0] _replacer_touch_ways_1_bits_T_1 = - u_s1_write_way_oh[31:17] | u_s1_write_way_oh[15:1]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30 + u_s1_write_way_oh[31:17] | u_s1_write_way_oh[15:1]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30] wire [6:0] _replacer_touch_ways_1_bits_T_3 = - _replacer_touch_ways_1_bits_T_1[14:8] | _replacer_touch_ways_1_bits_T_1[6:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + _replacer_touch_ways_1_bits_T_1[14:8] | _replacer_touch_ways_1_bits_T_1[6:0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _replacer_touch_ways_1_bits_T_5 = - _replacer_touch_ways_1_bits_T_3[6:4] | _replacer_touch_ways_1_bits_T_3[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + _replacer_touch_ways_1_bits_T_3[6:4] | _replacer_touch_ways_1_bits_T_3[2:0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] wire _replacer_touch_ways_1_bits_T_7 = - _replacer_touch_ways_1_bits_T_5[2] | _replacer_touch_ways_1_bits_T_5[0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + _replacer_touch_ways_1_bits_T_5[2] | _replacer_touch_ways_1_bits_T_5[0]; // @[src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28] wire [14:0] _state_reg_T_52 = replacer_touch_ways_0_bits_r[4] ? {~(replacer_touch_ways_0_bits_r[3]), @@ -2450,7 +2461,7 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 replacer_touch_ways_0_bits_r[1] ? state_reg[15] : ~(replacer_touch_ways_0_bits_r[0])}}} - : state_reg[29:15]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + : state_reg[29:15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44] wire [14:0] _state_reg_T_105 = replacer_touch_ways_0_bits_r[4] ? state_reg[14:0] @@ -2496,722 +2507,722 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 : state_reg[1], replacer_touch_ways_0_bits_r[1] ? state_reg[0] - : ~(replacer_touch_ways_0_bits_r[0])}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + : ~(replacer_touch_ways_0_bits_r[0])}}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44] wire [29:0] _state_reg_T_107 = replacer_touch_ways_0_valid_REG ? {_state_reg_T_52, _state_reg_T_105} - : state_reg[29:0]; // rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 - always @(posedge clock or posedge reset) begin - if (reset) begin - ctrs_0_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_0_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_1_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_1_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_2_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_2_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_3_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_3_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_4_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_4_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_5_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_5_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_6_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_6_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_7_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_7_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_8_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_8_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_9_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_9_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_10_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_10_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_11_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_11_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_12_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_12_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_13_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_13_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_14_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_14_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_15_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_15_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_16_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_16_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_17_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_17_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_18_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_18_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_19_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_19_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_20_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_20_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_21_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_21_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_22_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_22_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_23_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_23_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_24_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_24_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_25_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_25_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_26_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_26_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_27_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_27_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_28_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_28_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_29_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_29_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_30_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_30_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_31_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_31_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - state_reg <= 31'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + : state_reg[29:0]; // @[rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42] + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + if (reset) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + ctrs_0_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_0_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_1_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_1_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_2_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_2_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_3_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_3_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_4_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_4_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_5_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_5_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_6_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_6_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_7_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_7_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_8_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_8_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_9_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_9_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_10_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_10_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_11_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_11_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_12_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_12_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_13_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_13_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_14_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_14_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_15_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_15_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_16_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_16_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_17_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_17_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_18_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_18_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_19_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_19_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_20_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_20_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_21_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_21_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_22_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_22_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_23_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_23_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_24_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_24_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_25_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_25_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_26_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_26_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_27_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_27_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_28_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_28_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_29_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_29_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_30_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_30_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_31_0 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_31_1 <= 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + state_reg <= 31'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end - else begin - if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_0_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_0_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_0_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_0_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_0_0 <= 2'(ctrs_0_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_0_0 <= 2'(ctrs_0_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_0_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_0_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_0_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_0_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_0_0 <= 2'(ctrs_0_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_0_0 <= 2'(ctrs_0_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_0_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_0_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_0_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_0_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_0_1 <= 2'(ctrs_0_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_0_1 <= 2'(ctrs_0_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_0_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_0_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_0_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_0_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_0_1 <= 2'(ctrs_0_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_0_1 <= 2'(ctrs_0_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_1_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_1_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_1_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_1_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_1_0 <= 2'(ctrs_1_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_1_0 <= 2'(ctrs_1_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_1_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_1_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_1_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_1_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_1_0 <= 2'(ctrs_1_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_1_0 <= 2'(ctrs_1_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_1_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_1_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_1_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_1_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_1_1 <= 2'(ctrs_1_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_1_1 <= 2'(ctrs_1_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_1_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_1_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_1_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_1_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_1_1 <= 2'(ctrs_1_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_1_1 <= 2'(ctrs_1_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_2_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_2_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_2_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_2_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_2_0 <= 2'(ctrs_2_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_2_0 <= 2'(ctrs_2_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_2_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_2_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_2_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_2_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_2_0 <= 2'(ctrs_2_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_2_0 <= 2'(ctrs_2_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_2_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_2_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_2_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_2_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_2_1 <= 2'(ctrs_2_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_2_1 <= 2'(ctrs_2_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_2_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_2_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_2_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_2_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_2_1 <= 2'(ctrs_2_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_2_1 <= 2'(ctrs_2_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_3_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_3_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_3_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_3_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_3_0 <= 2'(ctrs_3_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_3_0 <= 2'(ctrs_3_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_3_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_3_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_3_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_3_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_3_0 <= 2'(ctrs_3_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_3_0 <= 2'(ctrs_3_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_3_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_3_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_3_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_3_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_3_1 <= 2'(ctrs_3_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_3_1 <= 2'(ctrs_3_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_3_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_3_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_3_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_3_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_3_1 <= 2'(ctrs_3_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_3_1 <= 2'(ctrs_3_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_4_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_4_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_4_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_4_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_4_0 <= 2'(ctrs_4_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_4_0 <= 2'(ctrs_4_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_4_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_4_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_4_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_4_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_4_0 <= 2'(ctrs_4_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_4_0 <= 2'(ctrs_4_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_4_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_4_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_4_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_4_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_4_1 <= 2'(ctrs_4_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_4_1 <= 2'(ctrs_4_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_4_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_4_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_4_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_4_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_4_1 <= 2'(ctrs_4_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_4_1 <= 2'(ctrs_4_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_5_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_5_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_5_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_5_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_5_0 <= 2'(ctrs_5_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_5_0 <= 2'(ctrs_5_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_5_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_5_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_5_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_5_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_5_0 <= 2'(ctrs_5_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_5_0 <= 2'(ctrs_5_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_5_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_5_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_5_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_5_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_5_1 <= 2'(ctrs_5_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_5_1 <= 2'(ctrs_5_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_5_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_5_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_5_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_5_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_5_1 <= 2'(ctrs_5_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_5_1 <= 2'(ctrs_5_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_6_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_6_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_6_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_6_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_6_0 <= 2'(ctrs_6_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_6_0 <= 2'(ctrs_6_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_6_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_6_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_6_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_6_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_6_0 <= 2'(ctrs_6_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_6_0 <= 2'(ctrs_6_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_6_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_6_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_6_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_6_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_6_1 <= 2'(ctrs_6_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_6_1 <= 2'(ctrs_6_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_6_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_6_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_6_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_6_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_6_1 <= 2'(ctrs_6_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_6_1 <= 2'(ctrs_6_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_7_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_7_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_7_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_7_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_7_0 <= 2'(ctrs_7_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_7_0 <= 2'(ctrs_7_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_7_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_7_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_7_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_7_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_7_0 <= 2'(ctrs_7_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_7_0 <= 2'(ctrs_7_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_7_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_7_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_7_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_7_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_7_1 <= 2'(ctrs_7_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_7_1 <= 2'(ctrs_7_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_7_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_7_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_7_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_7_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_7_1 <= 2'(ctrs_7_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_7_1 <= 2'(ctrs_7_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_8_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_8_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_8_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_8_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_8_0 <= 2'(ctrs_8_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_8_0 <= 2'(ctrs_8_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_8_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_8_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_8_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_8_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_8_0 <= 2'(ctrs_8_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_8_0 <= 2'(ctrs_8_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_8_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_8_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_8_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_8_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_8_1 <= 2'(ctrs_8_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_8_1 <= 2'(ctrs_8_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_8_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_8_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_8_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_8_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_8_1 <= 2'(ctrs_8_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_8_1 <= 2'(ctrs_8_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_9_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_9_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_9_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_9_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_9_0 <= 2'(ctrs_9_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_9_0 <= 2'(ctrs_9_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_9_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_9_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_9_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_9_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_9_0 <= 2'(ctrs_9_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_9_0 <= 2'(ctrs_9_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_9_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_9_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_9_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_9_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_9_1 <= 2'(ctrs_9_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_9_1 <= 2'(ctrs_9_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_9_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_9_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_9_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_9_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_9_1 <= 2'(ctrs_9_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_9_1 <= 2'(ctrs_9_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_10_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_10_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_10_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_10_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_10_0 <= 2'(ctrs_10_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_10_0 <= 2'(ctrs_10_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_10_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_10_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_10_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_10_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_10_0 <= 2'(ctrs_10_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_10_0 <= 2'(ctrs_10_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_10_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_10_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_10_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_10_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_10_1 <= 2'(ctrs_10_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_10_1 <= 2'(ctrs_10_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_10_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_10_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_10_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_10_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_10_1 <= 2'(ctrs_10_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_10_1 <= 2'(ctrs_10_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_11_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_11_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_11_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_11_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_11_0 <= 2'(ctrs_11_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_11_0 <= 2'(ctrs_11_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_11_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_11_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_11_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_11_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_11_0 <= 2'(ctrs_11_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_11_0 <= 2'(ctrs_11_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_11_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_11_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_11_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_11_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_11_1 <= 2'(ctrs_11_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_11_1 <= 2'(ctrs_11_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_11_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_11_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_11_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_11_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_11_1 <= 2'(ctrs_11_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_11_1 <= 2'(ctrs_11_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_12_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_12_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_12_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_12_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_12_0 <= 2'(ctrs_12_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_12_0 <= 2'(ctrs_12_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_12_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_12_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_12_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_12_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_12_0 <= 2'(ctrs_12_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_12_0 <= 2'(ctrs_12_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_12_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_12_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_12_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_12_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_12_1 <= 2'(ctrs_12_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_12_1 <= 2'(ctrs_12_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_12_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_12_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_12_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_12_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_12_1 <= 2'(ctrs_12_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_12_1 <= 2'(ctrs_12_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_13_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_13_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_13_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_13_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_13_0 <= 2'(ctrs_13_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_13_0 <= 2'(ctrs_13_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_13_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_13_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_13_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_13_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_13_0 <= 2'(ctrs_13_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_13_0 <= 2'(ctrs_13_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_13_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_13_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_13_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_13_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_13_1 <= 2'(ctrs_13_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_13_1 <= 2'(ctrs_13_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_13_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_13_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_13_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_13_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_13_1 <= 2'(ctrs_13_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_13_1 <= 2'(ctrs_13_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_14_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_14_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_14_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_14_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_14_0 <= 2'(ctrs_14_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_14_0 <= 2'(ctrs_14_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_14_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_14_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_14_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_14_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_14_0 <= 2'(ctrs_14_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_14_0 <= 2'(ctrs_14_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_14_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_14_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_14_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_14_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_14_1 <= 2'(ctrs_14_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_14_1 <= 2'(ctrs_14_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_14_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_14_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_14_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_14_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_14_1 <= 2'(ctrs_14_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_14_1 <= 2'(ctrs_14_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_15_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_15_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_15_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_15_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_15_0 <= 2'(ctrs_15_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_15_0 <= 2'(ctrs_15_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_15_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_15_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_15_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_15_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_15_0 <= 2'(ctrs_15_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_15_0 <= 2'(ctrs_15_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_15_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_15_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_15_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_15_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_15_1 <= 2'(ctrs_15_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_15_1 <= 2'(ctrs_15_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_15_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_15_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_15_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_15_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_15_1 <= 2'(ctrs_15_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_15_1 <= 2'(ctrs_15_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_16_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_16_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_16_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_16_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_16_0 <= 2'(ctrs_16_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_16_0 <= 2'(ctrs_16_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_16_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_16_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_16_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_16_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_16_0 <= 2'(ctrs_16_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_16_0 <= 2'(ctrs_16_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_16_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_16_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_16_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_16_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_16_1 <= 2'(ctrs_16_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_16_1 <= 2'(ctrs_16_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_16_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_16_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_16_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_16_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_16_1 <= 2'(ctrs_16_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_16_1 <= 2'(ctrs_16_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_17_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_17_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_17_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_17_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_17_0 <= 2'(ctrs_17_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_17_0 <= 2'(ctrs_17_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_17_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_17_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_17_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_17_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_17_0 <= 2'(ctrs_17_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_17_0 <= 2'(ctrs_17_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_17_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_17_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_17_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_17_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_17_1 <= 2'(ctrs_17_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_17_1 <= 2'(ctrs_17_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_17_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_17_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_17_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_17_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_17_1 <= 2'(ctrs_17_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_17_1 <= 2'(ctrs_17_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_18_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_18_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_18_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_18_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_18_0 <= 2'(ctrs_18_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_18_0 <= 2'(ctrs_18_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_18_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_18_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_18_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_18_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_18_0 <= 2'(ctrs_18_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_18_0 <= 2'(ctrs_18_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_18_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_18_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_18_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_18_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_18_1 <= 2'(ctrs_18_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_18_1 <= 2'(ctrs_18_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_18_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_18_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_18_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_18_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_18_1 <= 2'(ctrs_18_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_18_1 <= 2'(ctrs_18_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_19_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_19_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_19_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_19_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_19_0 <= 2'(ctrs_19_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_19_0 <= 2'(ctrs_19_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_19_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_19_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_19_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_19_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_19_0 <= 2'(ctrs_19_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_19_0 <= 2'(ctrs_19_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_19_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_19_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_19_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_19_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_19_1 <= 2'(ctrs_19_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_19_1 <= 2'(ctrs_19_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_19_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_19_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_19_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_19_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_19_1 <= 2'(ctrs_19_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_19_1 <= 2'(ctrs_19_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_20_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_20_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_20_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_20_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_20_0 <= 2'(ctrs_20_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_20_0 <= 2'(ctrs_20_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_20_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_20_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_20_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_20_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_20_0 <= 2'(ctrs_20_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_20_0 <= 2'(ctrs_20_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_20_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_20_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_20_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_20_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_20_1 <= 2'(ctrs_20_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_20_1 <= 2'(ctrs_20_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_20_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_20_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_20_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_20_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_20_1 <= 2'(ctrs_20_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_20_1 <= 2'(ctrs_20_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_21_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_21_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_21_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_21_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_21_0 <= 2'(ctrs_21_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_21_0 <= 2'(ctrs_21_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_21_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_21_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_21_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_21_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_21_0 <= 2'(ctrs_21_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_21_0 <= 2'(ctrs_21_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_21_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_21_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_21_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_21_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_21_1 <= 2'(ctrs_21_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_21_1 <= 2'(ctrs_21_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_21_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_21_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_21_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_21_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_21_1 <= 2'(ctrs_21_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_21_1 <= 2'(ctrs_21_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_22_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_22_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_22_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_22_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_22_0 <= 2'(ctrs_22_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_22_0 <= 2'(ctrs_22_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_22_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_22_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_22_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_22_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_22_0 <= 2'(ctrs_22_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_22_0 <= 2'(ctrs_22_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_22_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_22_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_22_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_22_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_22_1 <= 2'(ctrs_22_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_22_1 <= 2'(ctrs_22_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_22_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_22_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_22_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_22_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_22_1 <= 2'(ctrs_22_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_22_1 <= 2'(ctrs_22_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_23_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_23_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_23_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_23_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_23_0 <= 2'(ctrs_23_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_23_0 <= 2'(ctrs_23_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_23_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_23_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_23_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_23_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_23_0 <= 2'(ctrs_23_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_23_0 <= 2'(ctrs_23_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_23_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_23_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_23_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_23_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_23_1 <= 2'(ctrs_23_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_23_1 <= 2'(ctrs_23_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_23_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_23_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_23_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_23_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_23_1 <= 2'(ctrs_23_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_23_1 <= 2'(ctrs_23_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_24_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_24_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_24_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_24_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_24_0 <= 2'(ctrs_24_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_24_0 <= 2'(ctrs_24_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_24_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_24_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_24_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_24_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_24_0 <= 2'(ctrs_24_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_24_0 <= 2'(ctrs_24_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_24_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_24_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_24_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_24_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_24_1 <= 2'(ctrs_24_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_24_1 <= 2'(ctrs_24_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_24_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_24_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_24_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_24_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_24_1 <= 2'(ctrs_24_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_24_1 <= 2'(ctrs_24_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_25_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_25_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_25_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_25_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_25_0 <= 2'(ctrs_25_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_25_0 <= 2'(ctrs_25_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_25_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_25_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_25_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_25_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_25_0 <= 2'(ctrs_25_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_25_0 <= 2'(ctrs_25_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_25_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_25_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_25_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_25_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_25_1 <= 2'(ctrs_25_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_25_1 <= 2'(ctrs_25_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_25_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_25_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_25_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_25_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_25_1 <= 2'(ctrs_25_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_25_1 <= 2'(ctrs_25_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_26_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_26_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_26_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_26_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_26_0 <= 2'(ctrs_26_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_26_0 <= 2'(ctrs_26_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_26_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_26_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_26_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_26_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_26_0 <= 2'(ctrs_26_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_26_0 <= 2'(ctrs_26_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_26_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_26_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_26_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_26_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_26_1 <= 2'(ctrs_26_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_26_1 <= 2'(ctrs_26_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_26_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_26_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_26_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_26_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_26_1 <= 2'(ctrs_26_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_26_1 <= 2'(ctrs_26_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_27_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_27_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_27_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_27_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_27_0 <= 2'(ctrs_27_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_27_0 <= 2'(ctrs_27_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_27_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_27_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_27_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_27_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_27_0 <= 2'(ctrs_27_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_27_0 <= 2'(ctrs_27_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_27_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_27_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_27_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_27_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_27_1 <= 2'(ctrs_27_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_27_1 <= 2'(ctrs_27_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_27_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_27_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_27_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_27_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_27_1 <= 2'(ctrs_27_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_27_1 <= 2'(ctrs_27_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_28_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_28_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_28_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_28_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_28_0 <= 2'(ctrs_28_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_28_0 <= 2'(ctrs_28_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_28_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_28_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_28_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_28_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_28_0 <= 2'(ctrs_28_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_28_0 <= 2'(ctrs_28_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_28_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_28_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_28_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_28_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_28_1 <= 2'(ctrs_28_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_28_1 <= 2'(ctrs_28_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_28_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_28_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_28_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_28_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_28_1 <= 2'(ctrs_28_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_28_1 <= 2'(ctrs_28_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_29_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_29_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_29_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_29_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_29_0 <= 2'(ctrs_29_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_29_0 <= 2'(ctrs_29_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_29_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_29_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_29_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_29_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_29_0 <= 2'(ctrs_29_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_29_0 <= 2'(ctrs_29_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_29_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_29_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_29_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_29_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_29_1 <= 2'(ctrs_29_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_29_1 <= 2'(ctrs_29_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_29_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_29_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_29_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_29_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_29_1 <= 2'(ctrs_29_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_29_1 <= 2'(ctrs_29_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_30_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_30_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_30_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_30_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_30_0 <= 2'(ctrs_30_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_30_0 <= 2'(ctrs_30_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_30_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_30_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_30_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_30_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_30_0 <= 2'(ctrs_30_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_30_0 <= 2'(ctrs_30_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_30_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_30_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_30_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_30_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_30_1 <= 2'(ctrs_30_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_30_1 <= 2'(ctrs_30_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_30_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_30_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_30_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_30_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_30_1 <= 2'(ctrs_30_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_30_1 <= 2'(ctrs_30_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_31_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_31_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_31_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_31_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_31_0 <= 2'(ctrs_31_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_31_0 <= 2'(ctrs_31_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_0) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_31_0) & u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_31_0 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_31_0 == 2'h0 & ~u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_31_0 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_0) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_31_0 <= 2'(ctrs_31_0 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_31_0 <= 2'(ctrs_31_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 - if ((&ctrs_31_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_31_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (ctrs_31_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 - ctrs_31_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_31_1 <= 2'(ctrs_31_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 - ctrs_31_1 <= 2'(ctrs_31_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_1) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23] + if ((&ctrs_31_1) & u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_31_1 <= 2'h3; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (ctrs_31_1 == 2'h0 & ~u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40] + ctrs_31_1 <= 2'h0; // @[src/main/scala/xiangshan/frontend/BPU.scala:98:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else if (u_s1_br_takens_1) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_31_1 <= 2'(ctrs_31_1 + 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:163:40] + ctrs_31_1 <= 2'(ctrs_31_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] end - if (replacer_touch_ways_0_valid_REG | u_s1_valid) begin // rocket-chip/src/main/scala/util/package.scala:73:59, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42, :147:27 - if (u_s1_valid) // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 + if (replacer_touch_ways_0_valid_REG | u_s1_valid) begin // @[rocket-chip/src/main/scala/util/package.scala:73:59, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42, :147:27] + if (u_s1_valid) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:147:27] state_reg <= {~(|(u_s1_write_way_oh[31:16])), (|(u_s1_write_way_oh[31:16])) @@ -3303,207 +3314,211 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 : _state_reg_T_107[1], (|(_replacer_touch_ways_1_bits_T_5[2:1])) ? _state_reg_T_107[0] - : ~_replacer_touch_ways_1_bits_T_7}}}}; // rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :196:33, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30 - else if (replacer_touch_ways_0_valid_REG) // src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 + : ~_replacer_touch_ways_1_bits_T_7}}}}; // @[rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :196:33, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30] + else if (replacer_touch_ways_0_valid_REG) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:127:42] state_reg <= - {~(replacer_touch_ways_0_bits_r[4]), _state_reg_T_52, _state_reg_T_105}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + {~(replacer_touch_ways_0_bits_r[4]), _state_reg_T_52, _state_reg_T_105}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44] end end end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:23]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - initial begin // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + logic [31:0] _RANDOM[0:24]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + initial begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - for (logic [4:0] i = 5'h0; i < 5'h18; i += 5'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - end // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - s1_pc_dup_1 = {_RANDOM[5'h1][31:7], _RANDOM[5'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - s1_pc_dup_2 = {_RANDOM[5'h2][31:14], _RANDOM[5'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - s1_pc_dup_3 = {_RANDOM[5'h3][31:21], _RANDOM[5'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - REG = _RANDOM[5'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - REG_1 = _RANDOM[5'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24}, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - ctrs_0_0 = _RANDOM[5'hE][23:22]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_0_1 = _RANDOM[5'hE][25:24]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_1_0 = _RANDOM[5'hE][27:26]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_1_1 = _RANDOM[5'hE][29:28]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_2_0 = _RANDOM[5'hE][31:30]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_2_1 = _RANDOM[5'hF][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_3_0 = _RANDOM[5'hF][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_3_1 = _RANDOM[5'hF][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_4_0 = _RANDOM[5'hF][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_4_1 = _RANDOM[5'hF][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_5_0 = _RANDOM[5'hF][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_5_1 = _RANDOM[5'hF][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_6_0 = _RANDOM[5'hF][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_6_1 = _RANDOM[5'hF][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_7_0 = _RANDOM[5'hF][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_7_1 = _RANDOM[5'hF][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_8_0 = _RANDOM[5'hF][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_8_1 = _RANDOM[5'hF][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_9_0 = _RANDOM[5'hF][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_9_1 = _RANDOM[5'hF][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_10_0 = _RANDOM[5'hF][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_10_1 = _RANDOM[5'h10][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_11_0 = _RANDOM[5'h10][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_11_1 = _RANDOM[5'h10][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_12_0 = _RANDOM[5'h10][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_12_1 = _RANDOM[5'h10][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_13_0 = _RANDOM[5'h10][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_13_1 = _RANDOM[5'h10][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_14_0 = _RANDOM[5'h10][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_14_1 = _RANDOM[5'h10][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_15_0 = _RANDOM[5'h10][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_15_1 = _RANDOM[5'h10][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_16_0 = _RANDOM[5'h10][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_16_1 = _RANDOM[5'h10][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_17_0 = _RANDOM[5'h10][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_17_1 = _RANDOM[5'h10][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_18_0 = _RANDOM[5'h10][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_18_1 = _RANDOM[5'h11][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_19_0 = _RANDOM[5'h11][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_19_1 = _RANDOM[5'h11][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_20_0 = _RANDOM[5'h11][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_20_1 = _RANDOM[5'h11][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_21_0 = _RANDOM[5'h11][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_21_1 = _RANDOM[5'h11][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_22_0 = _RANDOM[5'h11][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_22_1 = _RANDOM[5'h11][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_23_0 = _RANDOM[5'h11][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_23_1 = _RANDOM[5'h11][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_24_0 = _RANDOM[5'h11][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_24_1 = _RANDOM[5'h11][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_25_0 = _RANDOM[5'h11][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_25_1 = _RANDOM[5'h11][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_26_0 = _RANDOM[5'h11][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_26_1 = _RANDOM[5'h12][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_27_0 = _RANDOM[5'h12][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_27_1 = _RANDOM[5'h12][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_28_0 = _RANDOM[5'h12][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_28_1 = _RANDOM[5'h12][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_29_0 = _RANDOM[5'h12][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_29_1 = _RANDOM[5'h12][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_30_0 = _RANDOM[5'h12][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_30_1 = _RANDOM[5'h12][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_31_0 = _RANDOM[5'h12][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - ctrs_31_1 = _RANDOM[5'h12][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - state_reg = {_RANDOM[5'h12][31:22], _RANDOM[5'h13][20:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 - fauftb_enable = _RANDOM[5'h13][21]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :116:30 - resp_meta_hit_r = _RANDOM[5'h13][22]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:39 - resp_meta_hit_r_1 = _RANDOM[5'h13][23]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:29 - resp_meta_pred_way_r = _RANDOM[5'h13][28:24]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:44 - resp_meta_pred_way_r_1 = {_RANDOM[5'h13][31:29], _RANDOM[5'h14][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34 - replacer_touch_ways_0_valid_REG = _RANDOM[5'h14][2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :127:42 - replacer_touch_ways_0_bits_r = _RANDOM[5'h14][7:3]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :128:44 - u_s1_valid = _RANDOM[5'h14][8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :147:27 - u_s1_tag = _RANDOM[5'h14][24:9]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :148:33 - u_s1_hit_oh = {_RANDOM[5'h14][31:25], _RANDOM[5'h15][24:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :149:33 - u_s1_hit = _RANDOM[5'h15][25]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :150:33 - u_s1_ftb_entry_brSlots_0_offset = _RANDOM[5'h15][30:27]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33 - u_s1_ftb_entry_brSlots_0_lower = {_RANDOM[5'h15][31], _RANDOM[5'h16][10:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33 - u_s1_ftb_entry_brSlots_0_tarStat = _RANDOM[5'h16][12:11]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_brSlots_0_valid = _RANDOM[5'h16][14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_tailSlot_offset = _RANDOM[5'h16][18:15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_tailSlot_lower = {_RANDOM[5'h16][31:19], _RANDOM[5'h17][6:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_tailSlot_tarStat = _RANDOM[5'h17][8:7]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_tailSlot_sharing = _RANDOM[5'h17][9]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_tailSlot_valid = _RANDOM[5'h17][10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_pftAddr = _RANDOM[5'h17][14:11]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_carry = _RANDOM[5'h17][15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_always_taken_0 = _RANDOM[5'h17][20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_ftb_entry_always_taken_1 = _RANDOM[5'h17][21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 - u_s1_br_update_valids_0 = _RANDOM[5'h17][22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40 - u_s1_br_update_valids_1 = _RANDOM[5'h17][23]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40 - u_s1_br_takens_0 = _RANDOM[5'h17][24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40 - u_s1_br_takens_1 = _RANDOM[5'h17][25]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + for (logic [4:0] i = 5'h0; i < 5'h19; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + end // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]}; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + REG = _RANDOM[5'hF][12]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + REG_1 = _RANDOM[5'hF][13]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:{16,24}, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + ctrs_0_0 = _RANDOM[5'hF][15:14]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_0_1 = _RANDOM[5'hF][17:16]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_1_0 = _RANDOM[5'hF][19:18]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_1_1 = _RANDOM[5'hF][21:20]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_2_0 = _RANDOM[5'hF][23:22]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_2_1 = _RANDOM[5'hF][25:24]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_3_0 = _RANDOM[5'hF][27:26]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_3_1 = _RANDOM[5'hF][29:28]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_4_0 = _RANDOM[5'hF][31:30]; // @[src/main/scala/xiangshan/frontend/BPU.scala:191:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_4_1 = _RANDOM[5'h10][1:0]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_5_0 = _RANDOM[5'h10][3:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_5_1 = _RANDOM[5'h10][5:4]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_6_0 = _RANDOM[5'h10][7:6]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_6_1 = _RANDOM[5'h10][9:8]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_7_0 = _RANDOM[5'h10][11:10]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_7_1 = _RANDOM[5'h10][13:12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_8_0 = _RANDOM[5'h10][15:14]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_8_1 = _RANDOM[5'h10][17:16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_9_0 = _RANDOM[5'h10][19:18]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_9_1 = _RANDOM[5'h10][21:20]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_10_0 = _RANDOM[5'h10][23:22]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_10_1 = _RANDOM[5'h10][25:24]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_11_0 = _RANDOM[5'h10][27:26]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_11_1 = _RANDOM[5'h10][29:28]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_12_0 = _RANDOM[5'h10][31:30]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_12_1 = _RANDOM[5'h11][1:0]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_13_0 = _RANDOM[5'h11][3:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_13_1 = _RANDOM[5'h11][5:4]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_14_0 = _RANDOM[5'h11][7:6]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_14_1 = _RANDOM[5'h11][9:8]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_15_0 = _RANDOM[5'h11][11:10]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_15_1 = _RANDOM[5'h11][13:12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_16_0 = _RANDOM[5'h11][15:14]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_16_1 = _RANDOM[5'h11][17:16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_17_0 = _RANDOM[5'h11][19:18]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_17_1 = _RANDOM[5'h11][21:20]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_18_0 = _RANDOM[5'h11][23:22]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_18_1 = _RANDOM[5'h11][25:24]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_19_0 = _RANDOM[5'h11][27:26]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_19_1 = _RANDOM[5'h11][29:28]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_20_0 = _RANDOM[5'h11][31:30]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_20_1 = _RANDOM[5'h12][1:0]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_21_0 = _RANDOM[5'h12][3:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_21_1 = _RANDOM[5'h12][5:4]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_22_0 = _RANDOM[5'h12][7:6]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_22_1 = _RANDOM[5'h12][9:8]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_23_0 = _RANDOM[5'h12][11:10]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_23_1 = _RANDOM[5'h12][13:12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_24_0 = _RANDOM[5'h12][15:14]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_24_1 = _RANDOM[5'h12][17:16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_25_0 = _RANDOM[5'h12][19:18]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_25_1 = _RANDOM[5'h12][21:20]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_26_0 = _RANDOM[5'h12][23:22]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_26_1 = _RANDOM[5'h12][25:24]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_27_0 = _RANDOM[5'h12][27:26]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_27_1 = _RANDOM[5'h12][29:28]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_28_0 = _RANDOM[5'h12][31:30]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_28_1 = _RANDOM[5'h13][1:0]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_29_0 = _RANDOM[5'h13][3:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_29_1 = _RANDOM[5'h13][5:4]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_30_0 = _RANDOM[5'h13][7:6]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_30_1 = _RANDOM[5'h13][9:8]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_31_0 = _RANDOM[5'h13][11:10]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + ctrs_31_1 = _RANDOM[5'h13][13:12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + state_reg = {_RANDOM[5'h13][31:14], _RANDOM[5'h14][12:0]}; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73] + fauftb_enable = _RANDOM[5'h14][13]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :116:30] + resp_meta_hit_r = _RANDOM[5'h14][14]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:39] + resp_meta_hit_r_1 = _RANDOM[5'h14][15]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:29] + resp_meta_pred_way_r = _RANDOM[5'h14][20:16]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:44] + resp_meta_pred_way_r_1 = _RANDOM[5'h14][25:21]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34] + replacer_touch_ways_0_valid_REG = _RANDOM[5'h14][26]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :127:42] + replacer_touch_ways_0_bits_r = _RANDOM[5'h14][31:27]; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :128:44] + u_s1_valid = _RANDOM[5'h15][0]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :147:27] + u_s1_tag = _RANDOM[5'h15][16:1]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :147:27, :148:33] + u_s1_hit_oh = {_RANDOM[5'h15][31:17], _RANDOM[5'h16][16:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :147:27, :149:33] + u_s1_hit = _RANDOM[5'h16][17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :150:33] + u_s1_ftb_entry_brSlots_0_offset = _RANDOM[5'h16][22:19]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33] + u_s1_ftb_entry_brSlots_0_lower = {_RANDOM[5'h16][31:23], _RANDOM[5'h17][2:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33] + u_s1_ftb_entry_brSlots_0_tarStat = _RANDOM[5'h17][4:3]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_brSlots_0_valid = _RANDOM[5'h17][6]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_tailSlot_offset = _RANDOM[5'h17][10:7]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_tailSlot_lower = _RANDOM[5'h17][30:11]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_tailSlot_tarStat = {_RANDOM[5'h17][31], _RANDOM[5'h18][0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_tailSlot_sharing = _RANDOM[5'h18][1]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_tailSlot_valid = _RANDOM[5'h18][2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_pftAddr = _RANDOM[5'h18][6:3]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_carry = _RANDOM[5'h18][7]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_always_taken_0 = _RANDOM[5'h18][12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_ftb_entry_always_taken_1 = _RANDOM[5'h18][13]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + u_s1_br_update_valids_0 = _RANDOM[5'h18][14]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40] + u_s1_br_update_valids_1 = _RANDOM[5'h18][15]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40] + u_s1_br_takens_0 = _RANDOM[5'h18][16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40] + u_s1_br_takens_1 = _RANDOM[5'h18][17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40] + io_perf_0_value_REG = _RANDOM[5'h18][19]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + io_perf_0_value_REG_1 = _RANDOM[5'h18][20]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + io_perf_1_value_REG = _RANDOM[5'h18][21]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:35, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] + io_perf_1_value_REG_1 = _RANDOM[5'h18][22]; // @[src/main/scala/utils/PerfCounterUtils.scala:325:27, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33] `endif // RANDOMIZE_REG_INIT - if (reset) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - ctrs_0_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_0_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_1_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_1_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_2_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_2_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_3_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_3_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_4_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_4_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_5_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_5_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_6_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_6_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_7_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_7_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_8_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_8_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_9_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_9_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_10_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_10_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_11_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_11_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_12_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_12_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_13_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_13_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_14_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_14_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_15_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_15_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_16_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_16_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_17_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_17_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_18_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_18_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_19_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_19_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_20_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_20_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_21_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_21_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_22_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_22_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_23_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_23_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_24_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_24_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_25_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_25_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_26_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_26_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_27_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_27_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_28_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_28_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_29_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_29_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_30_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_30_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_31_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - ctrs_31_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 - state_reg = 31'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + if (reset) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + ctrs_0_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_0_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_1_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_1_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_2_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_2_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_3_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_3_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_4_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_4_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_5_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_5_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_6_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_6_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_7_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_7_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_8_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_8_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_9_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_9_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_10_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_10_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_11_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_11_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_12_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_12_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_13_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_13_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_14_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_14_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_15_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_15_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_16_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_16_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_17_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_17_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_18_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_18_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_19_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_19_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_20_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_20_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_21_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_21_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_22_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_22_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_23_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_23_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_24_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_24_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_25_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_25_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_26_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_26_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_27_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_27_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_28_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_28_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_29_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_29_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_30_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_30_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_31_0 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + ctrs_31_1 = 2'h2; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:92:73] + state_reg = 31'h0; // @[rocket-chip/src/main/scala/util/Replacement.scala:168:72] end end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + DelayN_2 reset_vector_delay ( // @[utility/src/main/scala/utility/Hold.scala:100:23] .clock (clock), .io_in (io_reset_vector), .io_out (_reset_vector_delay_io_out) ); - FauFTBWay ways_0 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_0 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_0_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_0_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_0_io_resp_brSlots_0_tarStat), @@ -3518,28 +3533,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_0_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_0_io_resp_always_taken_1), .io_resp_hit (_ways_0_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_0_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_1 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_1 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_1_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_1_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_1_io_resp_brSlots_0_tarStat), @@ -3554,28 +3569,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_1_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_1_io_resp_always_taken_1), .io_resp_hit (_ways_1_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_1_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_2 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_2 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_2_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_2_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_2_io_resp_brSlots_0_tarStat), @@ -3590,28 +3605,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_2_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_2_io_resp_always_taken_1), .io_resp_hit (_ways_2_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_2_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_2), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_2), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_3 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_3 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_3_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_3_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_3_io_resp_brSlots_0_tarStat), @@ -3626,28 +3641,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_3_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_3_io_resp_always_taken_1), .io_resp_hit (_ways_3_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_3_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_3), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_3), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_4 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_4 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_4_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_4_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_4_io_resp_brSlots_0_tarStat), @@ -3662,28 +3677,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_4_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_4_io_resp_always_taken_1), .io_resp_hit (_ways_4_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_4_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_4), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_4), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_5 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_5 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_5_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_5_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_5_io_resp_brSlots_0_tarStat), @@ -3698,28 +3713,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_5_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_5_io_resp_always_taken_1), .io_resp_hit (_ways_5_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_5_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_5), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_5), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_6 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_6 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_6_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_6_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_6_io_resp_brSlots_0_tarStat), @@ -3734,28 +3749,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_6_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_6_io_resp_always_taken_1), .io_resp_hit (_ways_6_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_6_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_6), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_6), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_7 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_7 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_7_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_7_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_7_io_resp_brSlots_0_tarStat), @@ -3770,28 +3785,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_7_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_7_io_resp_always_taken_1), .io_resp_hit (_ways_7_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_7_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_7), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_7), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_8 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_8 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_8_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_8_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_8_io_resp_brSlots_0_tarStat), @@ -3806,28 +3821,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_8_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_8_io_resp_always_taken_1), .io_resp_hit (_ways_8_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_8_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_8), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_8), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_9 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_9 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_9_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_9_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_9_io_resp_brSlots_0_tarStat), @@ -3842,28 +3857,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_9_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_9_io_resp_always_taken_1), .io_resp_hit (_ways_9_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_9_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_9), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_9), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_10 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_10 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_10_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_10_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_10_io_resp_brSlots_0_tarStat), @@ -3878,28 +3893,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_10_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_10_io_resp_always_taken_1), .io_resp_hit (_ways_10_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_10_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_10), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_10), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_11 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_11 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_11_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_11_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_11_io_resp_brSlots_0_tarStat), @@ -3914,28 +3929,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_11_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_11_io_resp_always_taken_1), .io_resp_hit (_ways_11_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_11_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_11), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_11), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_12 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_12 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_12_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_12_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_12_io_resp_brSlots_0_tarStat), @@ -3950,28 +3965,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_12_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_12_io_resp_always_taken_1), .io_resp_hit (_ways_12_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_12_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_12), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_12), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_13 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_13 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_13_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_13_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_13_io_resp_brSlots_0_tarStat), @@ -3986,28 +4001,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_13_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_13_io_resp_always_taken_1), .io_resp_hit (_ways_13_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_13_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_13), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_13), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_14 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_14 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_14_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_14_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_14_io_resp_brSlots_0_tarStat), @@ -4022,28 +4037,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_14_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_14_io_resp_always_taken_1), .io_resp_hit (_ways_14_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_14_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_14), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_14), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_15 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_15 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_15_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_15_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_15_io_resp_brSlots_0_tarStat), @@ -4058,28 +4073,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_15_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_15_io_resp_always_taken_1), .io_resp_hit (_ways_15_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_15_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_15), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_15), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_16 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_16 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_16_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_16_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_16_io_resp_brSlots_0_tarStat), @@ -4094,28 +4109,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_16_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_16_io_resp_always_taken_1), .io_resp_hit (_ways_16_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_16_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_16), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_16), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_17 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_17 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_17_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_17_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_17_io_resp_brSlots_0_tarStat), @@ -4130,28 +4145,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_17_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_17_io_resp_always_taken_1), .io_resp_hit (_ways_17_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_17_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_17), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_17), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_18 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_18 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_18_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_18_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_18_io_resp_brSlots_0_tarStat), @@ -4166,28 +4181,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_18_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_18_io_resp_always_taken_1), .io_resp_hit (_ways_18_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_18_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_18), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_18), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_19 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_19 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_19_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_19_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_19_io_resp_brSlots_0_tarStat), @@ -4202,28 +4217,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_19_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_19_io_resp_always_taken_1), .io_resp_hit (_ways_19_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_19_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_19), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_19), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_20 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_20 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_20_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_20_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_20_io_resp_brSlots_0_tarStat), @@ -4238,28 +4253,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_20_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_20_io_resp_always_taken_1), .io_resp_hit (_ways_20_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_20_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_20), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_20), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_21 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_21 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_21_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_21_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_21_io_resp_brSlots_0_tarStat), @@ -4274,28 +4289,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_21_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_21_io_resp_always_taken_1), .io_resp_hit (_ways_21_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_21_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_21), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_21), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_22 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_22 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_22_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_22_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_22_io_resp_brSlots_0_tarStat), @@ -4310,28 +4325,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_22_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_22_io_resp_always_taken_1), .io_resp_hit (_ways_22_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_22_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_22), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_22), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_23 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_23 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_23_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_23_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_23_io_resp_brSlots_0_tarStat), @@ -4346,28 +4361,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_23_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_23_io_resp_always_taken_1), .io_resp_hit (_ways_23_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_23_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_23), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_23), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_24 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_24 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_24_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_24_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_24_io_resp_brSlots_0_tarStat), @@ -4382,28 +4397,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_24_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_24_io_resp_always_taken_1), .io_resp_hit (_ways_24_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_24_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_24), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_24), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_25 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_25 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_25_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_25_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_25_io_resp_brSlots_0_tarStat), @@ -4418,28 +4433,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_25_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_25_io_resp_always_taken_1), .io_resp_hit (_ways_25_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_25_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_25), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_25), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_26 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_26 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_26_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_26_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_26_io_resp_brSlots_0_tarStat), @@ -4454,28 +4469,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_26_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_26_io_resp_always_taken_1), .io_resp_hit (_ways_26_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_26_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_26), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_26), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_27 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_27 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_27_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_27_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_27_io_resp_brSlots_0_tarStat), @@ -4490,28 +4505,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_27_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_27_io_resp_always_taken_1), .io_resp_hit (_ways_27_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_27_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_27), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_27), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_28 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_28 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_28_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_28_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_28_io_resp_brSlots_0_tarStat), @@ -4526,28 +4541,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_28_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_28_io_resp_always_taken_1), .io_resp_hit (_ways_28_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_28_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_28), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_28), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_29 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_29 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_29_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_29_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_29_io_resp_brSlots_0_tarStat), @@ -4562,28 +4577,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_29_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_29_io_resp_always_taken_1), .io_resp_hit (_ways_29_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_29_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_29), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_29), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_30 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_30 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_30_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_30_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_30_io_resp_brSlots_0_tarStat), @@ -4598,28 +4613,28 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_30_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_30_io_resp_always_taken_1), .io_resp_hit (_ways_30_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_30_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_30), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_30), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - FauFTBWay ways_31 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + FauFTBWay ways_31 ( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:90:47] .clock (clock), .reset (reset), - .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_req_tag (s1_pc_dup_0[16:1]), // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_resp_brSlots_0_offset (_ways_31_io_resp_brSlots_0_offset), .io_resp_brSlots_0_lower (_ways_31_io_resp_brSlots_0_lower), .io_resp_brSlots_0_tarStat (_ways_31_io_resp_brSlots_0_tarStat), @@ -4634,70 +4649,70 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 .io_resp_always_taken_0 (_ways_31_io_resp_always_taken_0), .io_resp_always_taken_1 (_ways_31_io_resp_always_taken_1), .io_resp_hit (_ways_31_io_resp_hit), - .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_req_tag (io_update_bits_pc[16:1]), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:39:28] .io_update_hit (_ways_31_io_update_hit), - .io_write_valid (u_s1_ways_write_valid_31), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 - .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 - .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + .io_write_valid (u_s1_ways_write_valid_31), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:154:94] + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_carry (u_s1_ftb_entry_carry), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // @[src/main/scala/xiangshan/frontend/FauFTB.scala:153:33] + .io_write_tag (u_s1_tag) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:148:33] ); - assign io_out_s1_pc_0 = s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_pc_1 = s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_pc_2 = s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_pc_3 = s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_0_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 - assign io_out_s1_full_pred_1_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_1_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 - assign io_out_s1_full_pred_2_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_2_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 - assign io_out_s1_full_pred_3_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_pc_0 = s1_pc_dup_0; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_pc_1 = s1_pc_dup_1; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_pc_2 = s1_pc_dup_2; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_pc_3 = s1_pc_dup_3; // @[src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_br_taken_mask_0 = _s1_hit_full_pred_T_1102; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_br_taken_mask_1 = _s1_hit_full_pred_T_1165; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_slot_valids_0 = _s1_hit_full_pred_T_976; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_slot_valids_1 = _s1_hit_full_pred_T_1039; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_targets_0 = _s1_hit_full_pred_T_850; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_targets_1 = _s1_hit_full_pred_T_913; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_offsets_0 = _s1_hit_full_pred_T_661; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_offsets_1 = _s1_hit_full_pred_T_724; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_fallThroughAddr = _s1_hit_full_pred_T_598; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_is_br_sharing = _s1_hit_full_pred_T_157; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_0_hit = io_out_s1_full_pred_3_hit_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44] + assign io_out_s1_full_pred_1_br_taken_mask_0 = _s1_hit_full_pred_T_1102; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_br_taken_mask_1 = _s1_hit_full_pred_T_1165; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_slot_valids_0 = _s1_hit_full_pred_T_976; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_slot_valids_1 = _s1_hit_full_pred_T_1039; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_targets_0 = _s1_hit_full_pred_T_850; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_targets_1 = _s1_hit_full_pred_T_913; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_offsets_0 = _s1_hit_full_pred_T_661; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_offsets_1 = _s1_hit_full_pred_T_724; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_fallThroughAddr = _s1_hit_full_pred_T_598; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_is_br_sharing = _s1_hit_full_pred_T_157; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_1_hit = io_out_s1_full_pred_3_hit_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44] + assign io_out_s1_full_pred_2_br_taken_mask_0 = _s1_hit_full_pred_T_1102; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_br_taken_mask_1 = _s1_hit_full_pred_T_1165; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_slot_valids_0 = _s1_hit_full_pred_T_976; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_slot_valids_1 = _s1_hit_full_pred_T_1039; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_targets_0 = _s1_hit_full_pred_T_850; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_targets_1 = _s1_hit_full_pred_T_913; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_offsets_0 = _s1_hit_full_pred_T_661; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_offsets_1 = _s1_hit_full_pred_T_724; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_fallThroughAddr = _s1_hit_full_pred_T_598; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_is_br_sharing = _s1_hit_full_pred_T_157; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_2_hit = io_out_s1_full_pred_3_hit_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44] + assign io_out_s1_full_pred_3_br_taken_mask_0 = _s1_hit_full_pred_T_1102; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_br_taken_mask_1 = _s1_hit_full_pred_T_1165; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_slot_valids_0 = _s1_hit_full_pred_T_976; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_slot_valids_1 = _s1_hit_full_pred_T_1039; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_targets_0 = _s1_hit_full_pred_T_850; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_targets_1 = _s1_hit_full_pred_T_913; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_offsets_0 = _s1_hit_full_pred_T_661; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_offsets_1 = _s1_hit_full_pred_T_724; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_fallThroughAddr = _s1_hit_full_pred_T_598; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] assign io_out_s1_full_pred_3_fallThroughErr = _ways_0_io_resp_hit & s1_possible_full_preds_0_fallThroughErr | _ways_1_io_resp_hit & s1_possible_full_preds_1_fallThroughErr | _ways_2_io_resp_hit @@ -4730,9 +4745,11 @@ module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 & s1_possible_full_preds_28_fallThroughErr | _ways_29_io_resp_hit & s1_possible_full_preds_29_fallThroughErr | _ways_30_io_resp_hit & s1_possible_full_preds_30_fallThroughErr | _ways_31_io_resp_hit - & s1_possible_full_preds_31_fallThroughErr; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 - assign io_out_s1_full_pred_3_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 - assign io_out_s1_full_pred_3_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 - assign io_out_last_stage_meta = {213'h0, resp_meta_pred_way_r_1, resp_meta_hit_r_1}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :121:26, :122:29, :123:34 + & s1_possible_full_preds_31_fallThroughErr; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:34] + assign io_out_s1_full_pred_3_is_br_sharing = _s1_hit_full_pred_T_157; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_out_s1_full_pred_3_hit = io_out_s1_full_pred_3_hit_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44] + assign io_out_last_stage_meta = {217'h0, resp_meta_pred_way_r_1, resp_meta_hit_r_1}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :121:26, :122:29, :123:34] + assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] + assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1}; // @[src/main/scala/utils/PerfCounterUtils.scala:325:{17,27}, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7] endmodule diff --git a/rtl/uFTB/FauFTBWay.sv b/rtl/uFTB/FauFTBWay.sv index 2d84b56..50da21a 100644 --- a/rtl/uFTB/FauFTBWay.sv +++ b/rtl/uFTB/FauFTBWay.sv @@ -1,4 +1,4 @@ -// Generated by CIRCT firtool-1.61.0 +// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for register randomization. `ifndef RANDOMIZE `ifdef RANDOMIZE_MEM_INIT @@ -55,133 +55,133 @@ `endif // not def ENABLE_INITIAL_MEM_ `endif // not def SYNTHESIS -module FauFTBWay( // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - input clock, - input reset, - input [15:0] io_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [3:0] io_resp_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [11:0] io_resp_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [1:0] io_resp_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [3:0] io_resp_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [19:0] io_resp_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [1:0] io_resp_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output [3:0] io_resp_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_resp_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [15:0] io_update_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - output io_update_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [3:0] io_write_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [11:0] io_write_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [1:0] io_write_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [3:0] io_write_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [19:0] io_write_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [1:0] io_write_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [3:0] io_write_entry_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input io_write_entry_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - input [15:0] io_write_tag // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 +module FauFTBWay( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + input clock, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + input reset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + input [15:0] io_req_tag, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [3:0] io_resp_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [11:0] io_resp_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [1:0] io_resp_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [3:0] io_resp_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [19:0] io_resp_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [1:0] io_resp_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output [3:0] io_resp_pftAddr, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_carry, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_always_taken_0, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_always_taken_1, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_resp_hit, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [15:0] io_update_req_tag, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + output io_update_hit, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [3:0] io_write_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [11:0] io_write_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [1:0] io_write_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [3:0] io_write_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [19:0] io_write_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [1:0] io_write_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [3:0] io_write_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_carry, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input io_write_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + input [15:0] io_write_tag // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] ); - reg [3:0] data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [11:0] data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [1:0] data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [3:0] data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [19:0] data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [1:0] data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [3:0] data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - reg [15:0] tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16 - reg valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 - always @(posedge clock) begin - if (io_write_valid) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 - data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_tailSlot_offset <= io_write_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_tailSlot_lower <= io_write_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_tailSlot_valid <= io_write_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_pftAddr <= io_write_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_carry <= io_write_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_always_taken_0 <= io_write_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - data_always_taken_1 <= io_write_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 - tag <= io_write_tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16 + reg [3:0] data_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [11:0] data_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [1:0] data_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [3:0] data_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [19:0] data_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [1:0] data_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [3:0] data_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg data_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + reg [15:0] tag; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:58:16] + reg valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22] + always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + if (io_write_valid) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14] + data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_tailSlot_offset <= io_write_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_tailSlot_lower <= io_write_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_tailSlot_valid <= io_write_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_pftAddr <= io_write_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_carry <= io_write_entry_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_always_taken_0 <= io_write_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + data_always_taken_1 <= io_write_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17] + tag <= io_write_tag; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:58:16] end end // always @(posedge) - always @(posedge clock or posedge reset) begin - if (reset) - valid <= 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 - else - valid <= io_write_valid & ~valid | valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22, :68:25, :69:{11,19}, :70:13 + always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + if (reset) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + valid <= 1'h0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22] + else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + valid <= io_write_valid & ~valid | valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22, :68:25, :69:{11,19}, :70:13] end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + `ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + `FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - initial begin // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + logic [31:0] _RANDOM[0:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + initial begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + `ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + `INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - end // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - data_brSlots_0_offset = _RANDOM[2'h0][4:1]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_brSlots_0_lower = _RANDOM[2'h0][16:5]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_brSlots_0_valid = _RANDOM[2'h0][20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_tailSlot_offset = _RANDOM[2'h0][24:21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_tailSlot_sharing = _RANDOM[2'h1][15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_tailSlot_valid = _RANDOM[2'h1][16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_pftAddr = _RANDOM[2'h1][20:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_carry = _RANDOM[2'h1][21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_always_taken_0 = _RANDOM[2'h1][26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - data_always_taken_1 = _RANDOM[2'h1][27]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17, :58:16 - valid = _RANDOM[2'h2][12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22 + _RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + end // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + data_brSlots_0_offset = _RANDOM[2'h0][4:1]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_brSlots_0_lower = _RANDOM[2'h0][16:5]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_brSlots_0_valid = _RANDOM[2'h0][20]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_tailSlot_offset = _RANDOM[2'h0][24:21]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_tailSlot_sharing = _RANDOM[2'h1][15]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_tailSlot_valid = _RANDOM[2'h1][16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_pftAddr = _RANDOM[2'h1][20:17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_carry = _RANDOM[2'h1][21]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_always_taken_0 = _RANDOM[2'h1][26]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + data_always_taken_1 = _RANDOM[2'h1][27]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17, :58:16] + valid = _RANDOM[2'h2][12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22] `endif // RANDOMIZE_REG_INIT - if (reset) // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - valid = 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 + if (reset) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + valid = 1'h0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22] end // initial - `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 - `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] + `FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7] `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_resp_brSlots_0_offset = data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_brSlots_0_lower = data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_brSlots_0_valid = data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_tailSlot_offset = data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_tailSlot_lower = data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_tailSlot_sharing = data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_tailSlot_valid = data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_pftAddr = data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_carry = data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_always_taken_0 = data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_always_taken_1 = data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 - assign io_resp_hit = tag == io_req_tag & valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :62:{22,37} + assign io_resp_brSlots_0_offset = data_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_brSlots_0_lower = data_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_brSlots_0_valid = data_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_tailSlot_offset = data_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_tailSlot_lower = data_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_tailSlot_sharing = data_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_tailSlot_valid = data_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_pftAddr = data_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_carry = data_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_always_taken_0 = data_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_always_taken_1 = data_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17] + assign io_resp_hit = tag == io_req_tag & valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :62:{22,37}] assign io_update_hit = - tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :64:{26,49,59}, :65:{35,58} + tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :64:{26,49,59}, :65:{35,58}] endmodule